guangzong/stm32-data
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

rcc: cleanup f4, f7 plls.

Browse Source
This commit is contained in:
Dario Nieuwenhuis 2023-10-18 05:08:14 +02:00
parent 6f7449303b
commit 5b04234fbe
2 changed files with 84 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

74
data/registers/rcc_f4.yaml
View File

@ -1581,11 +1581,11 @@ fieldset/DCKCFGR:
bit_offset: 25 bit_offset: 25
bit_size: 2 bit_size: 2
enum: ISSRC enum: ISSRC
- name: CK48MSEL - name: CLK48SEL
description: 48 MHz clock source selection description: 48 MHz clock source selection
bit_offset: 27 bit_offset: 27
bit_size: 1 bit_size: 1
enum: CKMSEL enum: CLK48SEL
- name: I2S2SRC - name: I2S2SRC
description: I2S APB2 clocks source selection (I2S1/4/5) description: I2S APB2 clocks source selection (I2S1/4/5)
bit_offset: 27 bit_offset: 27
@ -1619,11 +1619,11 @@ fieldset/DCKCFGR2:
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
enum: CECSEL enum: CECSEL
- name: CK48MSEL - name: CLK48SEL
description: SDIO/USB clock selection description: SDIO/USB clock selection
bit_offset: 27 bit_offset: 27
bit_size: 1 bit_size: 1
enum: CKMSEL enum: CLK48SEL
- name: SDIOSEL - name: SDIOSEL
description: SDIO clock selection description: SDIO clock selection
bit_offset: 28 bit_offset: 28
@ -1675,56 +1675,74 @@ fieldset/PLLCFGR:
fieldset/PLLI2SCFGR: fieldset/PLLI2SCFGR:
description: PLLI2S configuration register description: PLLI2S configuration register
fields: fields:
- name: PLLI2SM - name: PLLM
description: Division factor for the audio PLL (PLLI2S) input clock description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bit_offset: 0 bit_offset: 0
bit_size: 6 bit_size: 6
- name: PLLI2SN enum: PLLM
description: PLLI2S multiplication factor for VCO - name: PLLN
description: Main PLL (PLL) multiplication factor for VCO
bit_offset: 6 bit_offset: 6
bit_size: 9 bit_size: 9
- name: PLLI2SP enum: PLLN
description: PLLI2S division factor for SPDIF-IN clock - name: PLLP
description: Main PLL (PLL) division factor for main system clock
bit_offset: 16 bit_offset: 16
bit_size: 2 bit_size: 2
enum: PLLI2SP enum: PLLP
- name: PLLI2SSRC - name: PLLI2SSRC
description: PLLI2S entry clock source description: PLLI2S entry clock source
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
enum: PLLI2SSRC enum: PLLI2SSRC
- name: PLLI2SQ - name: PLLSRC
description: PLLI2S division factor for USB OTG FS/SDIO/RNG clock description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
bit_offset: 22
bit_size: 1
enum: PLLSRC
- name: PLLQ
description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
bit_offset: 24 bit_offset: 24
bit_size: 4 bit_size: 4
- name: PLLI2SR enum: PLLQ
description: PLLI2S division factor for I2S clocks - name: PLLR
description: PLL division factor for I2S and System clocks
bit_offset: 28 bit_offset: 28
bit_size: 3 bit_size: 3
enum: PLLR
fieldset/PLLSAICFGR: fieldset/PLLSAICFGR:
description: PLL configuration register description: PLL configuration register
fields: fields:
- name: PLLSAIM - name: PLLM
description: Division factor for audio PLLSAI input clock description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bit_offset: 0 bit_offset: 0
bit_size: 6 bit_size: 6
- name: PLLSAIN enum: PLLM
description: PLLSAI division factor for VCO - name: PLLN
description: Main PLL (PLL) multiplication factor for VCO
bit_offset: 6 bit_offset: 6
bit_size: 9 bit_size: 9
- name: PLLSAIP enum: PLLN
description: PLLSAI division factor for 48 MHz clock - name: PLLP
description: Main PLL (PLL) division factor for main system clock
bit_offset: 16 bit_offset: 16
bit_size: 2 bit_size: 2
enum: PLLSAIP enum: PLLP
- name: PLLSAIQ - name: PLLSRC
description: PLLSAI division factor for SAI1 clock description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
bit_offset: 22
bit_size: 1
enum: PLLSRC
- name: PLLQ
description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
bit_offset: 24 bit_offset: 24
bit_size: 4 bit_size: 4
- name: PLLSAIR enum: PLLQ
description: PLLSAI division factor for LCD clock - name: PLLR
description: PLL division factor for I2S and System clocks
bit_offset: 28 bit_offset: 28
bit_size: 3 bit_size: 3
enum: PLLR
fieldset/SSCGR: fieldset/SSCGR:
description: spread spectrum clock generation register description: spread spectrum clock generation register
fields: fields:
@ -1772,7 +1790,7 @@ enum/CKDFSDMSEL:
- name: SYSCLK - name: SYSCLK
description: System clock used as Kernel clock description: System clock used as Kernel clock
value: 1 value: 1
enum/CKMSEL: enum/CLK48SEL:
bit_size: 1 bit_size: 1
variants: variants:
- name: PLL - name: PLL
@ -3434,7 +3452,7 @@ enum/SAIBSRC:
enum/SDIOSEL: enum/SDIOSEL:
bit_size: 1 bit_size: 1
variants: variants:
- name: CK48M - name: CLK48
description: 48 MHz clock is selected as SD clock description: 48 MHz clock is selected as SD clock
value: 0 value: 0
- name: SYSCLK - name: SYSCLK

70
data/registers/rcc_f7.yaml
View File

@ -1280,7 +1280,7 @@ fieldset/CIR:
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: PLLRDYF - name: PLLRDYF
description: Main PLL (PLL) ready interrupt flag description: PLL ready interrupt flag
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
- name: PLLI2SRDYF - name: PLLI2SRDYF
@ -1312,7 +1312,7 @@ fieldset/CIR:
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
- name: PLLRDYIE - name: PLLRDYIE
description: Main PLL (PLL) ready interrupt enable description: PLL ready interrupt enable
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: PLLI2SRDYIE - name: PLLI2SRDYIE
@ -1391,11 +1391,11 @@ fieldset/CR:
bit_offset: 19 bit_offset: 19
bit_size: 1 bit_size: 1
- name: PLLON - name: PLLON
description: Main PLL (PLL) enable description: PLL enable
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: PLLRDY - name: PLLRDY
description: Main PLL (PLL) clock ready flag description: PLL clock ready flag
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: PLLI2SON - name: PLLI2SON
@ -1464,7 +1464,7 @@ fieldset/DCKCFGR1:
description: PLLI2S division factor for SAI1 clock description: PLLI2S division factor for SAI1 clock
bit_offset: 0 bit_offset: 0
bit_size: 5 bit_size: 5
enum: PLLISDIVQ enum: PLLI2SDIVQ
- name: PLLSAIDIVQ - name: PLLSAIDIVQ
description: PLLSAI division factor for SAI1 clock description: PLLSAI division factor for SAI1 clock
bit_offset: 8 bit_offset: 8
@ -1573,7 +1573,7 @@ fieldset/DCKCFGR2:
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
enum: CECSEL enum: CECSEL
- name: CK48MSEL - name: CLK48SEL
description: 48MHz clock source selection description: 48MHz clock source selection
bit_offset: 27 bit_offset: 27
bit_size: 1 bit_size: 1
@ -1597,27 +1597,27 @@ fieldset/PLLCFGR:
description: PLL configuration register description: PLL configuration register
fields: fields:
- name: PLLM - name: PLLM
description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock description: Division factor for the PLL and audio PLL (PLLI2S) input clock
bit_offset: 0 bit_offset: 0
bit_size: 6 bit_size: 6
enum: PLLM enum: PLLM
- name: PLLN - name: PLLN
description: Main PLL (PLL) multiplication factor for VCO description: PLL multiplication factor for VCO
bit_offset: 6 bit_offset: 6
bit_size: 9 bit_size: 9
enum: PLLN enum: PLLN
- name: PLLP - name: PLLP
description: Main PLL (PLL) division factor for main system clock description: PLL division factor for main system clock
bit_offset: 16 bit_offset: 16
bit_size: 2 bit_size: 2
enum: PLLP enum: PLLP
- name: PLLSRC - name: PLLSRC
description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source description: PLL and audio PLL (PLLI2S, PLLSAI) entry clock source
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
enum: PLLSRC enum: PLLSRC
- name: PLLQ - name: PLLQ
description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks description: PLL division factor for USB OTG FS, SDIO and random number generator clocks
bit_offset: 24 bit_offset: 24
bit_size: 4 bit_size: 4
enum: PLLQ enum: PLLQ
@ -1629,43 +1629,49 @@ fieldset/PLLCFGR:
fieldset/PLLI2SCFGR: fieldset/PLLI2SCFGR:
description: PLLI2S configuration register description: PLLI2S configuration register
fields: fields:
- name: PLLI2SN - name: PLLN
description: PLLI2S multiplication factor for VCO description: PLL multiplication factor for VCO
bit_offset: 6 bit_offset: 6
bit_size: 9 bit_size: 9
- name: PLLI2SP enum: PLLN
description: PLLI2S division factor for SPDIFRX clock - name: PLLP
description: PLL division factor for main system clock
bit_offset: 16 bit_offset: 16
bit_size: 2 bit_size: 2
enum: PLLISP enum: PLLP
- name: PLLI2SQ - name: PLLQ
description: PLLI2S division factor for SAI1 clock description: PLL division factor for USB OTG FS, SDIO and random number generator clocks
bit_offset: 24 bit_offset: 24
bit_size: 4 bit_size: 4
- name: PLLI2SR enum: PLLQ
description: PLLI2S division factor for I2S clocks - name: PLLR
description: PLL division factor for DSI clock
bit_offset: 28 bit_offset: 28
bit_size: 3 bit_size: 3
enum: PLLR
fieldset/PLLSAICFGR: fieldset/PLLSAICFGR:
description: PLL configuration register description: PLL configuration register
fields: fields:
- name: PLLSAIN - name: PLLN
description: PLLSAI division factor for VCO description: PLL multiplication factor for VCO
bit_offset: 6 bit_offset: 6
bit_size: 9 bit_size: 9
- name: PLLSAIP enum: PLLN
description: PLLSAI division factor for 48MHz clock - name: PLLP
description: PLL division factor for main system clock
bit_offset: 16 bit_offset: 16
bit_size: 2 bit_size: 2
enum: PLLSAIP enum: PLLP
- name: PLLSAIQ - name: PLLQ
description: PLLSAI division factor for SAI clock description: PLL division factor for USB OTG FS, SDIO and random number generator clocks
bit_offset: 24 bit_offset: 24
bit_size: 4 bit_size: 4
- name: PLLSAIR enum: PLLQ
description: PLLSAI division factor for LCD clock - name: PLLR
description: PLL division factor for DSI clock
bit_offset: 28 bit_offset: 28
bit_size: 3 bit_size: 3
enum: PLLR
fieldset/SSCGR: fieldset/SSCGR:
description: spread spectrum clock generation register description: spread spectrum clock generation register
fields: fields:
@ -1860,7 +1866,7 @@ enum/MCOPRE:
- name: Div5 - name: Div5
description: Division by 5 description: Division by 5
value: 7 value: 7
enum/PLLISDIVQ: enum/PLLI2SDIVQ:
bit_size: 5 bit_size: 5
variants: variants:
- name: Div1 - name: Div1
@ -1959,7 +1965,7 @@ enum/PLLISDIVQ:
- name: Div32 - name: Div32
description: PLLI2SDIVQ = /32 description: PLLI2SDIVQ = /32
value: 31 value: 31
enum/PLLISP: enum/PLLI2SP:
bit_size: 2 bit_size: 2
variants: variants:
- name: Div2 - name: Div2
@ -3120,7 +3126,7 @@ enum/SAISEL:
enum/SDMMCSEL: enum/SDMMCSEL:
bit_size: 1 bit_size: 1
variants: variants:
- name: CK48M - name: CLK48
description: 48 MHz clock is selected as SD clock description: 48 MHz clock is selected as SD clock
value: 0 value: 0
- name: SYSCLK - name: SYSCLK