From 58e92e0670b6969da90172cca8470561f0359366 Mon Sep 17 00:00:00 2001 From: xoviat Date: Sun, 30 Apr 2023 18:01:50 -0500 Subject: [PATCH] add hrtim --- d.ps1 | 2 +- data/registers/hrtim_v1.yaml | 13687 +++++++++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 1 + 3 files changed, 13689 insertions(+), 1 deletion(-) create mode 100644 data/registers/hrtim_v1.yaml diff --git a/d.ps1 b/d.ps1 index 131266f..10d6141 100644 --- a/d.ps1 +++ b/d.ps1 @@ -28,7 +28,7 @@ Switch ($CMD) echo "processing $f ..." chiptool extract-peripheral --svd "sources/svd/stm32$f.svd" --peripheral "$peri" > "tmp/$peri/$f.yaml" 2> "tmp/$peri/$f.err" - if (!$error) { + if ($LASTEXITCODE -eq 0) { rm "tmp/$peri/$f.err" echo OK } else { diff --git a/data/registers/hrtim_v1.yaml b/data/registers/hrtim_v1.yaml new file mode 100644 index 0000000..6ed9372 --- /dev/null +++ b/data/registers/hrtim_v1.yaml @@ -0,0 +1,13687 @@ +block/HRTIM_Master: + description: "High Resolution Timer: Master\r Timers" + items: + - byte_offset: 0 + description: Master Timer Control Register + fieldset: MCR + name: MCR + - access: Read + byte_offset: 4 + description: "Master Timer Interrupt Status\r Register" + fieldset: MISR + name: MISR + - access: Write + byte_offset: 8 + description: "Master Timer Interrupt Clear\r Register" + fieldset: MICR + name: MICR + - byte_offset: 12 + description: MDIER4 + fieldset: MDIER + name: MDIER + - byte_offset: 16 + description: Master Timer Counter Register + fieldset: MCNTR + name: MCNTR + - byte_offset: 20 + description: Master Timer Period Register + fieldset: MPER + name: MPER + - byte_offset: 24 + description: "Master Timer Repetition\r Register" + fieldset: MREP + name: MREP + - byte_offset: 28 + description: "Master Timer Compare 1\r Register" + fieldset: MCMP1R + name: MCMP1R + - byte_offset: 36 + description: "Master Timer Compare 2\r Register" + fieldset: MCMP2R + name: MCMP2R + - byte_offset: 40 + description: "Master Timer Compare 3\r Register" + fieldset: MCMP3R + name: MCMP3R + - byte_offset: 44 + description: "Master Timer Compare 4\r Register" + fieldset: MCMP4R + name: MCMP4R +block/HRTIM_TIMA: + description: 'High Resolution Timer: TIMA' + items: + - byte_offset: 0 + description: Timerx Control Register + fieldset: TIMACR + name: TIMACR + - access: Read + byte_offset: 4 + description: "Timerx Interrupt Status\r Register" + fieldset: TIMAISR + name: TIMAISR + - access: Write + byte_offset: 8 + description: "Timerx Interrupt Clear\r Register" + fieldset: TIMAICR + name: TIMAICR + - byte_offset: 12 + description: TIMxDIER5 + fieldset: TIMADIER + name: TIMADIER + - byte_offset: 16 + description: Timerx Counter Register + fieldset: CNTAR + name: CNTAR + - byte_offset: 20 + description: Timerx Period Register + fieldset: PERAR + name: PERAR + - byte_offset: 24 + description: Timerx Repetition Register + fieldset: REPAR + name: REPAR + - byte_offset: 28 + description: Timerx Compare 1 Register + fieldset: CMP1AR + name: CMP1AR + - byte_offset: 32 + description: "Timerx Compare 1 Compound\r Register" + fieldset: CMP1CAR + name: CMP1CAR + - byte_offset: 36 + description: Timerx Compare 2 Register + fieldset: CMP2AR + name: CMP2AR + - byte_offset: 40 + description: Timerx Compare 3 Register + fieldset: CMP3AR + name: CMP3AR + - byte_offset: 44 + description: Timerx Compare 4 Register + fieldset: CMP4AR + name: CMP4AR + - access: Read + byte_offset: 48 + description: Timerx Capture 1 Register + fieldset: CPT1AR + name: CPT1AR + - access: Read + byte_offset: 52 + description: Timerx Capture 2 Register + fieldset: CPT2AR + name: CPT2AR + - byte_offset: 56 + description: Timerx Deadtime Register + fieldset: DTAR + name: DTAR + - byte_offset: 60 + description: Timerx Output1 Set Register + fieldset: SETA1R + name: SETA1R + - byte_offset: 64 + description: Timerx Output1 Reset Register + fieldset: RSTA1R + name: RSTA1R + - byte_offset: 68 + description: Timerx Output2 Set Register + fieldset: SETA2R + name: SETA2R + - byte_offset: 72 + description: Timerx Output2 Reset Register + fieldset: RSTA2R + name: RSTA2R + - byte_offset: 76 + description: "Timerx External Event Filtering Register\r 1" + fieldset: EEFAR1 + name: EEFAR1 + - byte_offset: 80 + description: "Timerx External Event Filtering Register\r 2" + fieldset: EEFAR2 + name: EEFAR2 + - byte_offset: 84 + description: TimerA Reset Register + fieldset: RSTAR + name: RSTAR + - byte_offset: 88 + description: Timerx Chopper Register + fieldset: CHPAR + name: CHPAR + - byte_offset: 92 + description: "Timerx Capture 2 Control\r Register" + fieldset: CPT1ACR + name: CPT1ACR + - byte_offset: 96 + description: CPT2xCR + fieldset: CPT2ACR + name: CPT2ACR + - byte_offset: 100 + description: Timerx Output Register + fieldset: OUTAR + name: OUTAR + - byte_offset: 104 + description: Timerx Fault Register + fieldset: FLTAR + name: FLTAR +block/HRTIM_TIMB: + description: 'High Resolution Timer: TIMB' + items: + - byte_offset: 0 + description: Timerx Control Register + fieldset: TIMBCR + name: TIMBCR + - access: Read + byte_offset: 4 + description: "Timerx Interrupt Status\r Register" + fieldset: TIMBISR + name: TIMBISR + - access: Write + byte_offset: 8 + description: "Timerx Interrupt Clear\r Register" + fieldset: TIMBICR + name: TIMBICR + - byte_offset: 12 + description: TIMxDIER5 + fieldset: TIMBDIER + name: TIMBDIER + - byte_offset: 16 + description: Timerx Counter Register + fieldset: CNTBR + name: CNTBR + - byte_offset: 20 + description: Timerx Period Register + fieldset: PERBR + name: PERBR + - byte_offset: 24 + description: Timerx Repetition Register + fieldset: REPBR + name: REPBR + - byte_offset: 28 + description: Timerx Compare 1 Register + fieldset: CMP1BR + name: CMP1BR + - byte_offset: 32 + description: "Timerx Compare 1 Compound\r Register" + fieldset: CMP1CBR + name: CMP1CBR + - byte_offset: 36 + description: Timerx Compare 2 Register + fieldset: CMP2BR + name: CMP2BR + - byte_offset: 40 + description: Timerx Compare 3 Register + fieldset: CMP3BR + name: CMP3BR + - byte_offset: 44 + description: Timerx Compare 4 Register + fieldset: CMP4BR + name: CMP4BR + - access: Read + byte_offset: 48 + description: Timerx Capture 1 Register + fieldset: CPT1BR + name: CPT1BR + - access: Read + byte_offset: 52 + description: Timerx Capture 2 Register + fieldset: CPT2BR + name: CPT2BR + - byte_offset: 56 + description: Timerx Deadtime Register + fieldset: DTBR + name: DTBR + - byte_offset: 60 + description: Timerx Output1 Set Register + fieldset: SETB1R + name: SETB1R + - byte_offset: 64 + description: Timerx Output1 Reset Register + fieldset: RSTB1R + name: RSTB1R + - byte_offset: 68 + description: Timerx Output2 Set Register + fieldset: SETB2R + name: SETB2R + - byte_offset: 72 + description: Timerx Output2 Reset Register + fieldset: RSTB2R + name: RSTB2R + - byte_offset: 76 + description: "Timerx External Event Filtering Register\r 1" + fieldset: EEFBR1 + name: EEFBR1 + - byte_offset: 80 + description: "Timerx External Event Filtering Register\r 2" + fieldset: EEFBR2 + name: EEFBR2 + - byte_offset: 84 + description: TimerA Reset Register + fieldset: RSTBR + name: RSTBR + - byte_offset: 88 + description: Timerx Chopper Register + fieldset: CHPBR + name: CHPBR + - byte_offset: 92 + description: "Timerx Capture 2 Control\r Register" + fieldset: CPT1BCR + name: CPT1BCR + - byte_offset: 96 + description: CPT2xCR + fieldset: CPT2BCR + name: CPT2BCR + - byte_offset: 100 + description: Timerx Output Register + fieldset: OUTBR + name: OUTBR + - byte_offset: 104 + description: Timerx Fault Register + fieldset: FLTBR + name: FLTBR +block/HRTIM_TIMC: + description: 'High Resolution Timer: TIMC' + items: + - byte_offset: 0 + description: Timerx Control Register + fieldset: TIMCCR + name: TIMCCR + - access: Read + byte_offset: 4 + description: "Timerx Interrupt Status\r Register" + fieldset: TIMCISR + name: TIMCISR + - access: Write + byte_offset: 8 + description: "Timerx Interrupt Clear\r Register" + fieldset: TIMCICR + name: TIMCICR + - byte_offset: 12 + description: TIMxDIER5 + fieldset: TIMCDIER + name: TIMCDIER + - byte_offset: 16 + description: Timerx Counter Register + fieldset: CNTCR + name: CNTCR + - byte_offset: 20 + description: Timerx Period Register + fieldset: PERCR + name: PERCR + - byte_offset: 24 + description: Timerx Repetition Register + fieldset: REPCR + name: REPCR + - byte_offset: 28 + description: Timerx Compare 1 Register + fieldset: CMP1CR + name: CMP1CR + - byte_offset: 32 + description: "Timerx Compare 1 Compound\r Register" + fieldset: CMP1CCR + name: CMP1CCR + - byte_offset: 36 + description: Timerx Compare 2 Register + fieldset: CMP2CR + name: CMP2CR + - byte_offset: 40 + description: Timerx Compare 3 Register + fieldset: CMP3CR + name: CMP3CR + - byte_offset: 44 + description: Timerx Compare 4 Register + fieldset: CMP4CR + name: CMP4CR + - access: Read + byte_offset: 48 + description: Timerx Capture 1 Register + fieldset: CPT1CR + name: CPT1CR + - access: Read + byte_offset: 52 + description: Timerx Capture 2 Register + fieldset: CPT2CR + name: CPT2CR + - byte_offset: 56 + description: Timerx Deadtime Register + fieldset: DTCR + name: DTCR + - byte_offset: 60 + description: Timerx Output1 Set Register + fieldset: SETC1R + name: SETC1R + - byte_offset: 64 + description: Timerx Output1 Reset Register + fieldset: RSTC1R + name: RSTC1R + - byte_offset: 68 + description: Timerx Output2 Set Register + fieldset: SETC2R + name: SETC2R + - byte_offset: 72 + description: Timerx Output2 Reset Register + fieldset: RSTC2R + name: RSTC2R + - byte_offset: 76 + description: "Timerx External Event Filtering Register\r 1" + fieldset: EEFCR1 + name: EEFCR1 + - byte_offset: 80 + description: "Timerx External Event Filtering Register\r 2" + fieldset: EEFCR2 + name: EEFCR2 + - byte_offset: 84 + description: TimerA Reset Register + fieldset: RSTCR + name: RSTCR + - byte_offset: 88 + description: Timerx Chopper Register + fieldset: CHPCR + name: CHPCR + - byte_offset: 92 + description: "Timerx Capture 2 Control\r Register" + fieldset: CPT1CCR + name: CPT1CCR + - byte_offset: 96 + description: CPT2xCR + fieldset: CPT2CCR + name: CPT2CCR + - byte_offset: 100 + description: Timerx Output Register + fieldset: OUTCR + name: OUTCR + - byte_offset: 104 + description: Timerx Fault Register + fieldset: FLTCR + name: FLTCR +block/HRTIM_TIMD: + description: 'High Resolution Timer: TIMD' + items: + - byte_offset: 0 + description: Timerx Control Register + fieldset: TIMDCR + name: TIMDCR + - access: Read + byte_offset: 4 + description: "Timerx Interrupt Status\r Register" + fieldset: TIMDISR + name: TIMDISR + - access: Write + byte_offset: 8 + description: "Timerx Interrupt Clear\r Register" + fieldset: TIMDICR + name: TIMDICR + - byte_offset: 12 + description: TIMxDIER5 + fieldset: TIMDDIER + name: TIMDDIER + - byte_offset: 16 + description: Timerx Counter Register + fieldset: CNTDR + name: CNTDR + - byte_offset: 20 + description: Timerx Period Register + fieldset: PERDR + name: PERDR + - byte_offset: 24 + description: Timerx Repetition Register + fieldset: REPDR + name: REPDR + - byte_offset: 28 + description: Timerx Compare 1 Register + fieldset: CMP1DR + name: CMP1DR + - byte_offset: 32 + description: "Timerx Compare 1 Compound\r Register" + fieldset: CMP1CDR + name: CMP1CDR + - byte_offset: 36 + description: Timerx Compare 2 Register + fieldset: CMP2DR + name: CMP2DR + - byte_offset: 40 + description: Timerx Compare 3 Register + fieldset: CMP3DR + name: CMP3DR + - byte_offset: 44 + description: Timerx Compare 4 Register + fieldset: CMP4DR + name: CMP4DR + - access: Read + byte_offset: 48 + description: Timerx Capture 1 Register + fieldset: CPT1DR + name: CPT1DR + - access: Read + byte_offset: 52 + description: Timerx Capture 2 Register + fieldset: CPT2DR + name: CPT2DR + - byte_offset: 56 + description: Timerx Deadtime Register + fieldset: DTDR + name: DTDR + - byte_offset: 60 + description: Timerx Output1 Set Register + fieldset: SETD1R + name: SETD1R + - byte_offset: 64 + description: Timerx Output1 Reset Register + fieldset: RSTD1R + name: RSTD1R + - byte_offset: 68 + description: Timerx Output2 Set Register + fieldset: SETD2R + name: SETD2R + - byte_offset: 72 + description: Timerx Output2 Reset Register + fieldset: RSTD2R + name: RSTD2R + - byte_offset: 76 + description: "Timerx External Event Filtering Register\r 1" + fieldset: EEFDR1 + name: EEFDR1 + - byte_offset: 80 + description: "Timerx External Event Filtering Register\r 2" + fieldset: EEFDR2 + name: EEFDR2 + - byte_offset: 84 + description: TimerA Reset Register + fieldset: RSTDR + name: RSTDR + - byte_offset: 88 + description: Timerx Chopper Register + fieldset: CHPDR + name: CHPDR + - byte_offset: 92 + description: "Timerx Capture 2 Control\r Register" + fieldset: CPT1DCR + name: CPT1DCR + - byte_offset: 96 + description: CPT2xCR + fieldset: CPT2DCR + name: CPT2DCR + - byte_offset: 100 + description: Timerx Output Register + fieldset: OUTDR + name: OUTDR + - byte_offset: 104 + description: Timerx Fault Register + fieldset: FLTDR + name: FLTDR +block/HRTIM_TIME: + description: 'High Resolution Timer: TIME' + items: + - byte_offset: 0 + description: Timerx Control Register + fieldset: TIMECR + name: TIMECR + - access: Read + byte_offset: 4 + description: "Timerx Interrupt Status\r Register" + fieldset: TIMEISR + name: TIMEISR + - access: Write + byte_offset: 8 + description: "Timerx Interrupt Clear\r Register" + fieldset: TIMEICR + name: TIMEICR + - byte_offset: 12 + description: TIMxDIER5 + fieldset: TIMEDIER + name: TIMEDIER + - byte_offset: 16 + description: Timerx Counter Register + fieldset: CNTER + name: CNTER + - byte_offset: 20 + description: Timerx Period Register + fieldset: PERER + name: PERER + - byte_offset: 24 + description: Timerx Repetition Register + fieldset: REPER + name: REPER + - byte_offset: 28 + description: Timerx Compare 1 Register + fieldset: CMP1ER + name: CMP1ER + - byte_offset: 32 + description: "Timerx Compare 1 Compound\r Register" + fieldset: CMP1CER + name: CMP1CER + - byte_offset: 36 + description: Timerx Compare 2 Register + fieldset: CMP2ER + name: CMP2ER + - byte_offset: 40 + description: Timerx Compare 3 Register + fieldset: CMP3ER + name: CMP3ER + - byte_offset: 44 + description: Timerx Compare 4 Register + fieldset: CMP4ER + name: CMP4ER + - access: Read + byte_offset: 48 + description: Timerx Capture 1 Register + fieldset: CPT1ER + name: CPT1ER + - access: Read + byte_offset: 52 + description: Timerx Capture 2 Register + fieldset: CPT2ER + name: CPT2ER + - byte_offset: 56 + description: Timerx Deadtime Register + fieldset: DTER + name: DTER + - byte_offset: 60 + description: Timerx Output1 Set Register + fieldset: SETE1R + name: SETE1R + - byte_offset: 64 + description: Timerx Output1 Reset Register + fieldset: RSTE1R + name: RSTE1R + - byte_offset: 68 + description: Timerx Output2 Set Register + fieldset: SETE2R + name: SETE2R + - byte_offset: 72 + description: Timerx Output2 Reset Register + fieldset: RSTE2R + name: RSTE2R + - byte_offset: 76 + description: "Timerx External Event Filtering Register\r 1" + fieldset: EEFER1 + name: EEFER1 + - byte_offset: 80 + description: "Timerx External Event Filtering Register\r 2" + fieldset: EEFER2 + name: EEFER2 + - byte_offset: 84 + description: TimerA Reset Register + fieldset: RSTER + name: RSTER + - byte_offset: 88 + description: Timerx Chopper Register + fieldset: CHPER + name: CHPER + - byte_offset: 92 + description: "Timerx Capture 2 Control\r Register" + fieldset: CPT1ECR + name: CPT1ECR + - byte_offset: 96 + description: CPT2xCR + fieldset: CPT2ECR + name: CPT2ECR + - byte_offset: 100 + description: Timerx Output Register + fieldset: OUTER + name: OUTER + - byte_offset: 104 + description: Timerx Fault Register + fieldset: FLTER + name: FLTER +enum/BRSTDMA: + bit_size: 2 + variants: + - description: Update done independently from the DMA burst transfer completion + name: Independent + value: 0 + - description: Update done when the DMA burst transfer is completed + name: Completion + value: 1 + - description: Update done on master timer roll-over following a DMA burst transfer + completion + name: Rollover + value: 2 +enum/CHP1: + bit_size: 1 + variants: + - description: Output signal not altered + name: Disabled + value: 0 + - description: Output signal is chopped by a carrier signal + name: Enabled + value: 1 +enum/CMP1C: + bit_size: 1 + variants: + - description: Clears associated flag in ISR register + name: Clear + value: 1 +enum/CMP1DE: + bit_size: 1 + variants: + - description: Compare DMA request disabled + name: Disabled + value: 0 + - description: Compare DMA request enabled + name: Enabled + value: 1 +enum/CMP1IE: + bit_size: 1 + variants: + - description: Compare interrupt disabled + name: Disabled + value: 0 + - description: Compare interrupt enabled + name: Enabled + value: 1 +enum/CMP2: + bit_size: 1 + variants: + - description: Timer X compare Z event has no effect + name: NoEffect + value: 0 + - description: Timer X counter is reset upon timer X compare Z event + name: ResetCounter + value: 1 +enum/CONT: + bit_size: 1 + variants: + - description: The timer operates in single-shot mode and stops when it reaches + the MPER value + name: SingleShot + value: 0 + - description: The timer operates in continuous (free-running) mode and rolls over + to zero when it reaches the MPER value + name: Continuous + value: 1 +enum/CPPSTAT: + bit_size: 1 + variants: + - description: Signal applied on output 1 and output 2 forced inactive + name: Output1Active + value: 0 + - description: Signal applied on output 2 and output 1 forced inactive + name: Output2Active + value: 1 +enum/CPT1: + bit_size: 1 + variants: + - description: No timer x capture reset interrupt occurred + name: NoEvent + value: 0 + - description: Timer x capture reset interrupt occurred + name: Event + value: 1 +enum/CPT1ACR_EXEV1CPT: + bit_size: 1 + variants: + - description: External event Y has no effect + name: NoEffect + value: 0 + - description: External event Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1ACR_SWCPT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force capture Z + name: TriggerCapture + value: 1 +enum/CPT1ACR_TB1RST: + bit_size: 1 + variants: + - description: Timer X output Y active to inactive transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y active to inactive transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1ACR_TB1SET: + bit_size: 1 + variants: + - description: Timer X output Y inactive to active transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y inactive to active transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1ACR_TBCMP1: + bit_size: 1 + variants: + - description: Timer X compare Y has no effect + name: NoEffect + value: 0 + - description: Timer X compare Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1ACR_UPDCPT: + bit_size: 1 + variants: + - description: Update event has no effect + name: NoEffect + value: 0 + - description: Update event triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1BCR_EXEV1CPT: + bit_size: 1 + variants: + - description: External event Y has no effect + name: NoEffect + value: 0 + - description: External event Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1BCR_SWCPT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force capture Z + name: TriggerCapture + value: 1 +enum/CPT1BCR_TA1RST: + bit_size: 1 + variants: + - description: Timer X output Y active to inactive transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y active to inactive transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1BCR_TA1SET: + bit_size: 1 + variants: + - description: Timer X output Y inactive to active transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y inactive to active transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1BCR_TACMP1: + bit_size: 1 + variants: + - description: Timer X compare Y has no effect + name: NoEffect + value: 0 + - description: Timer X compare Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1BCR_UPDCPT: + bit_size: 1 + variants: + - description: Update event has no effect + name: NoEffect + value: 0 + - description: Update event triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1CCR_EXEV1CPT: + bit_size: 1 + variants: + - description: External event Y has no effect + name: NoEffect + value: 0 + - description: External event Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1CCR_SWCPT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force capture Z + name: TriggerCapture + value: 1 +enum/CPT1CCR_TA1RST: + bit_size: 1 + variants: + - description: Timer X output Y active to inactive transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y active to inactive transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1CCR_TA1SET: + bit_size: 1 + variants: + - description: Timer X output Y inactive to active transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y inactive to active transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1CCR_TACMP1: + bit_size: 1 + variants: + - description: Timer X compare Y has no effect + name: NoEffect + value: 0 + - description: Timer X compare Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1CCR_UPDCPT: + bit_size: 1 + variants: + - description: Update event has no effect + name: NoEffect + value: 0 + - description: Update event triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1DCR_EXEV1CPT: + bit_size: 1 + variants: + - description: External event Y has no effect + name: NoEffect + value: 0 + - description: External event Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1DCR_SWCPT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force capture Z + name: TriggerCapture + value: 1 +enum/CPT1DCR_TA1RST: + bit_size: 1 + variants: + - description: Timer X output Y active to inactive transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y active to inactive transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1DCR_TA1SET: + bit_size: 1 + variants: + - description: Timer X output Y inactive to active transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y inactive to active transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1DCR_TACMP1: + bit_size: 1 + variants: + - description: Timer X compare Y has no effect + name: NoEffect + value: 0 + - description: Timer X compare Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1DCR_UPDCPT: + bit_size: 1 + variants: + - description: Update event has no effect + name: NoEffect + value: 0 + - description: Update event triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1DE: + bit_size: 1 + variants: + - description: Capture DMA request disabled + name: Disabled + value: 0 + - description: Capture DMA request enabled + name: Enabled + value: 1 +enum/CPT1ECR_EXEV1CPT: + bit_size: 1 + variants: + - description: External event Y has no effect + name: NoEffect + value: 0 + - description: External event Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1ECR_SWCPT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force capture Z + name: TriggerCapture + value: 1 +enum/CPT1ECR_TA1RST: + bit_size: 1 + variants: + - description: Timer X output Y active to inactive transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y active to inactive transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1ECR_TA1SET: + bit_size: 1 + variants: + - description: Timer X output Y inactive to active transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y inactive to active transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1ECR_TACMP1: + bit_size: 1 + variants: + - description: Timer X compare Y has no effect + name: NoEffect + value: 0 + - description: Timer X compare Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1ECR_UPDCPT: + bit_size: 1 + variants: + - description: Update event has no effect + name: NoEffect + value: 0 + - description: Update event triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT1IE: + bit_size: 1 + variants: + - description: Capture interrupt disabled + name: Disabled + value: 0 + - description: Capture interrupt enabled + name: Enabled + value: 1 +enum/CPT2ACR_EXEV1CPT: + bit_size: 1 + variants: + - description: External event Y has no effect + name: NoEffect + value: 0 + - description: External event Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2ACR_SWCPT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force capture Z + name: TriggerCapture + value: 1 +enum/CPT2ACR_TB1RST: + bit_size: 1 + variants: + - description: Timer X output Y active to inactive transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y active to inactive transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2ACR_TB1SET: + bit_size: 1 + variants: + - description: Timer X output Y inactive to active transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y inactive to active transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2ACR_TBCMP1: + bit_size: 1 + variants: + - description: Timer X compare Y has no effect + name: NoEffect + value: 0 + - description: Timer X compare Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2ACR_UPDCPT: + bit_size: 1 + variants: + - description: Update event has no effect + name: NoEffect + value: 0 + - description: Update event triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2BCR_EXEV1CPT: + bit_size: 1 + variants: + - description: External event Y has no effect + name: NoEffect + value: 0 + - description: External event Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2BCR_SWCPT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force capture Z + name: TriggerCapture + value: 1 +enum/CPT2BCR_TA1RST: + bit_size: 1 + variants: + - description: Timer X output Y active to inactive transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y active to inactive transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2BCR_TA1SET: + bit_size: 1 + variants: + - description: Timer X output Y inactive to active transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y inactive to active transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2BCR_TACMP1: + bit_size: 1 + variants: + - description: Timer X compare Y has no effect + name: NoEffect + value: 0 + - description: Timer X compare Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2BCR_UPDCPT: + bit_size: 1 + variants: + - description: Update event has no effect + name: NoEffect + value: 0 + - description: Update event triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2CCR_EXEV1CPT: + bit_size: 1 + variants: + - description: External event Y has no effect + name: NoEffect + value: 0 + - description: External event Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2CCR_SWCPT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force capture Z + name: TriggerCapture + value: 1 +enum/CPT2CCR_TA1RST: + bit_size: 1 + variants: + - description: Timer X output Y active to inactive transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y active to inactive transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2CCR_TA1SET: + bit_size: 1 + variants: + - description: Timer X output Y inactive to active transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y inactive to active transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2CCR_TACMP1: + bit_size: 1 + variants: + - description: Timer X compare Y has no effect + name: NoEffect + value: 0 + - description: Timer X compare Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2CCR_UPDCPT: + bit_size: 1 + variants: + - description: Update event has no effect + name: NoEffect + value: 0 + - description: Update event triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2DCR_EXEV1CPT: + bit_size: 1 + variants: + - description: External event Y has no effect + name: NoEffect + value: 0 + - description: External event Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2DCR_SWCPT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force capture Z + name: TriggerCapture + value: 1 +enum/CPT2DCR_TA1RST: + bit_size: 1 + variants: + - description: Timer X output Y active to inactive transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y active to inactive transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2DCR_TA1SET: + bit_size: 1 + variants: + - description: Timer X output Y inactive to active transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y inactive to active transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2DCR_TACMP1: + bit_size: 1 + variants: + - description: Timer X compare Y has no effect + name: NoEffect + value: 0 + - description: Timer X compare Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2DCR_UPDCPT: + bit_size: 1 + variants: + - description: Update event has no effect + name: NoEffect + value: 0 + - description: Update event triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2ECR_EXEV1CPT: + bit_size: 1 + variants: + - description: External event Y has no effect + name: NoEffect + value: 0 + - description: External event Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2ECR_SWCPT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force capture Z + name: TriggerCapture + value: 1 +enum/CPT2ECR_TA1RST: + bit_size: 1 + variants: + - description: Timer X output Y active to inactive transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y active to inactive transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2ECR_TA1SET: + bit_size: 1 + variants: + - description: Timer X output Y inactive to active transition has no effect + name: NoEffect + value: 0 + - description: Timer X output Y inactive to active transition triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2ECR_TACMP1: + bit_size: 1 + variants: + - description: Timer X compare Y has no effect + name: NoEffect + value: 0 + - description: Timer X compare Y triggers capture Z + name: TriggerCapture + value: 1 +enum/CPT2ECR_UPDCPT: + bit_size: 1 + variants: + - description: Update event has no effect + name: NoEffect + value: 0 + - description: Update event triggers capture Z + name: TriggerCapture + value: 1 +enum/DACSYNC: + bit_size: 2 + variants: + - description: No DAC trigger generated + name: Disabled + value: 0 + - description: Trigger generated on DACSync1 + name: DACSync1 + value: 1 + - description: Trigger generated on DACSync2 + name: DACSync2 + value: 2 + - description: Trigger generated on DACSync3 + name: DACSync3 + value: 3 +enum/DELCMP2: + bit_size: 2 + variants: + - description: CMP2 register is always active (standard compare mode) + name: Standard + value: 0 + - description: CMP2 is recomputed and is active following a capture 1 event + name: Capture1 + value: 1 + - description: CMP2 is recomputed and is active following a capture 1 event or a + Compare 1 match + name: Capture1_Compare1 + value: 2 + - description: CMP2 is recomputed and is active following a capture 1 event or a + Compare 3 match + name: Capture1_Compare3 + value: 3 +enum/DELCMP4: + bit_size: 2 + variants: + - description: CMP4 register is always active (standard compare mode) + name: Standard + value: 0 + - description: CMP4 is recomputed and is active following a capture 2 event + name: Capture2 + value: 1 + - description: CMP4 is recomputed and is active following a capture 2 event or a + Compare 1 match + name: Capture2_Compare1 + value: 2 + - description: CMP4 is recomputed and is active following a capture event or a Compare + 3 match + name: Capture_Compare3 + value: 3 +enum/DIDL1: + bit_size: 1 + variants: + - description: The programmed idle state is applied immediately to the output + name: Disabled + value: 0 + - description: Deadtime (inactive level) is inserted on output before entering the + idle mode + name: Enabled + value: 1 +enum/DLYPRTDE: + bit_size: 1 + variants: + - description: Delayed protection DMA request disabled + name: Disabled + value: 0 + - description: Delayed protection DMA request enabled + name: Enabled + value: 1 +enum/DLYPRTEN: + bit_size: 1 + variants: + - description: No action + name: Disabled + value: 0 + - description: Delayed protection is enabled, as per DLYPRT bits + name: Enabled + value: 1 +enum/DLYPRTIE: + bit_size: 1 + variants: + - description: Delayed protection interrupt disabled + name: Disabled + value: 0 + - description: Delayed protection interrupt enabled + name: Enabled + value: 1 +enum/DTEN: + bit_size: 1 + variants: + - description: Output 1 and 2 signals are independent + name: Disabled + value: 0 + - description: Deadtime is inserted between output 1 and output 2 + name: Enabled + value: 1 +enum/DTFLKx: + bit_size: 1 + variants: + - description: Deadtime falling value and sign is writable + name: Unlocked + value: 0 + - description: Deadtime falling value and sign is read-only + name: Locked + value: 1 +enum/DTFSLKx: + bit_size: 1 + variants: + - description: Deadtime falling sign is writable + name: Unlocked + value: 0 + - description: Deadtime falling sign is read-only + name: Locked + value: 1 +enum/DTRLKx: + bit_size: 1 + variants: + - description: Deadtime rising value and sign is writable + name: Unlocked + value: 0 + - description: Deadtime rising value and sign is read-only + name: Locked + value: 1 +enum/DTRSLKx: + bit_size: 1 + variants: + - description: Deadtime rising sign is writable + name: Unlocked + value: 0 + - description: Deadtime rising sign is read-only + name: Locked + value: 1 +enum/EE1FLTR: + bit_size: 4 + variants: + - description: No filtering + name: Disabled + value: 0 + - description: Blanking from counter reset/roll-over to Compare 1 + name: BlankResetToCompare1 + value: 1 + - description: Blanking from counter reset/roll-over to Compare 2 + name: BlankResetToCompare2 + value: 2 + - description: Blanking from counter reset/roll-over to Compare 3 + name: BlankResetToCompare3 + value: 3 + - description: Blanking from counter reset/roll-over to Compare 4 + name: BlankResetToCompare4 + value: 4 + - description: 'Blanking from another timing unit: TIMFLTR1 source' + name: BlankTIMFLTR1 + value: 5 + - description: 'Blanking from another timing unit: TIMFLTR2 source' + name: BlankTIMFLTR2 + value: 6 + - description: 'Blanking from another timing unit: TIMFLTR3 source' + name: BlankTIMFLTR3 + value: 7 + - description: 'Blanking from another timing unit: TIMFLTR4 source' + name: BlankTIMFLTR4 + value: 8 + - description: 'Blanking from another timing unit: TIMFLTR5 source' + name: BlankTIMFLTR5 + value: 9 + - description: 'Blanking from another timing unit: TIMFLTR6 source' + name: BlankTIMFLTR6 + value: 10 + - description: 'Blanking from another timing unit: TIMFLTR7 source' + name: BlankTIMFLTR7 + value: 11 + - description: 'Blanking from another timing unit: TIMFLTR8 source' + name: BlankTIMFLTR8 + value: 12 + - description: Windowing from counter reset/roll-over to compare 2 + name: WindowResetToCompare2 + value: 13 + - description: Windowing from counter reset/roll-over to compare 3 + name: WindowResetToCompare3 + value: 14 + - description: 'Windowing from another timing unit: TIMWIN source' + name: WindowTIMWIN + value: 15 +enum/EE1LTCH: + bit_size: 1 + variants: + - description: Event is ignored if it happens during a blank, or passed through + during a window + name: Disabled + value: 0 + - description: Event is latched and delayed till the end of the blanking or windowing + period + name: Enabled + value: 1 +enum/EE6FLTR: + bit_size: 4 + variants: + - description: No filtering + name: Disabled + value: 0 + - description: Blanking from counter reset/roll-over to Compare 1 + name: BlankResetToCompare1 + value: 1 + - description: Blanking from counter reset/roll-over to Compare 2 + name: BlankResetToCompare2 + value: 2 + - description: Blanking from counter reset/roll-over to Compare 3 + name: BlankResetToCompare3 + value: 3 + - description: Blanking from counter reset/roll-over to Compare 4 + name: BlankResetToCompare4 + value: 4 + - description: 'Blanking from another timing unit: TIMFLTR1 source' + name: BlankTIMFLTR1 + value: 5 + - description: 'Blanking from another timing unit: TIMFLTR2 source' + name: BlankTIMFLTR2 + value: 6 + - description: 'Blanking from another timing unit: TIMFLTR3 source' + name: BlankTIMFLTR3 + value: 7 + - description: 'Blanking from another timing unit: TIMFLTR4 source' + name: BlankTIMFLTR4 + value: 8 + - description: 'Blanking from another timing unit: TIMFLTR5 source' + name: BlankTIMFLTR5 + value: 9 + - description: 'Blanking from another timing unit: TIMFLTR6 source' + name: BlankTIMFLTR6 + value: 10 + - description: 'Blanking from another timing unit: TIMFLTR7 source' + name: BlankTIMFLTR7 + value: 11 + - description: 'Blanking from another timing unit: TIMFLTR8 source' + name: BlankTIMFLTR8 + value: 12 + - description: Windowing from counter reset/roll-over to compare 2 + name: WindowResetToCompare2 + value: 13 + - description: Windowing from counter reset/roll-over to compare 3 + name: WindowResetToCompare3 + value: 14 + - description: 'Windowing from another timing unit: TIMWIN source' + name: WindowTIMWIN + value: 15 +enum/EE6LTCH: + bit_size: 1 + variants: + - description: Event is ignored if it happens during a blank, or passed through + during a window + name: Disabled + value: 0 + - description: Event is latched and delayed till the end of the blanking or windowing + period + name: Enabled + value: 1 +enum/FAULT1: + bit_size: 2 + variants: + - description: 'No action: the output is not affected by the fault input and stays + in run mode' + name: Disabled + value: 0 + - description: Output goes to active state after a fault event + name: SetActive + value: 1 + - description: Output goes to inactive state after a fault event + name: SetInactive + value: 2 + - description: Output goes to high-z state after a fault event + name: SetHighZ + value: 3 +enum/FLT1EN: + bit_size: 1 + variants: + - description: Fault input ignored + name: Ignored + value: 0 + - description: Fault input is active and can disable HRTIM outputs + name: Active + value: 1 +enum/FLTLCK: + bit_size: 1 + variants: + - description: FLT1EN..FLT5EN bits are read/write + name: Unlocked + value: 0 + - description: FLT1EN..FLT5EN bits are read only + name: Locked + value: 1 +enum/HALF: + bit_size: 1 + variants: + - description: Half mode disabled + name: Disabled + value: 0 + - description: Half mode enabled + name: Enabled + value: 1 +enum/IDLEM1: + bit_size: 1 + variants: + - description: 'No action: the output is not affected by the burst mode operation' + name: NoEffect + value: 0 + - description: The output is in idle state when requested by the burst mode controller + name: SetIdle + value: 1 +enum/IDLES1: + bit_size: 1 + variants: + - description: Output idle state is inactive + name: Inactive + value: 0 + - description: Output idle state is active + name: Active + value: 1 +enum/IPPSTAT: + bit_size: 1 + variants: + - description: Protection occurred when the output 1 was active and output 2 forced + inactive + name: Output1Active + value: 0 + - description: Protection occurred when the output 2 was active and output 1 forced + inactive + name: Output2Active + value: 1 +enum/MCEN: + bit_size: 1 + variants: + - description: Master timer counter disabled + name: Disabled + value: 0 + - description: Master timer counter enabled + name: Enabled + value: 1 +enum/MCMP1: + bit_size: 1 + variants: + - description: No master compare interrupt occurred + name: NoEvent + value: 0 + - description: Master compare interrupt occurred + name: Event + value: 1 +enum/MCMP1C: + bit_size: 1 + variants: + - description: Clears flag in MISR register + name: Clear + value: 1 +enum/MCMP1DE: + bit_size: 1 + variants: + - description: DMA request disabled + name: Disabled + value: 0 + - description: DMA request enabled + name: Enabled + value: 1 +enum/MCMP1IE: + bit_size: 1 + variants: + - description: Interrupt disabled + name: Disabled + value: 0 + - description: Interrupt enabled + name: Enabled + value: 1 +enum/MREP: + bit_size: 1 + variants: + - description: No master repetition interrupt occurred + name: NoEvent + value: 0 + - description: Master repetition interrupt occurred + name: Event + value: 1 +enum/MREPU: + bit_size: 1 + variants: + - description: Update on repetition disabled + name: Disabled + value: 0 + - description: Update on repetition enabled + name: Enabled + value: 1 +enum/MSTU: + bit_size: 1 + variants: + - description: Update by master timer disabled + name: Disabled + value: 0 + - description: Update by master timer enabled + name: Enabled + value: 1 +enum/MUPD: + bit_size: 1 + variants: + - description: No master update interrupt occurred + name: NoEvent + value: 0 + - description: Master update interrupt occurred + name: Event + value: 1 +enum/O1CPY: + bit_size: 1 + variants: + - description: Output is inactive + name: Inactive + value: 0 + - description: Output is active + name: Active + value: 1 +enum/O1STAT: + bit_size: 1 + variants: + - description: Output was inactive + name: Inactive + value: 0 + - description: Output was active + name: Active + value: 1 +enum/OUTAR_DLYPRT: + bit_size: 3 + variants: + - description: Output 1 delayed idle on external event 6 + name: Output1_EE6 + value: 0 + - description: Output 2 delayed idle on external event 6 + name: Output2_EE6 + value: 1 + - description: Output 1 and 2 delayed idle on external event 6 + name: Output1_2_EE6 + value: 2 + - description: Balanced idle on external event 6 + name: Balanced_EE6 + value: 3 + - description: Output 1 delayed idle on external event 7 + name: Output1_EE7 + value: 4 + - description: Output 2 delayed idle on external event 7 + name: Output2_EE7 + value: 5 + - description: Output 1 and 2 delayed idle on external event 7 + name: Output1_2_EE7 + value: 6 + - description: Balanced idle on external event 7 + name: Balanced_EE7 + value: 7 +enum/OUTBR_DLYPRT: + bit_size: 3 + variants: + - description: Output 1 delayed idle on external event 6 + name: Output1_EE6 + value: 0 + - description: Output 2 delayed idle on external event 6 + name: Output2_EE6 + value: 1 + - description: Output 1 and 2 delayed idle on external event 6 + name: Output1_2_EE6 + value: 2 + - description: Balanced idle on external event 6 + name: Balanced_EE6 + value: 3 + - description: Output 1 delayed idle on external event 7 + name: Output1_EE7 + value: 4 + - description: Output 2 delayed idle on external event 7 + name: Output2_EE7 + value: 5 + - description: Output 1 and 2 delayed idle on external event 7 + name: Output1_2_EE7 + value: 6 + - description: Balanced idle on external event 7 + name: Balanced_EE7 + value: 7 +enum/OUTCR_DLYPRT: + bit_size: 3 + variants: + - description: Output 1 delayed idle on external event 6 + name: Output1_EE6 + value: 0 + - description: Output 2 delayed idle on external event 6 + name: Output2_EE6 + value: 1 + - description: Output 1 and 2 delayed idle on external event 6 + name: Output1_2_EE6 + value: 2 + - description: Balanced idle on external event 6 + name: Balanced_EE6 + value: 3 + - description: Output 1 delayed idle on external event 7 + name: Output1_EE7 + value: 4 + - description: Output 2 delayed idle on external event 7 + name: Output2_EE7 + value: 5 + - description: Output 1 and 2 delayed idle on external event 7 + name: Output1_2_EE7 + value: 6 + - description: Balanced idle on external event 7 + name: Balanced_EE7 + value: 7 +enum/OUTDR_DLYPRT: + bit_size: 3 + variants: + - description: Output 1 delayed idle on external event 8 + name: Output1_EE8 + value: 0 + - description: Output 2 delayed idle on external event 8 + name: Output2_EE8 + value: 1 + - description: Output 1 and 2 delayed idle on external event 8 + name: Output1_2_EE8 + value: 2 + - description: Balanced idle on external event 8 + name: Balanced_EE8 + value: 3 + - description: Output 1 delayed idle on external event 9 + name: Output1_EE9 + value: 4 + - description: Output 2 delayed idle on external event 9 + name: Output2_EE9 + value: 5 + - description: Output 1 and 2 delayed idle on external event 9 + name: Output1_2_EE9 + value: 6 + - description: Balanced idle on external event 9 + name: Balanced_EE9 + value: 7 +enum/OUTER_DLYPRT: + bit_size: 3 + variants: + - description: Output 1 delayed idle on external event 8 + name: Output1_EE8 + value: 0 + - description: Output 2 delayed idle on external event 8 + name: Output2_EE8 + value: 1 + - description: Output 1 and 2 delayed idle on external event 8 + name: Output1_2_EE8 + value: 2 + - description: Balanced idle on external event 8 + name: Balanced_EE8 + value: 3 + - description: Output 1 delayed idle on external event 9 + name: Output1_EE9 + value: 4 + - description: Output 2 delayed idle on external event 9 + name: Output2_EE9 + value: 5 + - description: Output 1 and 2 delayed idle on external event 9 + name: Output1_2_EE9 + value: 6 + - description: Balanced idle on external event 9 + name: Balanced_EE9 + value: 7 +enum/POL1: + bit_size: 1 + variants: + - description: Positive polarity (output active high) + name: ActiveHigh + value: 0 + - description: Negative polarity (output active low) + name: ActiveLow + value: 1 +enum/PREEN: + bit_size: 1 + variants: + - description: 'Preload disabled: the write access is directly done into the active + register' + name: Disabled + value: 0 + - description: 'Preload enabled: the write access is done into the preload register' + name: Enabled + value: 1 +enum/PSHPLL: + bit_size: 1 + variants: + - description: Push-pull mode disabled + name: Disabled + value: 0 + - description: Push-pull mode enabled + name: Enabled + value: 1 +enum/REP: + bit_size: 1 + variants: + - description: No timer repetition interrupt occurred + name: NoEvent + value: 0 + - description: Timer repetition interrupt occurred + name: Event + value: 1 +enum/REPDE: + bit_size: 1 + variants: + - description: Repetition DMA request disabled + name: Disabled + value: 0 + - description: Repetition DMA request enabled + name: Enabled + value: 1 +enum/REPIE: + bit_size: 1 + variants: + - description: Repetition interrupt disabled + name: Disabled + value: 0 + - description: Repetition interrupt enabled + name: Enabled + value: 1 +enum/RETRIG: + bit_size: 1 + variants: + - description: 'The timer is not re-triggerable: a counter reset can be done only + if the counter is stopped' + name: Disabled + value: 0 + - description: 'The timer is retriggerable: a counter reset is done whatever the + counter state' + name: Enabled + value: 1 +enum/RST: + bit_size: 1 + variants: + - description: No TIMx counter reset/roll-over interrupt occurred + name: NoEvent + value: 0 + - description: TIMx counter reset/roll-over interrupt occurred + name: Event + value: 1 +enum/RSTA1R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTA1R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTA1R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTA1R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its inactive + state + name: SetInactive + value: 1 +enum/RSTA1R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTA1R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTA1R_SRT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its inactive state + name: SetInactive + value: 1 +enum/RSTA1R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTA1R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTA2R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTA2R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTA2R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTA2R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its inactive + state + name: SetInactive + value: 1 +enum/RSTA2R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTA2R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTA2R_SRT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its inactive state + name: SetInactive + value: 1 +enum/RSTA2R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTA2R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTAR_EXTEVNT1: + bit_size: 1 + variants: + - description: External event Z has no effect + name: NoEffect + value: 0 + - description: Timer X counter is reset upon external event Z + name: ResetCounter + value: 1 +enum/RSTAR_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare Z event has no effect + name: NoEffect + value: 0 + - description: Timer X counter is reset upon master timer compare Z event + name: ResetCounter + value: 1 +enum/RSTAR_MSTPER: + bit_size: 1 + variants: + - description: Master timer period event has no effect + name: NoEffect + value: 0 + - description: Timer X counter is reset upon master timer period event + name: ResetCounter + value: 1 +enum/RSTB1R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTB1R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTB1R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTB1R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its inactive + state + name: SetInactive + value: 1 +enum/RSTB1R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTB1R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTB1R_SRT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its inactive state + name: SetInactive + value: 1 +enum/RSTB1R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTB1R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTB2R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTB2R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTB2R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTB2R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its inactive + state + name: SetInactive + value: 1 +enum/RSTB2R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTB2R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTB2R_SRT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its inactive state + name: SetInactive + value: 1 +enum/RSTB2R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTB2R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTBR_EXTEVNT1: + bit_size: 1 + variants: + - description: External event Z has no effect + name: NoEffect + value: 0 + - description: Timer X counter is reset upon external event Z + name: ResetCounter + value: 1 +enum/RSTBR_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare Z event has no effect + name: NoEffect + value: 0 + - description: Timer X counter is reset upon master timer compare Z event + name: ResetCounter + value: 1 +enum/RSTBR_MSTPER: + bit_size: 1 + variants: + - description: Master timer period event has no effect + name: NoEffect + value: 0 + - description: Timer X counter is reset upon master timer period event + name: ResetCounter + value: 1 +enum/RSTC1R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTC1R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTC1R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTC1R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its inactive + state + name: SetInactive + value: 1 +enum/RSTC1R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTC1R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTC1R_SRT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its inactive state + name: SetInactive + value: 1 +enum/RSTC1R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTC1R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTC2R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTC2R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTC2R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTC2R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its inactive + state + name: SetInactive + value: 1 +enum/RSTC2R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTC2R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTC2R_SRT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its inactive state + name: SetInactive + value: 1 +enum/RSTC2R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTC2R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTCR_EXTEVNT1: + bit_size: 1 + variants: + - description: External event Z has no effect + name: NoEffect + value: 0 + - description: Timer X counter is reset upon external event Z + name: ResetCounter + value: 1 +enum/RSTCR_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare Z event has no effect + name: NoEffect + value: 0 + - description: Timer X counter is reset upon master timer compare Z event + name: ResetCounter + value: 1 +enum/RSTCR_MSTPER: + bit_size: 1 + variants: + - description: Master timer period event has no effect + name: NoEffect + value: 0 + - description: Timer X counter is reset upon master timer period event + name: ResetCounter + value: 1 +enum/RSTD1R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTD1R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTD1R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTD1R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its inactive + state + name: SetInactive + value: 1 +enum/RSTD1R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTD1R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTD1R_SRT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its inactive state + name: SetInactive + value: 1 +enum/RSTD1R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTD1R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTD2R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTD2R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTD2R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTD2R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its inactive + state + name: SetInactive + value: 1 +enum/RSTD2R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTD2R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTD2R_SRT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its inactive state + name: SetInactive + value: 1 +enum/RSTD2R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTD2R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTDE: + bit_size: 1 + variants: + - description: Timer x counter reset/roll-over DMA request disabled + name: Disabled + value: 0 + - description: Timer x counter reset/roll-over DMA request enabled + name: Enabled + value: 1 +enum/RSTDR_EXTEVNT1: + bit_size: 1 + variants: + - description: External event Z has no effect + name: NoEffect + value: 0 + - description: Timer X counter is reset upon external event Z + name: ResetCounter + value: 1 +enum/RSTDR_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare Z event has no effect + name: NoEffect + value: 0 + - description: Timer X counter is reset upon master timer compare Z event + name: ResetCounter + value: 1 +enum/RSTDR_MSTPER: + bit_size: 1 + variants: + - description: Master timer period event has no effect + name: NoEffect + value: 0 + - description: Timer X counter is reset upon master timer period event + name: ResetCounter + value: 1 +enum/RSTE1R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTE1R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTE1R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTE1R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its inactive + state + name: SetInactive + value: 1 +enum/RSTE1R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTE1R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTE1R_SRT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its inactive state + name: SetInactive + value: 1 +enum/RSTE1R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTE1R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTE2R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTE2R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTE2R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTE2R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its inactive + state + name: SetInactive + value: 1 +enum/RSTE2R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTE2R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTE2R_SRT: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its inactive state + name: SetInactive + value: 1 +enum/RSTE2R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTE2R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its inactive state + name: SetInactive + value: 1 +enum/RSTER_EXTEVNT1: + bit_size: 1 + variants: + - description: External event Z has no effect + name: NoEffect + value: 0 + - description: Timer X counter is reset upon external event Z + name: ResetCounter + value: 1 +enum/RSTER_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare Z event has no effect + name: NoEffect + value: 0 + - description: Timer X counter is reset upon master timer compare Z event + name: ResetCounter + value: 1 +enum/RSTER_MSTPER: + bit_size: 1 + variants: + - description: Master timer period event has no effect + name: NoEffect + value: 0 + - description: Timer X counter is reset upon master timer period event + name: ResetCounter + value: 1 +enum/RSTIE: + bit_size: 1 + variants: + - description: Timer x counter/reset roll-over interrupt disabled + name: Disabled + value: 0 + - description: Timer x counter/reset roll-over interrupt enabled + name: Enabled + value: 1 +enum/RSTx1: + bit_size: 1 + variants: + - description: No Tx output reset interrupt occurred + name: NoEvent + value: 0 + - description: Tx output reset interrupt occurred + name: Event + value: 1 +enum/RSTx1DE: + bit_size: 1 + variants: + - description: Tx output reset DMA request disabled + name: Disabled + value: 0 + - description: Tx output reset DMA request enabled + name: Enabled + value: 1 +enum/RSTx1IE: + bit_size: 1 + variants: + - description: Tx output reset interrupt disabled + name: Disabled + value: 0 + - description: Tx output reset interrupt enabled + name: Enabled + value: 1 +enum/SDTFx: + bit_size: 1 + variants: + - description: Positive deadtime on falling edge + name: Positive + value: 0 + - description: Negative deadtime on falling edge + name: Negative + value: 1 +enum/SDTRx: + bit_size: 1 + variants: + - description: Positive deadtime on rising edge + name: Positive + value: 0 + - description: Negative deadtime on rising edge + name: Negative + value: 1 +enum/SETA1R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETA1R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its active state + name: SetActive + value: 1 +enum/SETA1R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETA1R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its active + state + name: SetActive + value: 1 +enum/SETA1R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its active state + name: SetActive + value: 1 +enum/SETA1R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its active state + name: SetActive + value: 1 +enum/SETA1R_SST: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its active state + name: SetActive + value: 1 +enum/SETA1R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its active state + name: SetActive + value: 1 +enum/SETA1R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its active state + name: SetActive + value: 1 +enum/SETA2R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETA2R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its active state + name: SetActive + value: 1 +enum/SETA2R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETA2R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its active + state + name: SetActive + value: 1 +enum/SETA2R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its active state + name: SetActive + value: 1 +enum/SETA2R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its active state + name: SetActive + value: 1 +enum/SETA2R_SST: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its active state + name: SetActive + value: 1 +enum/SETA2R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its active state + name: SetActive + value: 1 +enum/SETA2R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its active state + name: SetActive + value: 1 +enum/SETB1R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETB1R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its active state + name: SetActive + value: 1 +enum/SETB1R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETB1R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its active + state + name: SetActive + value: 1 +enum/SETB1R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its active state + name: SetActive + value: 1 +enum/SETB1R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its active state + name: SetActive + value: 1 +enum/SETB1R_SST: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its active state + name: SetActive + value: 1 +enum/SETB1R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its active state + name: SetActive + value: 1 +enum/SETB1R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its active state + name: SetActive + value: 1 +enum/SETB2R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETB2R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its active state + name: SetActive + value: 1 +enum/SETB2R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETB2R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its active + state + name: SetActive + value: 1 +enum/SETB2R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its active state + name: SetActive + value: 1 +enum/SETB2R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its active state + name: SetActive + value: 1 +enum/SETB2R_SST: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its active state + name: SetActive + value: 1 +enum/SETB2R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its active state + name: SetActive + value: 1 +enum/SETB2R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its active state + name: SetActive + value: 1 +enum/SETC1R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETC1R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its active state + name: SetActive + value: 1 +enum/SETC1R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETC1R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its active + state + name: SetActive + value: 1 +enum/SETC1R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its active state + name: SetActive + value: 1 +enum/SETC1R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its active state + name: SetActive + value: 1 +enum/SETC1R_SST: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its active state + name: SetActive + value: 1 +enum/SETC1R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its active state + name: SetActive + value: 1 +enum/SETC1R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its active state + name: SetActive + value: 1 +enum/SETC2R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETC2R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its active state + name: SetActive + value: 1 +enum/SETC2R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETC2R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its active + state + name: SetActive + value: 1 +enum/SETC2R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its active state + name: SetActive + value: 1 +enum/SETC2R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its active state + name: SetActive + value: 1 +enum/SETC2R_SST: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its active state + name: SetActive + value: 1 +enum/SETC2R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its active state + name: SetActive + value: 1 +enum/SETC2R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its active state + name: SetActive + value: 1 +enum/SETD1R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETD1R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its active state + name: SetActive + value: 1 +enum/SETD1R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETD1R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its active + state + name: SetActive + value: 1 +enum/SETD1R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its active state + name: SetActive + value: 1 +enum/SETD1R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its active state + name: SetActive + value: 1 +enum/SETD1R_SST: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its active state + name: SetActive + value: 1 +enum/SETD1R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its active state + name: SetActive + value: 1 +enum/SETD1R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its active state + name: SetActive + value: 1 +enum/SETD2R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETD2R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its active state + name: SetActive + value: 1 +enum/SETD2R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETD2R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its active + state + name: SetActive + value: 1 +enum/SETD2R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its active state + name: SetActive + value: 1 +enum/SETD2R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its active state + name: SetActive + value: 1 +enum/SETD2R_SST: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its active state + name: SetActive + value: 1 +enum/SETD2R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its active state + name: SetActive + value: 1 +enum/SETD2R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its active state + name: SetActive + value: 1 +enum/SETE1R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETE1R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its active state + name: SetActive + value: 1 +enum/SETE1R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETE1R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its active + state + name: SetActive + value: 1 +enum/SETE1R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its active state + name: SetActive + value: 1 +enum/SETE1R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its active state + name: SetActive + value: 1 +enum/SETE1R_SST: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its active state + name: SetActive + value: 1 +enum/SETE1R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its active state + name: SetActive + value: 1 +enum/SETE1R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its active state + name: SetActive + value: 1 +enum/SETE2R_CMP1: + bit_size: 1 + variants: + - description: Timer compare event has no effect + name: NoEffect + value: 0 + - description: Timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETE2R_EXTEVNT1: + bit_size: 1 + variants: + - description: External event has no effect + name: NoEffect + value: 0 + - description: External event forces the output to its active state + name: SetActive + value: 1 +enum/SETE2R_MSTCMP1: + bit_size: 1 + variants: + - description: Master timer compare event has no effect + name: NoEffect + value: 0 + - description: Master timer compare event forces the output to its active state + name: SetActive + value: 1 +enum/SETE2R_MSTPER: + bit_size: 1 + variants: + - description: Master timer counter roll-over/reset has no effect + name: NoEffect + value: 0 + - description: Master timer counter roll-over/reset forces the output to its active + state + name: SetActive + value: 1 +enum/SETE2R_PER: + bit_size: 1 + variants: + - description: Timer period event has no effect + name: NoEffect + value: 0 + - description: Timer period event forces the output to its active state + name: SetActive + value: 1 +enum/SETE2R_RESYNC: + bit_size: 1 + variants: + - description: Timer reset event coming solely from software or SYNC input event + has no effect + name: NoEffect + value: 0 + - description: Timer reset event coming solely from software or SYNC input event + forces the output to its active state + name: SetActive + value: 1 +enum/SETE2R_SST: + bit_size: 1 + variants: + - description: No effect + name: NoEffect + value: 0 + - description: Force output to its active state + name: SetActive + value: 1 +enum/SETE2R_TIMEVNT1: + bit_size: 1 + variants: + - description: Timer event has no effect + name: NoEffect + value: 0 + - description: Timer event forces the output to its active state + name: SetActive + value: 1 +enum/SETE2R_UPDATE: + bit_size: 1 + variants: + - description: Register update event has no effect + name: NoEffect + value: 0 + - description: Register update event forces the output to its active state + name: SetActive + value: 1 +enum/SETx1: + bit_size: 1 + variants: + - description: No Tx output set interrupt occurred + name: NoEvent + value: 0 + - description: Tx output set interrupt occurred + name: Event + value: 1 +enum/SETx1DE: + bit_size: 1 + variants: + - description: Tx output set DMA request disabled + name: Disabled + value: 0 + - description: Tx output set DMA request enabled + name: Enabled + value: 1 +enum/SETx1IE: + bit_size: 1 + variants: + - description: Tx output set interrupt disabled + name: Disabled + value: 0 + - description: Tx output set interrupt enabled + name: Enabled + value: 1 +enum/SYNC: + bit_size: 1 + variants: + - description: No sync input interrupt occurred + name: NoEvent + value: 0 + - description: Sync input interrupt occurred + name: Event + value: 1 +enum/SYNCIN: + bit_size: 2 + variants: + - description: Disabled. HRTIM is not synchronized and runs in standalone mode + name: Disabled + value: 0 + - description: 'Internal event: the HRTIM is synchronized with the on-chip timer' + name: Internal + value: 2 + - description: 'External event: a positive pulse on HRTIM_SCIN input triggers the + HRTIM' + name: External + value: 3 +enum/SYNCOUT: + bit_size: 2 + variants: + - description: Disabled + name: Disabled + value: 0 + - description: Positive pulse on SCOUT output (16x f_HRTIM clock cycles) + name: PositivePulse + value: 2 + - description: Negative pulse on SCOUT output (16x f_HRTIM clock cycles) + name: NegativePulse + value: 3 +enum/SYNCRSTM: + bit_size: 1 + variants: + - description: No effect on the master timer + name: Disabled + value: 0 + - description: A synchroniation input event resets the master timer + name: Enabled + value: 1 +enum/SYNCRSTx: + bit_size: 1 + variants: + - description: Synchronization event has no effect on Timer x + name: Disabled + value: 0 + - description: Synchronization event resets Timer x + name: Reset + value: 1 +enum/SYNCSRC: + bit_size: 2 + variants: + - description: Master timer Start + name: MasterStart + value: 0 + - description: Master timer Compare 1 event + name: MasterCompare1 + value: 1 + - description: Timer A start/reset + name: TimerAStart + value: 2 + - description: Timer A Compare 1 event + name: TimerACompare1 + value: 3 +enum/SYNCSTRTM: + bit_size: 1 + variants: + - description: No effect on the master timer + name: Disabled + value: 0 + - description: A synchroniation input event starts the master timer + name: Enabled + value: 1 +enum/SYNCSTRTx: + bit_size: 1 + variants: + - description: Synchronization event has no effect on Timer x + name: Disabled + value: 0 + - description: Synchronization event starts Timer x + name: Start + value: 1 +enum/TACEN: + bit_size: 1 + variants: + - description: Timer counter disabled + name: Disabled + value: 0 + - description: Timer counter enabled + name: Enabled + value: 1 +enum/TBU: + bit_size: 1 + variants: + - description: Update by timer x disabled + name: Disabled + value: 0 + - description: Update by timer x enabled + name: Enabled + value: 1 +enum/TIMACMP1: + bit_size: 1 + variants: + - description: Timer Y compare Z event has no effect + name: NoEffect + value: 0 + - description: Timer X counter is reset upon timer Y compare Z event + name: ResetCounter + value: 1 +enum/TIMAISR_CMP1: + bit_size: 1 + variants: + - description: No compare interrupt occurred + name: NoEvent + value: 0 + - description: Compare interrupt occurred + name: Event + value: 1 +enum/TIMAISR_DLYPRT: + bit_size: 1 + variants: + - description: Not in delayed idle or balanced idle mode + name: Inactive + value: 0 + - description: Delayed idle or balanced idle mode entry + name: Active + value: 1 +enum/TIMBCMP1: + bit_size: 1 + variants: + - description: Timer Y compare Z event has no effect + name: NoEffect + value: 0 + - description: Timer X counter is reset upon timer Y compare Z event + name: ResetCounter + value: 1 +enum/TIMBISR_CMP1: + bit_size: 1 + variants: + - description: No compare interrupt occurred + name: NoEvent + value: 0 + - description: Compare interrupt occurred + name: Event + value: 1 +enum/TIMBISR_DLYPRT: + bit_size: 1 + variants: + - description: Not in delayed idle or balanced idle mode + name: Inactive + value: 0 + - description: Delayed idle or balanced idle mode entry + name: Active + value: 1 +enum/TIMCISR_CMP1: + bit_size: 1 + variants: + - description: No compare interrupt occurred + name: NoEvent + value: 0 + - description: Compare interrupt occurred + name: Event + value: 1 +enum/TIMCISR_DLYPRT: + bit_size: 1 + variants: + - description: Not in delayed idle or balanced idle mode + name: Inactive + value: 0 + - description: Delayed idle or balanced idle mode entry + name: Active + value: 1 +enum/TIMDISR_CMP1: + bit_size: 1 + variants: + - description: No compare interrupt occurred + name: NoEvent + value: 0 + - description: Compare interrupt occurred + name: Event + value: 1 +enum/TIMDISR_DLYPRT: + bit_size: 1 + variants: + - description: Not in delayed idle or balanced idle mode + name: Inactive + value: 0 + - description: Delayed idle or balanced idle mode entry + name: Active + value: 1 +enum/TIMEISR_CMP1: + bit_size: 1 + variants: + - description: No compare interrupt occurred + name: NoEvent + value: 0 + - description: Compare interrupt occurred + name: Event + value: 1 +enum/TIMEISR_DLYPRT: + bit_size: 1 + variants: + - description: Not in delayed idle or balanced idle mode + name: Inactive + value: 0 + - description: Delayed idle or balanced idle mode entry + name: Active + value: 1 +enum/TxREPU: + bit_size: 1 + variants: + - description: Update by timer x repetition disabled + name: Disabled + value: 0 + - description: Update by timer x repetition enabled + name: Enabled + value: 1 +enum/TxRSTU: + bit_size: 1 + variants: + - description: Update by timer x reset/roll-over disabled + name: Disabled + value: 0 + - description: Update by timer x reset/roll-over enabled + name: Enabled + value: 1 +enum/UPD: + bit_size: 1 + variants: + - description: No timer update interrupt occurred + name: NoEvent + value: 0 + - description: Timer update interrupt occurred + name: Event + value: 1 +enum/UPDDE: + bit_size: 1 + variants: + - description: Update DMA request disabled + name: Disabled + value: 0 + - description: Update DMA request enabled + name: Enabled + value: 1 +enum/UPDGAT: + bit_size: 4 + variants: + - description: Update occurs independently from the DMA burst transfer + name: Independent + value: 0 + - description: Update occurs when the DMA burst transfer is completed + name: DMABurst + value: 1 + - description: Update occurs on the update event following DMA burst transfer completion + name: DMABurst_Update + value: 2 + - description: Update occurs on a rising edge of HRTIM update enable input 1 + name: Input1 + value: 3 + - description: Update occurs on a rising edge of HRTIM update enable input 2 + name: Input2 + value: 4 + - description: Update occurs on a rising edge of HRTIM update enable input 3 + name: Input3 + value: 5 + - description: Update occurs on the update event following a rising edge of HRTIM + update enable input 1 + name: Input1_Update + value: 6 + - description: Update occurs on the update event following a rising edge of HRTIM + update enable input 2 + name: Input2_Update + value: 7 + - description: Update occurs on the update event following a rising edge of HRTIM + update enable input 3 + name: Input3_Update + value: 8 +enum/UPDIE: + bit_size: 1 + variants: + - description: Update interrupt disabled + name: Disabled + value: 0 + - description: Update interrupt enabled + name: Enabled + value: 1 +enum/UPDT: + bit_size: 1 + variants: + - description: Update event has no effect + name: NoEffect + value: 0 + - description: Timer X counter is reset upon update event + name: ResetCounter + value: 1 +fieldset/CHPAR: + description: Timerx Chopper Register + fields: + - bit_offset: 0 + bit_size: 4 + description: "Timerx carrier frequency\r value" + name: CARFRQ + - bit_offset: 4 + bit_size: 3 + description: "Timerx chopper duty cycle\r value" + name: CARDTY + - bit_offset: 7 + bit_size: 4 + description: STRTPW + name: STRTPW +fieldset/CHPBR: + description: Timerx Chopper Register + fields: + - bit_offset: 0 + bit_size: 4 + description: "Timerx carrier frequency\r value" + name: CARFRQ + - bit_offset: 4 + bit_size: 3 + description: "Timerx chopper duty cycle\r value" + name: CARDTY + - bit_offset: 7 + bit_size: 4 + description: STRTPW + name: STRTPW +fieldset/CHPCR: + description: Timerx Chopper Register + fields: + - bit_offset: 0 + bit_size: 4 + description: "Timerx carrier frequency\r value" + name: CARFRQ + - bit_offset: 4 + bit_size: 3 + description: "Timerx chopper duty cycle\r value" + name: CARDTY + - bit_offset: 7 + bit_size: 4 + description: STRTPW + name: STRTPW +fieldset/CHPDR: + description: Timerx Chopper Register + fields: + - bit_offset: 0 + bit_size: 4 + description: "Timerx carrier frequency\r value" + name: CARFRQ + - bit_offset: 4 + bit_size: 3 + description: "Timerx chopper duty cycle\r value" + name: CARDTY + - bit_offset: 7 + bit_size: 4 + description: STRTPW + name: STRTPW +fieldset/CHPER: + description: Timerx Chopper Register + fields: + - bit_offset: 0 + bit_size: 4 + description: "Timerx carrier frequency\r value" + name: CARFRQ + - bit_offset: 4 + bit_size: 3 + description: "Timerx chopper duty cycle\r value" + name: CARDTY + - bit_offset: 7 + bit_size: 4 + description: STRTPW + name: STRTPW +fieldset/CMP1AR: + description: Timerx Compare 1 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 1 value + name: CMP1x +fieldset/CMP1BR: + description: Timerx Compare 1 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 1 value + name: CMP1x +fieldset/CMP1CAR: + description: "Timerx Compare 1 Compound\r Register" + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 1 value + name: CMP1x + - bit_offset: 16 + bit_size: 8 + description: "Timerx Repetition value (aliased from\r HRTIM_REPx register)" + name: REPx +fieldset/CMP1CBR: + description: "Timerx Compare 1 Compound\r Register" + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 1 value + name: CMP1x + - bit_offset: 16 + bit_size: 8 + description: "Timerx Repetition value (aliased from\r HRTIM_REPx register)" + name: REPx +fieldset/CMP1CCR: + description: "Timerx Compare 1 Compound\r Register" + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 1 value + name: CMP1x + - bit_offset: 16 + bit_size: 8 + description: "Timerx Repetition value (aliased from\r HRTIM_REPx register)" + name: REPx +fieldset/CMP1CDR: + description: "Timerx Compare 1 Compound\r Register" + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 1 value + name: CMP1x + - bit_offset: 16 + bit_size: 8 + description: "Timerx Repetition value (aliased from\r HRTIM_REPx register)" + name: REPx +fieldset/CMP1CER: + description: "Timerx Compare 1 Compound\r Register" + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 1 value + name: CMP1x + - bit_offset: 16 + bit_size: 8 + description: "Timerx Repetition value (aliased from\r HRTIM_REPx register)" + name: REPx +fieldset/CMP1CR: + description: Timerx Compare 1 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 1 value + name: CMP1x +fieldset/CMP1DR: + description: Timerx Compare 1 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 1 value + name: CMP1x +fieldset/CMP1ER: + description: Timerx Compare 1 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 1 value + name: CMP1x +fieldset/CMP2AR: + description: Timerx Compare 2 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 2 value + name: CMP2x +fieldset/CMP2BR: + description: Timerx Compare 2 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 2 value + name: CMP2x +fieldset/CMP2CR: + description: Timerx Compare 2 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 2 value + name: CMP2x +fieldset/CMP2DR: + description: Timerx Compare 2 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 2 value + name: CMP2x +fieldset/CMP2ER: + description: Timerx Compare 2 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 2 value + name: CMP2x +fieldset/CMP3AR: + description: Timerx Compare 3 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 3 value + name: CMP3x +fieldset/CMP3BR: + description: Timerx Compare 3 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 3 value + name: CMP3x +fieldset/CMP3CR: + description: Timerx Compare 3 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 3 value + name: CMP3x +fieldset/CMP3DR: + description: Timerx Compare 3 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 3 value + name: CMP3x +fieldset/CMP3ER: + description: Timerx Compare 3 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 3 value + name: CMP3x +fieldset/CMP4AR: + description: Timerx Compare 4 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 4 value + name: CMP4x +fieldset/CMP4BR: + description: Timerx Compare 4 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 4 value + name: CMP4x +fieldset/CMP4CR: + description: Timerx Compare 4 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 4 value + name: CMP4x +fieldset/CMP4DR: + description: Timerx Compare 4 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 4 value + name: CMP4x +fieldset/CMP4ER: + description: Timerx Compare 4 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Compare 4 value + name: CMP4x +fieldset/CNTAR: + description: Timerx Counter Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Counter value + name: CNTx +fieldset/CNTBR: + description: Timerx Counter Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Counter value + name: CNTx +fieldset/CNTCR: + description: Timerx Counter Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Counter value + name: CNTx +fieldset/CNTDR: + description: Timerx Counter Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Counter value + name: CNTx +fieldset/CNTER: + description: Timerx Counter Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Counter value + name: CNTx +fieldset/CPT1ACR: + description: "Timerx Capture 2 Control\r Register" + fields: + - bit_offset: 0 + bit_size: 1 + description: Software Capture + enum: CPT1ACR_SWCPT + name: SWCPT + - bit_offset: 1 + bit_size: 1 + description: Update Capture + enum: CPT1ACR_UPDCPT + name: UPDCPT + - bit_offset: 2 + bit_size: 1 + description: External Event 1 Capture + enum: CPT1ACR_EXEV1CPT + name: EXEV1CPT + - bit_offset: 3 + bit_size: 1 + description: External Event 2 Capture + enum: CPT1ACR_EXEV1CPT + name: EXEV2CPT + - bit_offset: 4 + bit_size: 1 + description: External Event 3 Capture + enum: CPT1ACR_EXEV1CPT + name: EXEV3CPT + - bit_offset: 5 + bit_size: 1 + description: External Event 4 Capture + enum: CPT1ACR_EXEV1CPT + name: EXEV4CPT + - bit_offset: 6 + bit_size: 1 + description: External Event 5 Capture + enum: CPT1ACR_EXEV1CPT + name: EXEV5CPT + - bit_offset: 7 + bit_size: 1 + description: External Event 6 Capture + enum: CPT1ACR_EXEV1CPT + name: EXEV6CPT + - bit_offset: 8 + bit_size: 1 + description: External Event 7 Capture + enum: CPT1ACR_EXEV1CPT + name: EXEV7CPT + - bit_offset: 9 + bit_size: 1 + description: External Event 8 Capture + enum: CPT1ACR_EXEV1CPT + name: EXEV8CPT + - bit_offset: 10 + bit_size: 1 + description: External Event 9 Capture + enum: CPT1ACR_EXEV1CPT + name: EXEV9CPT + - bit_offset: 11 + bit_size: 1 + description: External Event 10 Capture + enum: CPT1ACR_EXEV1CPT + name: EXEV10CPT + - bit_offset: 16 + bit_size: 1 + description: Timer B output 1 Set + enum: CPT1ACR_TB1SET + name: TB1SET + - bit_offset: 17 + bit_size: 1 + description: Timer B output 1 Reset + enum: CPT1ACR_TB1RST + name: TB1RST + - bit_offset: 18 + bit_size: 1 + description: Timer B Compare 1 + enum: CPT1ACR_TBCMP1 + name: TBCMP1 + - bit_offset: 19 + bit_size: 1 + description: Timer B Compare 2 + enum: CPT1ACR_TBCMP1 + name: TBCMP2 + - bit_offset: 20 + bit_size: 1 + description: Timer C output 1 Set + enum: CPT1ACR_TB1SET + name: TC1SET + - bit_offset: 21 + bit_size: 1 + description: Timer C output 1 Reset + enum: CPT1ACR_TB1RST + name: TC1RST + - bit_offset: 22 + bit_size: 1 + description: Timer C Compare 1 + enum: CPT1ACR_TBCMP1 + name: TCCMP1 + - bit_offset: 23 + bit_size: 1 + description: Timer C Compare 2 + enum: CPT1ACR_TBCMP1 + name: TCCMP2 + - bit_offset: 24 + bit_size: 1 + description: Timer D output 1 Set + enum: CPT1ACR_TB1SET + name: TD1SET + - bit_offset: 25 + bit_size: 1 + description: Timer D output 1 Reset + enum: CPT1ACR_TB1RST + name: TD1RST + - bit_offset: 26 + bit_size: 1 + description: Timer D Compare 1 + enum: CPT1ACR_TBCMP1 + name: TDCMP1 + - bit_offset: 27 + bit_size: 1 + description: Timer D Compare 2 + enum: CPT1ACR_TBCMP1 + name: TDCMP2 + - bit_offset: 28 + bit_size: 1 + description: Timer E output 1 Set + enum: CPT1ACR_TB1SET + name: TE1SET + - bit_offset: 29 + bit_size: 1 + description: Timer E output 1 Reset + enum: CPT1ACR_TB1RST + name: TE1RST + - bit_offset: 30 + bit_size: 1 + description: Timer E Compare 1 + enum: CPT1ACR_TBCMP1 + name: TECMP1 + - bit_offset: 31 + bit_size: 1 + description: Timer E Compare 2 + enum: CPT1ACR_TBCMP1 + name: TECMP2 +fieldset/CPT1AR: + description: Timerx Capture 1 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Capture 1 value + name: CPT1x +fieldset/CPT1BCR: + description: "Timerx Capture 2 Control\r Register" + fields: + - bit_offset: 0 + bit_size: 1 + description: Software Capture + enum: CPT1BCR_SWCPT + name: SWCPT + - bit_offset: 1 + bit_size: 1 + description: Update Capture + enum: CPT1BCR_UPDCPT + name: UPDCPT + - bit_offset: 2 + bit_size: 1 + description: External Event 1 Capture + enum: CPT1BCR_EXEV1CPT + name: EXEV1CPT + - bit_offset: 3 + bit_size: 1 + description: External Event 2 Capture + enum: CPT1BCR_EXEV1CPT + name: EXEV2CPT + - bit_offset: 4 + bit_size: 1 + description: External Event 3 Capture + enum: CPT1BCR_EXEV1CPT + name: EXEV3CPT + - bit_offset: 5 + bit_size: 1 + description: External Event 4 Capture + enum: CPT1BCR_EXEV1CPT + name: EXEV4CPT + - bit_offset: 6 + bit_size: 1 + description: External Event 5 Capture + enum: CPT1BCR_EXEV1CPT + name: EXEV5CPT + - bit_offset: 7 + bit_size: 1 + description: External Event 6 Capture + enum: CPT1BCR_EXEV1CPT + name: EXEV6CPT + - bit_offset: 8 + bit_size: 1 + description: External Event 7 Capture + enum: CPT1BCR_EXEV1CPT + name: EXEV7CPT + - bit_offset: 9 + bit_size: 1 + description: External Event 8 Capture + enum: CPT1BCR_EXEV1CPT + name: EXEV8CPT + - bit_offset: 10 + bit_size: 1 + description: External Event 9 Capture + enum: CPT1BCR_EXEV1CPT + name: EXEV9CPT + - bit_offset: 11 + bit_size: 1 + description: External Event 10 Capture + enum: CPT1BCR_EXEV1CPT + name: EXEV10CPT + - bit_offset: 12 + bit_size: 1 + description: Timer A output 1 Set + enum: CPT1BCR_TA1SET + name: TA1SET + - bit_offset: 13 + bit_size: 1 + description: Timer A output 1 Reset + enum: CPT1BCR_TA1RST + name: TA1RST + - bit_offset: 14 + bit_size: 1 + description: Timer A Compare 1 + enum: CPT1BCR_TACMP1 + name: TACMP1 + - bit_offset: 15 + bit_size: 1 + description: Timer A Compare 2 + enum: CPT1BCR_TACMP1 + name: TACMP2 + - bit_offset: 20 + bit_size: 1 + description: Timer C output 1 Set + enum: CPT1BCR_TA1SET + name: TC1SET + - bit_offset: 21 + bit_size: 1 + description: Timer C output 1 Reset + enum: CPT1BCR_TA1RST + name: TC1RST + - bit_offset: 22 + bit_size: 1 + description: Timer C Compare 1 + enum: CPT1BCR_TACMP1 + name: TCCMP1 + - bit_offset: 23 + bit_size: 1 + description: Timer C Compare 2 + enum: CPT1BCR_TACMP1 + name: TCCMP2 + - bit_offset: 24 + bit_size: 1 + description: Timer D output 1 Set + enum: CPT1BCR_TA1SET + name: TD1SET + - bit_offset: 25 + bit_size: 1 + description: Timer D output 1 Reset + enum: CPT1BCR_TA1RST + name: TD1RST + - bit_offset: 26 + bit_size: 1 + description: Timer D Compare 1 + enum: CPT1BCR_TACMP1 + name: TDCMP1 + - bit_offset: 27 + bit_size: 1 + description: Timer D Compare 2 + enum: CPT1BCR_TACMP1 + name: TDCMP2 + - bit_offset: 28 + bit_size: 1 + description: Timer E output 1 Set + enum: CPT1BCR_TA1SET + name: TE1SET + - bit_offset: 29 + bit_size: 1 + description: Timer E output 1 Reset + enum: CPT1BCR_TA1RST + name: TE1RST + - bit_offset: 30 + bit_size: 1 + description: Timer E Compare 1 + enum: CPT1BCR_TACMP1 + name: TECMP1 + - bit_offset: 31 + bit_size: 1 + description: Timer E Compare 2 + enum: CPT1BCR_TACMP1 + name: TECMP2 +fieldset/CPT1BR: + description: Timerx Capture 1 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Capture 1 value + name: CPT1x +fieldset/CPT1CCR: + description: "Timerx Capture 2 Control\r Register" + fields: + - bit_offset: 0 + bit_size: 1 + description: Software Capture + enum: CPT1CCR_SWCPT + name: SWCPT + - bit_offset: 1 + bit_size: 1 + description: Update Capture + enum: CPT1CCR_UPDCPT + name: UPDCPT + - bit_offset: 2 + bit_size: 1 + description: External Event 1 Capture + enum: CPT1CCR_EXEV1CPT + name: EXEV1CPT + - bit_offset: 3 + bit_size: 1 + description: External Event 2 Capture + enum: CPT1CCR_EXEV1CPT + name: EXEV2CPT + - bit_offset: 4 + bit_size: 1 + description: External Event 3 Capture + enum: CPT1CCR_EXEV1CPT + name: EXEV3CPT + - bit_offset: 5 + bit_size: 1 + description: External Event 4 Capture + enum: CPT1CCR_EXEV1CPT + name: EXEV4CPT + - bit_offset: 6 + bit_size: 1 + description: External Event 5 Capture + enum: CPT1CCR_EXEV1CPT + name: EXEV5CPT + - bit_offset: 7 + bit_size: 1 + description: External Event 6 Capture + enum: CPT1CCR_EXEV1CPT + name: EXEV6CPT + - bit_offset: 8 + bit_size: 1 + description: External Event 7 Capture + enum: CPT1CCR_EXEV1CPT + name: EXEV7CPT + - bit_offset: 9 + bit_size: 1 + description: External Event 8 Capture + enum: CPT1CCR_EXEV1CPT + name: EXEV8CPT + - bit_offset: 10 + bit_size: 1 + description: External Event 9 Capture + enum: CPT1CCR_EXEV1CPT + name: EXEV9CPT + - bit_offset: 11 + bit_size: 1 + description: External Event 10 Capture + enum: CPT1CCR_EXEV1CPT + name: EXEV10CPT + - bit_offset: 12 + bit_size: 1 + description: Timer A output 1 Set + enum: CPT1CCR_TA1SET + name: TA1SET + - bit_offset: 13 + bit_size: 1 + description: Timer A output 1 Reset + enum: CPT1CCR_TA1RST + name: TA1RST + - bit_offset: 14 + bit_size: 1 + description: Timer A Compare 1 + enum: CPT1CCR_TACMP1 + name: TACMP1 + - bit_offset: 15 + bit_size: 1 + description: Timer A Compare 2 + enum: CPT1CCR_TACMP1 + name: TACMP2 + - bit_offset: 16 + bit_size: 1 + description: Timer B output 1 Set + enum: CPT1CCR_TA1SET + name: TB1SET + - bit_offset: 17 + bit_size: 1 + description: Timer B output 1 Reset + enum: CPT1CCR_TA1RST + name: TB1RST + - bit_offset: 18 + bit_size: 1 + description: Timer B Compare 1 + enum: CPT1CCR_TACMP1 + name: TBCMP1 + - bit_offset: 19 + bit_size: 1 + description: Timer B Compare 2 + enum: CPT1CCR_TACMP1 + name: TBCMP2 + - bit_offset: 24 + bit_size: 1 + description: Timer D output 1 Set + enum: CPT1CCR_TA1SET + name: TD1SET + - bit_offset: 25 + bit_size: 1 + description: Timer D output 1 Reset + enum: CPT1CCR_TA1RST + name: TD1RST + - bit_offset: 26 + bit_size: 1 + description: Timer D Compare 1 + enum: CPT1CCR_TACMP1 + name: TDCMP1 + - bit_offset: 27 + bit_size: 1 + description: Timer D Compare 2 + enum: CPT1CCR_TACMP1 + name: TDCMP2 + - bit_offset: 28 + bit_size: 1 + description: Timer E output 1 Set + enum: CPT1CCR_TA1SET + name: TE1SET + - bit_offset: 29 + bit_size: 1 + description: Timer E output 1 Reset + enum: CPT1CCR_TA1RST + name: TE1RST + - bit_offset: 30 + bit_size: 1 + description: Timer E Compare 1 + enum: CPT1CCR_TACMP1 + name: TECMP1 + - bit_offset: 31 + bit_size: 1 + description: Timer E Compare 2 + enum: CPT1CCR_TACMP1 + name: TECMP2 +fieldset/CPT1CR: + description: Timerx Capture 1 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Capture 1 value + name: CPT1x +fieldset/CPT1DCR: + description: "Timerx Capture 2 Control\r Register" + fields: + - bit_offset: 0 + bit_size: 1 + description: Software Capture + enum: CPT1DCR_SWCPT + name: SWCPT + - bit_offset: 1 + bit_size: 1 + description: Update Capture + enum: CPT1DCR_UPDCPT + name: UPDCPT + - bit_offset: 2 + bit_size: 1 + description: External Event 1 Capture + enum: CPT1DCR_EXEV1CPT + name: EXEV1CPT + - bit_offset: 3 + bit_size: 1 + description: External Event 2 Capture + enum: CPT1DCR_EXEV1CPT + name: EXEV2CPT + - bit_offset: 4 + bit_size: 1 + description: External Event 3 Capture + enum: CPT1DCR_EXEV1CPT + name: EXEV3CPT + - bit_offset: 5 + bit_size: 1 + description: External Event 4 Capture + enum: CPT1DCR_EXEV1CPT + name: EXEV4CPT + - bit_offset: 6 + bit_size: 1 + description: External Event 5 Capture + enum: CPT1DCR_EXEV1CPT + name: EXEV5CPT + - bit_offset: 7 + bit_size: 1 + description: External Event 6 Capture + enum: CPT1DCR_EXEV1CPT + name: EXEV6CPT + - bit_offset: 8 + bit_size: 1 + description: External Event 7 Capture + enum: CPT1DCR_EXEV1CPT + name: EXEV7CPT + - bit_offset: 9 + bit_size: 1 + description: External Event 8 Capture + enum: CPT1DCR_EXEV1CPT + name: EXEV8CPT + - bit_offset: 10 + bit_size: 1 + description: External Event 9 Capture + enum: CPT1DCR_EXEV1CPT + name: EXEV9CPT + - bit_offset: 11 + bit_size: 1 + description: External Event 10 Capture + enum: CPT1DCR_EXEV1CPT + name: EXEV10CPT + - bit_offset: 12 + bit_size: 1 + description: Timer A output 1 Set + enum: CPT1DCR_TA1SET + name: TA1SET + - bit_offset: 13 + bit_size: 1 + description: Timer A output 1 Reset + enum: CPT1DCR_TA1RST + name: TA1RST + - bit_offset: 14 + bit_size: 1 + description: Timer A Compare 1 + enum: CPT1DCR_TACMP1 + name: TACMP1 + - bit_offset: 15 + bit_size: 1 + description: Timer A Compare 2 + enum: CPT1DCR_TACMP1 + name: TACMP2 + - bit_offset: 16 + bit_size: 1 + description: Timer B output 1 Set + enum: CPT1DCR_TA1SET + name: TB1SET + - bit_offset: 17 + bit_size: 1 + description: Timer B output 1 Reset + enum: CPT1DCR_TA1RST + name: TB1RST + - bit_offset: 18 + bit_size: 1 + description: Timer B Compare 1 + enum: CPT1DCR_TACMP1 + name: TBCMP1 + - bit_offset: 19 + bit_size: 1 + description: Timer B Compare 2 + enum: CPT1DCR_TACMP1 + name: TBCMP2 + - bit_offset: 20 + bit_size: 1 + description: Timer C output 1 Set + enum: CPT1DCR_TA1SET + name: TC1SET + - bit_offset: 21 + bit_size: 1 + description: Timer C output 1 Reset + enum: CPT1DCR_TA1RST + name: TC1RST + - bit_offset: 22 + bit_size: 1 + description: Timer C Compare 1 + enum: CPT1DCR_TACMP1 + name: TCCMP1 + - bit_offset: 23 + bit_size: 1 + description: Timer C Compare 2 + enum: CPT1DCR_TACMP1 + name: TCCMP2 + - bit_offset: 28 + bit_size: 1 + description: Timer E output 1 Set + enum: CPT1DCR_TA1SET + name: TE1SET + - bit_offset: 29 + bit_size: 1 + description: Timer E output 1 Reset + enum: CPT1DCR_TA1RST + name: TE1RST + - bit_offset: 30 + bit_size: 1 + description: Timer E Compare 1 + enum: CPT1DCR_TACMP1 + name: TECMP1 + - bit_offset: 31 + bit_size: 1 + description: Timer E Compare 2 + enum: CPT1DCR_TACMP1 + name: TECMP2 +fieldset/CPT1DR: + description: Timerx Capture 1 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Capture 1 value + name: CPT1x +fieldset/CPT1ECR: + description: "Timerx Capture 2 Control\r Register" + fields: + - bit_offset: 0 + bit_size: 1 + description: Software Capture + enum: CPT1ECR_SWCPT + name: SWCPT + - bit_offset: 1 + bit_size: 1 + description: Update Capture + enum: CPT1ECR_UPDCPT + name: UPDCPT + - bit_offset: 2 + bit_size: 1 + description: External Event 1 Capture + enum: CPT1ECR_EXEV1CPT + name: EXEV1CPT + - bit_offset: 3 + bit_size: 1 + description: External Event 2 Capture + enum: CPT1ECR_EXEV1CPT + name: EXEV2CPT + - bit_offset: 4 + bit_size: 1 + description: External Event 3 Capture + enum: CPT1ECR_EXEV1CPT + name: EXEV3CPT + - bit_offset: 5 + bit_size: 1 + description: External Event 4 Capture + enum: CPT1ECR_EXEV1CPT + name: EXEV4CPT + - bit_offset: 6 + bit_size: 1 + description: External Event 5 Capture + enum: CPT1ECR_EXEV1CPT + name: EXEV5CPT + - bit_offset: 7 + bit_size: 1 + description: External Event 6 Capture + enum: CPT1ECR_EXEV1CPT + name: EXEV6CPT + - bit_offset: 8 + bit_size: 1 + description: External Event 7 Capture + enum: CPT1ECR_EXEV1CPT + name: EXEV7CPT + - bit_offset: 9 + bit_size: 1 + description: External Event 8 Capture + enum: CPT1ECR_EXEV1CPT + name: EXEV8CPT + - bit_offset: 10 + bit_size: 1 + description: External Event 9 Capture + enum: CPT1ECR_EXEV1CPT + name: EXEV9CPT + - bit_offset: 11 + bit_size: 1 + description: External Event 10 Capture + enum: CPT1ECR_EXEV1CPT + name: EXEV10CPT + - bit_offset: 12 + bit_size: 1 + description: Timer A output 1 Set + enum: CPT1ECR_TA1SET + name: TA1SET + - bit_offset: 13 + bit_size: 1 + description: Timer A output 1 Reset + enum: CPT1ECR_TA1RST + name: TA1RST + - bit_offset: 14 + bit_size: 1 + description: Timer A Compare 1 + enum: CPT1ECR_TACMP1 + name: TACMP1 + - bit_offset: 15 + bit_size: 1 + description: Timer A Compare 2 + enum: CPT1ECR_TACMP1 + name: TACMP2 + - bit_offset: 16 + bit_size: 1 + description: Timer B output 1 Set + enum: CPT1ECR_TA1SET + name: TB1SET + - bit_offset: 17 + bit_size: 1 + description: Timer B output 1 Reset + enum: CPT1ECR_TA1RST + name: TB1RST + - bit_offset: 18 + bit_size: 1 + description: Timer B Compare 1 + enum: CPT1ECR_TACMP1 + name: TBCMP1 + - bit_offset: 19 + bit_size: 1 + description: Timer B Compare 2 + enum: CPT1ECR_TACMP1 + name: TBCMP2 + - bit_offset: 20 + bit_size: 1 + description: Timer C output 1 Set + enum: CPT1ECR_TA1SET + name: TC1SET + - bit_offset: 21 + bit_size: 1 + description: Timer C output 1 Reset + enum: CPT1ECR_TA1RST + name: TC1RST + - bit_offset: 22 + bit_size: 1 + description: Timer C Compare 1 + enum: CPT1ECR_TACMP1 + name: TCCMP1 + - bit_offset: 23 + bit_size: 1 + description: Timer C Compare 2 + enum: CPT1ECR_TACMP1 + name: TCCMP2 + - bit_offset: 24 + bit_size: 1 + description: Timer D output 1 Set + enum: CPT1ECR_TA1SET + name: TD1SET + - bit_offset: 25 + bit_size: 1 + description: Timer D output 1 Reset + enum: CPT1ECR_TA1RST + name: TD1RST + - bit_offset: 26 + bit_size: 1 + description: Timer D Compare 1 + enum: CPT1ECR_TACMP1 + name: TDCMP1 + - bit_offset: 27 + bit_size: 1 + description: Timer D Compare 2 + enum: CPT1ECR_TACMP1 + name: TDCMP2 +fieldset/CPT1ER: + description: Timerx Capture 1 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Capture 1 value + name: CPT1x +fieldset/CPT2ACR: + description: CPT2xCR + fields: + - bit_offset: 0 + bit_size: 1 + description: Software Capture + enum: CPT2ACR_SWCPT + name: SWCPT + - bit_offset: 1 + bit_size: 1 + description: Update Capture + enum: CPT2ACR_UPDCPT + name: UPDCPT + - bit_offset: 2 + bit_size: 1 + description: External Event 1 Capture + enum: CPT2ACR_EXEV1CPT + name: EXEV1CPT + - bit_offset: 3 + bit_size: 1 + description: External Event 2 Capture + enum: CPT2ACR_EXEV1CPT + name: EXEV2CPT + - bit_offset: 4 + bit_size: 1 + description: External Event 3 Capture + enum: CPT2ACR_EXEV1CPT + name: EXEV3CPT + - bit_offset: 5 + bit_size: 1 + description: External Event 4 Capture + enum: CPT2ACR_EXEV1CPT + name: EXEV4CPT + - bit_offset: 6 + bit_size: 1 + description: External Event 5 Capture + enum: CPT2ACR_EXEV1CPT + name: EXEV5CPT + - bit_offset: 7 + bit_size: 1 + description: External Event 6 Capture + enum: CPT2ACR_EXEV1CPT + name: EXEV6CPT + - bit_offset: 8 + bit_size: 1 + description: External Event 7 Capture + enum: CPT2ACR_EXEV1CPT + name: EXEV7CPT + - bit_offset: 9 + bit_size: 1 + description: External Event 8 Capture + enum: CPT2ACR_EXEV1CPT + name: EXEV8CPT + - bit_offset: 10 + bit_size: 1 + description: External Event 9 Capture + enum: CPT2ACR_EXEV1CPT + name: EXEV9CPT + - bit_offset: 11 + bit_size: 1 + description: External Event 10 Capture + enum: CPT2ACR_EXEV1CPT + name: EXEV10CPT + - bit_offset: 16 + bit_size: 1 + description: Timer B output 1 Set + enum: CPT2ACR_TB1SET + name: TB1SET + - bit_offset: 17 + bit_size: 1 + description: Timer B output 1 Reset + enum: CPT2ACR_TB1RST + name: TB1RST + - bit_offset: 18 + bit_size: 1 + description: Timer B Compare 1 + enum: CPT2ACR_TBCMP1 + name: TBCMP1 + - bit_offset: 19 + bit_size: 1 + description: Timer B Compare 2 + enum: CPT2ACR_TBCMP1 + name: TBCMP2 + - bit_offset: 20 + bit_size: 1 + description: Timer C output 1 Set + enum: CPT2ACR_TB1SET + name: TC1SET + - bit_offset: 21 + bit_size: 1 + description: Timer C output 1 Reset + enum: CPT2ACR_TB1RST + name: TC1RST + - bit_offset: 22 + bit_size: 1 + description: Timer C Compare 1 + enum: CPT2ACR_TBCMP1 + name: TCCMP1 + - bit_offset: 23 + bit_size: 1 + description: Timer C Compare 2 + enum: CPT2ACR_TBCMP1 + name: TCCMP2 + - bit_offset: 24 + bit_size: 1 + description: Timer D output 1 Set + enum: CPT2ACR_TB1SET + name: TD1SET + - bit_offset: 25 + bit_size: 1 + description: Timer D output 1 Reset + enum: CPT2ACR_TB1RST + name: TD1RST + - bit_offset: 26 + bit_size: 1 + description: Timer D Compare 1 + enum: CPT2ACR_TBCMP1 + name: TDCMP1 + - bit_offset: 27 + bit_size: 1 + description: Timer D Compare 2 + enum: CPT2ACR_TBCMP1 + name: TDCMP2 + - bit_offset: 28 + bit_size: 1 + description: Timer E output 1 Set + enum: CPT2ACR_TB1SET + name: TE1SET + - bit_offset: 29 + bit_size: 1 + description: Timer E output 1 Reset + enum: CPT2ACR_TB1RST + name: TE1RST + - bit_offset: 30 + bit_size: 1 + description: Timer E Compare 1 + enum: CPT2ACR_TBCMP1 + name: TECMP1 + - bit_offset: 31 + bit_size: 1 + description: Timer E Compare 2 + enum: CPT2ACR_TBCMP1 + name: TECMP2 +fieldset/CPT2AR: + description: Timerx Capture 2 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Capture 2 value + name: CPT2x +fieldset/CPT2BCR: + description: CPT2xCR + fields: + - bit_offset: 0 + bit_size: 1 + description: Software Capture + enum: CPT2BCR_SWCPT + name: SWCPT + - bit_offset: 1 + bit_size: 1 + description: Update Capture + enum: CPT2BCR_UPDCPT + name: UPDCPT + - bit_offset: 2 + bit_size: 1 + description: External Event 1 Capture + enum: CPT2BCR_EXEV1CPT + name: EXEV1CPT + - bit_offset: 3 + bit_size: 1 + description: External Event 2 Capture + enum: CPT2BCR_EXEV1CPT + name: EXEV2CPT + - bit_offset: 4 + bit_size: 1 + description: External Event 3 Capture + enum: CPT2BCR_EXEV1CPT + name: EXEV3CPT + - bit_offset: 5 + bit_size: 1 + description: External Event 4 Capture + enum: CPT2BCR_EXEV1CPT + name: EXEV4CPT + - bit_offset: 6 + bit_size: 1 + description: External Event 5 Capture + enum: CPT2BCR_EXEV1CPT + name: EXEV5CPT + - bit_offset: 7 + bit_size: 1 + description: External Event 6 Capture + enum: CPT2BCR_EXEV1CPT + name: EXEV6CPT + - bit_offset: 8 + bit_size: 1 + description: External Event 7 Capture + enum: CPT2BCR_EXEV1CPT + name: EXEV7CPT + - bit_offset: 9 + bit_size: 1 + description: External Event 8 Capture + enum: CPT2BCR_EXEV1CPT + name: EXEV8CPT + - bit_offset: 10 + bit_size: 1 + description: External Event 9 Capture + enum: CPT2BCR_EXEV1CPT + name: EXEV9CPT + - bit_offset: 11 + bit_size: 1 + description: External Event 10 Capture + enum: CPT2BCR_EXEV1CPT + name: EXEV10CPT + - bit_offset: 12 + bit_size: 1 + description: Timer A output 1 Set + enum: CPT2BCR_TA1SET + name: TA1SET + - bit_offset: 13 + bit_size: 1 + description: Timer A output 1 Reset + enum: CPT2BCR_TA1RST + name: TA1RST + - bit_offset: 14 + bit_size: 1 + description: Timer A Compare 1 + enum: CPT2BCR_TACMP1 + name: TACMP1 + - bit_offset: 15 + bit_size: 1 + description: Timer A Compare 2 + enum: CPT2BCR_TACMP1 + name: TACMP2 + - bit_offset: 20 + bit_size: 1 + description: Timer C output 1 Set + enum: CPT2BCR_TA1SET + name: TC1SET + - bit_offset: 21 + bit_size: 1 + description: Timer C output 1 Reset + enum: CPT2BCR_TA1RST + name: TC1RST + - bit_offset: 22 + bit_size: 1 + description: Timer C Compare 1 + enum: CPT2BCR_TACMP1 + name: TCCMP1 + - bit_offset: 23 + bit_size: 1 + description: Timer C Compare 2 + enum: CPT2BCR_TACMP1 + name: TCCMP2 + - bit_offset: 24 + bit_size: 1 + description: Timer D output 1 Set + enum: CPT2BCR_TA1SET + name: TD1SET + - bit_offset: 25 + bit_size: 1 + description: Timer D output 1 Reset + enum: CPT2BCR_TA1RST + name: TD1RST + - bit_offset: 26 + bit_size: 1 + description: Timer D Compare 1 + enum: CPT2BCR_TACMP1 + name: TDCMP1 + - bit_offset: 27 + bit_size: 1 + description: Timer D Compare 2 + enum: CPT2BCR_TACMP1 + name: TDCMP2 + - bit_offset: 28 + bit_size: 1 + description: Timer E output 1 Set + enum: CPT2BCR_TA1SET + name: TE1SET + - bit_offset: 29 + bit_size: 1 + description: Timer E output 1 Reset + enum: CPT2BCR_TA1RST + name: TE1RST + - bit_offset: 30 + bit_size: 1 + description: Timer E Compare 1 + enum: CPT2BCR_TACMP1 + name: TECMP1 + - bit_offset: 31 + bit_size: 1 + description: Timer E Compare 2 + enum: CPT2BCR_TACMP1 + name: TECMP2 +fieldset/CPT2BR: + description: Timerx Capture 2 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Capture 2 value + name: CPT2x +fieldset/CPT2CCR: + description: CPT2xCR + fields: + - bit_offset: 0 + bit_size: 1 + description: Software Capture + enum: CPT2CCR_SWCPT + name: SWCPT + - bit_offset: 1 + bit_size: 1 + description: Update Capture + enum: CPT2CCR_UPDCPT + name: UPDCPT + - bit_offset: 2 + bit_size: 1 + description: External Event 1 Capture + enum: CPT2CCR_EXEV1CPT + name: EXEV1CPT + - bit_offset: 3 + bit_size: 1 + description: External Event 2 Capture + enum: CPT2CCR_EXEV1CPT + name: EXEV2CPT + - bit_offset: 4 + bit_size: 1 + description: External Event 3 Capture + enum: CPT2CCR_EXEV1CPT + name: EXEV3CPT + - bit_offset: 5 + bit_size: 1 + description: External Event 4 Capture + enum: CPT2CCR_EXEV1CPT + name: EXEV4CPT + - bit_offset: 6 + bit_size: 1 + description: External Event 5 Capture + enum: CPT2CCR_EXEV1CPT + name: EXEV5CPT + - bit_offset: 7 + bit_size: 1 + description: External Event 6 Capture + enum: CPT2CCR_EXEV1CPT + name: EXEV6CPT + - bit_offset: 8 + bit_size: 1 + description: External Event 7 Capture + enum: CPT2CCR_EXEV1CPT + name: EXEV7CPT + - bit_offset: 9 + bit_size: 1 + description: External Event 8 Capture + enum: CPT2CCR_EXEV1CPT + name: EXEV8CPT + - bit_offset: 10 + bit_size: 1 + description: External Event 9 Capture + enum: CPT2CCR_EXEV1CPT + name: EXEV9CPT + - bit_offset: 11 + bit_size: 1 + description: External Event 10 Capture + enum: CPT2CCR_EXEV1CPT + name: EXEV10CPT + - bit_offset: 12 + bit_size: 1 + description: Timer A output 1 Set + enum: CPT2CCR_TA1SET + name: TA1SET + - bit_offset: 13 + bit_size: 1 + description: Timer A output 1 Reset + enum: CPT2CCR_TA1RST + name: TA1RST + - bit_offset: 14 + bit_size: 1 + description: Timer A Compare 1 + enum: CPT2CCR_TACMP1 + name: TACMP1 + - bit_offset: 15 + bit_size: 1 + description: Timer A Compare 2 + enum: CPT2CCR_TACMP1 + name: TACMP2 + - bit_offset: 16 + bit_size: 1 + description: Timer B output 1 Set + enum: CPT2CCR_TA1SET + name: TB1SET + - bit_offset: 17 + bit_size: 1 + description: Timer B output 1 Reset + enum: CPT2CCR_TA1RST + name: TB1RST + - bit_offset: 18 + bit_size: 1 + description: Timer B Compare 1 + enum: CPT2CCR_TACMP1 + name: TBCMP1 + - bit_offset: 19 + bit_size: 1 + description: Timer B Compare 2 + enum: CPT2CCR_TACMP1 + name: TBCMP2 + - bit_offset: 24 + bit_size: 1 + description: Timer D output 1 Set + enum: CPT2CCR_TA1SET + name: TD1SET + - bit_offset: 25 + bit_size: 1 + description: Timer D output 1 Reset + enum: CPT2CCR_TA1RST + name: TD1RST + - bit_offset: 26 + bit_size: 1 + description: Timer D Compare 1 + enum: CPT2CCR_TACMP1 + name: TDCMP1 + - bit_offset: 27 + bit_size: 1 + description: Timer D Compare 2 + enum: CPT2CCR_TACMP1 + name: TDCMP2 + - bit_offset: 28 + bit_size: 1 + description: Timer E output 1 Set + enum: CPT2CCR_TA1SET + name: TE1SET + - bit_offset: 29 + bit_size: 1 + description: Timer E output 1 Reset + enum: CPT2CCR_TA1RST + name: TE1RST + - bit_offset: 30 + bit_size: 1 + description: Timer E Compare 1 + enum: CPT2CCR_TACMP1 + name: TECMP1 + - bit_offset: 31 + bit_size: 1 + description: Timer E Compare 2 + enum: CPT2CCR_TACMP1 + name: TECMP2 +fieldset/CPT2CR: + description: Timerx Capture 2 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Capture 2 value + name: CPT2x +fieldset/CPT2DCR: + description: CPT2xCR + fields: + - bit_offset: 0 + bit_size: 1 + description: Software Capture + enum: CPT2DCR_SWCPT + name: SWCPT + - bit_offset: 1 + bit_size: 1 + description: Update Capture + enum: CPT2DCR_UPDCPT + name: UPDCPT + - bit_offset: 2 + bit_size: 1 + description: External Event 1 Capture + enum: CPT2DCR_EXEV1CPT + name: EXEV1CPT + - bit_offset: 3 + bit_size: 1 + description: External Event 2 Capture + enum: CPT2DCR_EXEV1CPT + name: EXEV2CPT + - bit_offset: 4 + bit_size: 1 + description: External Event 3 Capture + enum: CPT2DCR_EXEV1CPT + name: EXEV3CPT + - bit_offset: 5 + bit_size: 1 + description: External Event 4 Capture + enum: CPT2DCR_EXEV1CPT + name: EXEV4CPT + - bit_offset: 6 + bit_size: 1 + description: External Event 5 Capture + enum: CPT2DCR_EXEV1CPT + name: EXEV5CPT + - bit_offset: 7 + bit_size: 1 + description: External Event 6 Capture + enum: CPT2DCR_EXEV1CPT + name: EXEV6CPT + - bit_offset: 8 + bit_size: 1 + description: External Event 7 Capture + enum: CPT2DCR_EXEV1CPT + name: EXEV7CPT + - bit_offset: 9 + bit_size: 1 + description: External Event 8 Capture + enum: CPT2DCR_EXEV1CPT + name: EXEV8CPT + - bit_offset: 10 + bit_size: 1 + description: External Event 9 Capture + enum: CPT2DCR_EXEV1CPT + name: EXEV9CPT + - bit_offset: 11 + bit_size: 1 + description: External Event 10 Capture + enum: CPT2DCR_EXEV1CPT + name: EXEV10CPT + - bit_offset: 12 + bit_size: 1 + description: Timer A output 1 Set + enum: CPT2DCR_TA1SET + name: TA1SET + - bit_offset: 13 + bit_size: 1 + description: Timer A output 1 Reset + enum: CPT2DCR_TA1RST + name: TA1RST + - bit_offset: 14 + bit_size: 1 + description: Timer A Compare 1 + enum: CPT2DCR_TACMP1 + name: TACMP1 + - bit_offset: 15 + bit_size: 1 + description: Timer A Compare 2 + enum: CPT2DCR_TACMP1 + name: TACMP2 + - bit_offset: 16 + bit_size: 1 + description: Timer B output 1 Set + enum: CPT2DCR_TA1SET + name: TB1SET + - bit_offset: 17 + bit_size: 1 + description: Timer B output 1 Reset + enum: CPT2DCR_TA1RST + name: TB1RST + - bit_offset: 18 + bit_size: 1 + description: Timer B Compare 1 + enum: CPT2DCR_TACMP1 + name: TBCMP1 + - bit_offset: 19 + bit_size: 1 + description: Timer B Compare 2 + enum: CPT2DCR_TACMP1 + name: TBCMP2 + - bit_offset: 20 + bit_size: 1 + description: Timer C output 1 Set + enum: CPT2DCR_TA1SET + name: TC1SET + - bit_offset: 21 + bit_size: 1 + description: Timer C output 1 Reset + enum: CPT2DCR_TA1RST + name: TC1RST + - bit_offset: 22 + bit_size: 1 + description: Timer C Compare 1 + enum: CPT2DCR_TACMP1 + name: TCCMP1 + - bit_offset: 23 + bit_size: 1 + description: Timer C Compare 2 + enum: CPT2DCR_TACMP1 + name: TCCMP2 + - bit_offset: 28 + bit_size: 1 + description: Timer E output 1 Set + enum: CPT2DCR_TA1SET + name: TE1SET + - bit_offset: 29 + bit_size: 1 + description: Timer E output 1 Reset + enum: CPT2DCR_TA1RST + name: TE1RST + - bit_offset: 30 + bit_size: 1 + description: Timer E Compare 1 + enum: CPT2DCR_TACMP1 + name: TECMP1 + - bit_offset: 31 + bit_size: 1 + description: Timer E Compare 2 + enum: CPT2DCR_TACMP1 + name: TECMP2 +fieldset/CPT2DR: + description: Timerx Capture 2 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Capture 2 value + name: CPT2x +fieldset/CPT2ECR: + description: CPT2xCR + fields: + - bit_offset: 0 + bit_size: 1 + description: Software Capture + enum: CPT2ECR_SWCPT + name: SWCPT + - bit_offset: 1 + bit_size: 1 + description: Update Capture + enum: CPT2ECR_UPDCPT + name: UPDCPT + - bit_offset: 2 + bit_size: 1 + description: External Event 1 Capture + enum: CPT2ECR_EXEV1CPT + name: EXEV1CPT + - bit_offset: 3 + bit_size: 1 + description: External Event 2 Capture + enum: CPT2ECR_EXEV1CPT + name: EXEV2CPT + - bit_offset: 4 + bit_size: 1 + description: External Event 3 Capture + enum: CPT2ECR_EXEV1CPT + name: EXEV3CPT + - bit_offset: 5 + bit_size: 1 + description: External Event 4 Capture + enum: CPT2ECR_EXEV1CPT + name: EXEV4CPT + - bit_offset: 6 + bit_size: 1 + description: External Event 5 Capture + enum: CPT2ECR_EXEV1CPT + name: EXEV5CPT + - bit_offset: 7 + bit_size: 1 + description: External Event 6 Capture + enum: CPT2ECR_EXEV1CPT + name: EXEV6CPT + - bit_offset: 8 + bit_size: 1 + description: External Event 7 Capture + enum: CPT2ECR_EXEV1CPT + name: EXEV7CPT + - bit_offset: 9 + bit_size: 1 + description: External Event 8 Capture + enum: CPT2ECR_EXEV1CPT + name: EXEV8CPT + - bit_offset: 10 + bit_size: 1 + description: External Event 9 Capture + enum: CPT2ECR_EXEV1CPT + name: EXEV9CPT + - bit_offset: 11 + bit_size: 1 + description: External Event 10 Capture + enum: CPT2ECR_EXEV1CPT + name: EXEV10CPT + - bit_offset: 12 + bit_size: 1 + description: Timer A output 1 Set + enum: CPT2ECR_TA1SET + name: TA1SET + - bit_offset: 13 + bit_size: 1 + description: Timer A output 1 Reset + enum: CPT2ECR_TA1RST + name: TA1RST + - bit_offset: 14 + bit_size: 1 + description: Timer A Compare 1 + enum: CPT2ECR_TACMP1 + name: TACMP1 + - bit_offset: 15 + bit_size: 1 + description: Timer A Compare 2 + enum: CPT2ECR_TACMP1 + name: TACMP2 + - bit_offset: 16 + bit_size: 1 + description: Timer B output 1 Set + enum: CPT2ECR_TA1SET + name: TB1SET + - bit_offset: 17 + bit_size: 1 + description: Timer B output 1 Reset + enum: CPT2ECR_TA1RST + name: TB1RST + - bit_offset: 18 + bit_size: 1 + description: Timer B Compare 1 + enum: CPT2ECR_TACMP1 + name: TBCMP1 + - bit_offset: 19 + bit_size: 1 + description: Timer B Compare 2 + enum: CPT2ECR_TACMP1 + name: TBCMP2 + - bit_offset: 20 + bit_size: 1 + description: Timer C output 1 Set + enum: CPT2ECR_TA1SET + name: TC1SET + - bit_offset: 21 + bit_size: 1 + description: Timer C output 1 Reset + enum: CPT2ECR_TA1RST + name: TC1RST + - bit_offset: 22 + bit_size: 1 + description: Timer C Compare 1 + enum: CPT2ECR_TACMP1 + name: TCCMP1 + - bit_offset: 23 + bit_size: 1 + description: Timer C Compare 2 + enum: CPT2ECR_TACMP1 + name: TCCMP2 + - bit_offset: 24 + bit_size: 1 + description: Timer D output 1 Set + enum: CPT2ECR_TA1SET + name: TD1SET + - bit_offset: 25 + bit_size: 1 + description: Timer D output 1 Reset + enum: CPT2ECR_TA1RST + name: TD1RST + - bit_offset: 26 + bit_size: 1 + description: Timer D Compare 1 + enum: CPT2ECR_TACMP1 + name: TDCMP1 + - bit_offset: 27 + bit_size: 1 + description: Timer D Compare 2 + enum: CPT2ECR_TACMP1 + name: TDCMP2 +fieldset/CPT2ER: + description: Timerx Capture 2 Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Capture 2 value + name: CPT2x +fieldset/DTAR: + description: Timerx Deadtime Register + fields: + - bit_offset: 0 + bit_size: 9 + description: Deadtime Rising value + name: DTRx + - bit_offset: 9 + bit_size: 1 + description: Sign Deadtime Rising value + enum: SDTRx + name: SDTRx + - bit_offset: 10 + bit_size: 3 + description: Deadtime Prescaler + name: DTPRSC + - bit_offset: 14 + bit_size: 1 + description: Deadtime Rising Sign Lock + enum: DTRSLKx + name: DTRSLKx + - bit_offset: 15 + bit_size: 1 + description: Deadtime Rising Lock + enum: DTRLKx + name: DTRLKx + - bit_offset: 16 + bit_size: 9 + description: Deadtime Falling value + name: DTFx + - bit_offset: 25 + bit_size: 1 + description: "Sign Deadtime Falling\r value" + enum: SDTFx + name: SDTFx + - bit_offset: 30 + bit_size: 1 + description: Deadtime Falling Sign Lock + enum: DTFSLKx + name: DTFSLKx + - bit_offset: 31 + bit_size: 1 + description: Deadtime Falling Lock + enum: DTFLKx + name: DTFLKx +fieldset/DTBR: + description: Timerx Deadtime Register + fields: + - bit_offset: 0 + bit_size: 9 + description: Deadtime Rising value + name: DTRx + - bit_offset: 9 + bit_size: 1 + description: Sign Deadtime Rising value + enum: SDTRx + name: SDTRx + - bit_offset: 10 + bit_size: 3 + description: Deadtime Prescaler + name: DTPRSC + - bit_offset: 14 + bit_size: 1 + description: Deadtime Rising Sign Lock + enum: DTRSLKx + name: DTRSLKx + - bit_offset: 15 + bit_size: 1 + description: Deadtime Rising Lock + enum: DTRLKx + name: DTRLKx + - bit_offset: 16 + bit_size: 9 + description: Deadtime Falling value + name: DTFx + - bit_offset: 25 + bit_size: 1 + description: "Sign Deadtime Falling\r value" + enum: SDTFx + name: SDTFx + - bit_offset: 30 + bit_size: 1 + description: Deadtime Falling Sign Lock + enum: DTFSLKx + name: DTFSLKx + - bit_offset: 31 + bit_size: 1 + description: Deadtime Falling Lock + enum: DTFLKx + name: DTFLKx +fieldset/DTCR: + description: Timerx Deadtime Register + fields: + - bit_offset: 0 + bit_size: 9 + description: Deadtime Rising value + name: DTRx + - bit_offset: 9 + bit_size: 1 + description: Sign Deadtime Rising value + enum: SDTRx + name: SDTRx + - bit_offset: 10 + bit_size: 3 + description: Deadtime Prescaler + name: DTPRSC + - bit_offset: 14 + bit_size: 1 + description: Deadtime Rising Sign Lock + enum: DTRSLKx + name: DTRSLKx + - bit_offset: 15 + bit_size: 1 + description: Deadtime Rising Lock + enum: DTRLKx + name: DTRLKx + - bit_offset: 16 + bit_size: 9 + description: Deadtime Falling value + name: DTFx + - bit_offset: 25 + bit_size: 1 + description: "Sign Deadtime Falling\r value" + enum: SDTFx + name: SDTFx + - bit_offset: 30 + bit_size: 1 + description: Deadtime Falling Sign Lock + enum: DTFSLKx + name: DTFSLKx + - bit_offset: 31 + bit_size: 1 + description: Deadtime Falling Lock + enum: DTFLKx + name: DTFLKx +fieldset/DTDR: + description: Timerx Deadtime Register + fields: + - bit_offset: 0 + bit_size: 9 + description: Deadtime Rising value + name: DTRx + - bit_offset: 9 + bit_size: 1 + description: Sign Deadtime Rising value + enum: SDTRx + name: SDTRx + - bit_offset: 10 + bit_size: 3 + description: Deadtime Prescaler + name: DTPRSC + - bit_offset: 14 + bit_size: 1 + description: Deadtime Rising Sign Lock + enum: DTRSLKx + name: DTRSLKx + - bit_offset: 15 + bit_size: 1 + description: Deadtime Rising Lock + enum: DTRLKx + name: DTRLKx + - bit_offset: 16 + bit_size: 9 + description: Deadtime Falling value + name: DTFx + - bit_offset: 25 + bit_size: 1 + description: "Sign Deadtime Falling\r value" + enum: SDTFx + name: SDTFx + - bit_offset: 30 + bit_size: 1 + description: Deadtime Falling Sign Lock + enum: DTFSLKx + name: DTFSLKx + - bit_offset: 31 + bit_size: 1 + description: Deadtime Falling Lock + enum: DTFLKx + name: DTFLKx +fieldset/DTER: + description: Timerx Deadtime Register + fields: + - bit_offset: 0 + bit_size: 9 + description: Deadtime Rising value + name: DTRx + - bit_offset: 9 + bit_size: 1 + description: Sign Deadtime Rising value + enum: SDTRx + name: SDTRx + - bit_offset: 10 + bit_size: 3 + description: Deadtime Prescaler + name: DTPRSC + - bit_offset: 14 + bit_size: 1 + description: Deadtime Rising Sign Lock + enum: DTRSLKx + name: DTRSLKx + - bit_offset: 15 + bit_size: 1 + description: Deadtime Rising Lock + enum: DTRLKx + name: DTRLKx + - bit_offset: 16 + bit_size: 9 + description: Deadtime Falling value + name: DTFx + - bit_offset: 25 + bit_size: 1 + description: "Sign Deadtime Falling\r value" + enum: SDTFx + name: SDTFx + - bit_offset: 30 + bit_size: 1 + description: Deadtime Falling Sign Lock + enum: DTFSLKx + name: DTFSLKx + - bit_offset: 31 + bit_size: 1 + description: Deadtime Falling Lock + enum: DTFLKx + name: DTFLKx +fieldset/EEFAR1: + description: "Timerx External Event Filtering Register\r 1" + fields: + - bit_offset: 0 + bit_size: 1 + description: External Event 1 latch + enum: EE1LTCH + name: EE1LTCH + - bit_offset: 1 + bit_size: 4 + description: External Event 1 filter + enum: EE1FLTR + name: EE1FLTR + - bit_offset: 6 + bit_size: 1 + description: External Event 2 latch + enum: EE1LTCH + name: EE2LTCH + - bit_offset: 7 + bit_size: 4 + description: External Event 2 filter + enum: EE1FLTR + name: EE2FLTR + - bit_offset: 12 + bit_size: 1 + description: External Event 3 latch + enum: EE1LTCH + name: EE3LTCH + - bit_offset: 13 + bit_size: 4 + description: External Event 3 filter + enum: EE1FLTR + name: EE3FLTR + - bit_offset: 18 + bit_size: 1 + description: External Event 4 latch + enum: EE1LTCH + name: EE4LTCH + - bit_offset: 19 + bit_size: 4 + description: External Event 4 filter + enum: EE1FLTR + name: EE4FLTR + - bit_offset: 24 + bit_size: 1 + description: External Event 5 latch + enum: EE1LTCH + name: EE5LTCH + - bit_offset: 25 + bit_size: 4 + description: External Event 5 filter + enum: EE1FLTR + name: EE5FLTR +fieldset/EEFAR2: + description: "Timerx External Event Filtering Register\r 2" + fields: + - bit_offset: 0 + bit_size: 1 + description: External Event 6 latch + enum: EE6LTCH + name: EE6LTCH + - bit_offset: 1 + bit_size: 4 + description: External Event 6 filter + enum: EE6FLTR + name: EE6FLTR + - bit_offset: 6 + bit_size: 1 + description: External Event 7 latch + enum: EE6LTCH + name: EE7LTCH + - bit_offset: 7 + bit_size: 4 + description: External Event 7 filter + enum: EE6FLTR + name: EE7FLTR + - bit_offset: 12 + bit_size: 1 + description: External Event 8 latch + enum: EE6LTCH + name: EE8LTCH + - bit_offset: 13 + bit_size: 4 + description: External Event 8 filter + enum: EE6FLTR + name: EE8FLTR + - bit_offset: 18 + bit_size: 1 + description: External Event 9 latch + enum: EE6LTCH + name: EE9LTCH + - bit_offset: 19 + bit_size: 4 + description: External Event 9 filter + enum: EE6FLTR + name: EE9FLTR + - bit_offset: 24 + bit_size: 1 + description: External Event 10 latch + enum: EE6LTCH + name: EE10LTCH + - bit_offset: 25 + bit_size: 4 + description: External Event 10 filter + enum: EE6FLTR + name: EE10FLTR +fieldset/EEFBR1: + description: "Timerx External Event Filtering Register\r 1" + fields: + - bit_offset: 0 + bit_size: 1 + description: External Event 1 latch + enum: EE1LTCH + name: EE1LTCH + - bit_offset: 1 + bit_size: 4 + description: External Event 1 filter + enum: EE1FLTR + name: EE1FLTR + - bit_offset: 6 + bit_size: 1 + description: External Event 2 latch + enum: EE1LTCH + name: EE2LTCH + - bit_offset: 7 + bit_size: 4 + description: External Event 2 filter + enum: EE1FLTR + name: EE2FLTR + - bit_offset: 12 + bit_size: 1 + description: External Event 3 latch + enum: EE1LTCH + name: EE3LTCH + - bit_offset: 13 + bit_size: 4 + description: External Event 3 filter + enum: EE1FLTR + name: EE3FLTR + - bit_offset: 18 + bit_size: 1 + description: External Event 4 latch + enum: EE1LTCH + name: EE4LTCH + - bit_offset: 19 + bit_size: 4 + description: External Event 4 filter + enum: EE1FLTR + name: EE4FLTR + - bit_offset: 24 + bit_size: 1 + description: External Event 5 latch + enum: EE1LTCH + name: EE5LTCH + - bit_offset: 25 + bit_size: 4 + description: External Event 5 filter + enum: EE1FLTR + name: EE5FLTR +fieldset/EEFBR2: + description: "Timerx External Event Filtering Register\r 2" + fields: + - bit_offset: 0 + bit_size: 1 + description: External Event 6 latch + enum: EE6LTCH + name: EE6LTCH + - bit_offset: 1 + bit_size: 4 + description: External Event 6 filter + enum: EE6FLTR + name: EE6FLTR + - bit_offset: 6 + bit_size: 1 + description: External Event 7 latch + enum: EE6LTCH + name: EE7LTCH + - bit_offset: 7 + bit_size: 4 + description: External Event 7 filter + enum: EE6FLTR + name: EE7FLTR + - bit_offset: 12 + bit_size: 1 + description: External Event 8 latch + enum: EE6LTCH + name: EE8LTCH + - bit_offset: 13 + bit_size: 4 + description: External Event 8 filter + enum: EE6FLTR + name: EE8FLTR + - bit_offset: 18 + bit_size: 1 + description: External Event 9 latch + enum: EE6LTCH + name: EE9LTCH + - bit_offset: 19 + bit_size: 4 + description: External Event 9 filter + enum: EE6FLTR + name: EE9FLTR + - bit_offset: 24 + bit_size: 1 + description: External Event 10 latch + enum: EE6LTCH + name: EE10LTCH + - bit_offset: 25 + bit_size: 4 + description: External Event 10 filter + enum: EE6FLTR + name: EE10FLTR +fieldset/EEFCR1: + description: "Timerx External Event Filtering Register\r 1" + fields: + - bit_offset: 0 + bit_size: 1 + description: External Event 1 latch + enum: EE1LTCH + name: EE1LTCH + - bit_offset: 1 + bit_size: 4 + description: External Event 1 filter + enum: EE1FLTR + name: EE1FLTR + - bit_offset: 6 + bit_size: 1 + description: External Event 2 latch + enum: EE1LTCH + name: EE2LTCH + - bit_offset: 7 + bit_size: 4 + description: External Event 2 filter + enum: EE1FLTR + name: EE2FLTR + - bit_offset: 12 + bit_size: 1 + description: External Event 3 latch + enum: EE1LTCH + name: EE3LTCH + - bit_offset: 13 + bit_size: 4 + description: External Event 3 filter + enum: EE1FLTR + name: EE3FLTR + - bit_offset: 18 + bit_size: 1 + description: External Event 4 latch + enum: EE1LTCH + name: EE4LTCH + - bit_offset: 19 + bit_size: 4 + description: External Event 4 filter + enum: EE1FLTR + name: EE4FLTR + - bit_offset: 24 + bit_size: 1 + description: External Event 5 latch + enum: EE1LTCH + name: EE5LTCH + - bit_offset: 25 + bit_size: 4 + description: External Event 5 filter + enum: EE1FLTR + name: EE5FLTR +fieldset/EEFCR2: + description: "Timerx External Event Filtering Register\r 2" + fields: + - bit_offset: 0 + bit_size: 1 + description: External Event 6 latch + enum: EE6LTCH + name: EE6LTCH + - bit_offset: 1 + bit_size: 4 + description: External Event 6 filter + enum: EE6FLTR + name: EE6FLTR + - bit_offset: 6 + bit_size: 1 + description: External Event 7 latch + enum: EE6LTCH + name: EE7LTCH + - bit_offset: 7 + bit_size: 4 + description: External Event 7 filter + enum: EE6FLTR + name: EE7FLTR + - bit_offset: 12 + bit_size: 1 + description: External Event 8 latch + enum: EE6LTCH + name: EE8LTCH + - bit_offset: 13 + bit_size: 4 + description: External Event 8 filter + enum: EE6FLTR + name: EE8FLTR + - bit_offset: 18 + bit_size: 1 + description: External Event 9 latch + enum: EE6LTCH + name: EE9LTCH + - bit_offset: 19 + bit_size: 4 + description: External Event 9 filter + enum: EE6FLTR + name: EE9FLTR + - bit_offset: 24 + bit_size: 1 + description: External Event 10 latch + enum: EE6LTCH + name: EE10LTCH + - bit_offset: 25 + bit_size: 4 + description: External Event 10 filter + enum: EE6FLTR + name: EE10FLTR +fieldset/EEFDR1: + description: "Timerx External Event Filtering Register\r 1" + fields: + - bit_offset: 0 + bit_size: 1 + description: External Event 1 latch + enum: EE1LTCH + name: EE1LTCH + - bit_offset: 1 + bit_size: 4 + description: External Event 1 filter + enum: EE1FLTR + name: EE1FLTR + - bit_offset: 6 + bit_size: 1 + description: External Event 2 latch + enum: EE1LTCH + name: EE2LTCH + - bit_offset: 7 + bit_size: 4 + description: External Event 2 filter + enum: EE1FLTR + name: EE2FLTR + - bit_offset: 12 + bit_size: 1 + description: External Event 3 latch + enum: EE1LTCH + name: EE3LTCH + - bit_offset: 13 + bit_size: 4 + description: External Event 3 filter + enum: EE1FLTR + name: EE3FLTR + - bit_offset: 18 + bit_size: 1 + description: External Event 4 latch + enum: EE1LTCH + name: EE4LTCH + - bit_offset: 19 + bit_size: 4 + description: External Event 4 filter + enum: EE1FLTR + name: EE4FLTR + - bit_offset: 24 + bit_size: 1 + description: External Event 5 latch + enum: EE1LTCH + name: EE5LTCH + - bit_offset: 25 + bit_size: 4 + description: External Event 5 filter + enum: EE1FLTR + name: EE5FLTR +fieldset/EEFDR2: + description: "Timerx External Event Filtering Register\r 2" + fields: + - bit_offset: 0 + bit_size: 1 + description: External Event 6 latch + enum: EE6LTCH + name: EE6LTCH + - bit_offset: 1 + bit_size: 4 + description: External Event 6 filter + enum: EE6FLTR + name: EE6FLTR + - bit_offset: 6 + bit_size: 1 + description: External Event 7 latch + enum: EE6LTCH + name: EE7LTCH + - bit_offset: 7 + bit_size: 4 + description: External Event 7 filter + enum: EE6FLTR + name: EE7FLTR + - bit_offset: 12 + bit_size: 1 + description: External Event 8 latch + enum: EE6LTCH + name: EE8LTCH + - bit_offset: 13 + bit_size: 4 + description: External Event 8 filter + enum: EE6FLTR + name: EE8FLTR + - bit_offset: 18 + bit_size: 1 + description: External Event 9 latch + enum: EE6LTCH + name: EE9LTCH + - bit_offset: 19 + bit_size: 4 + description: External Event 9 filter + enum: EE6FLTR + name: EE9FLTR + - bit_offset: 24 + bit_size: 1 + description: External Event 10 latch + enum: EE6LTCH + name: EE10LTCH + - bit_offset: 25 + bit_size: 4 + description: External Event 10 filter + enum: EE6FLTR + name: EE10FLTR +fieldset/EEFER1: + description: "Timerx External Event Filtering Register\r 1" + fields: + - bit_offset: 0 + bit_size: 1 + description: External Event 1 latch + enum: EE1LTCH + name: EE1LTCH + - bit_offset: 1 + bit_size: 4 + description: External Event 1 filter + enum: EE1FLTR + name: EE1FLTR + - bit_offset: 6 + bit_size: 1 + description: External Event 2 latch + enum: EE1LTCH + name: EE2LTCH + - bit_offset: 7 + bit_size: 4 + description: External Event 2 filter + enum: EE1FLTR + name: EE2FLTR + - bit_offset: 12 + bit_size: 1 + description: External Event 3 latch + enum: EE1LTCH + name: EE3LTCH + - bit_offset: 13 + bit_size: 4 + description: External Event 3 filter + enum: EE1FLTR + name: EE3FLTR + - bit_offset: 18 + bit_size: 1 + description: External Event 4 latch + enum: EE1LTCH + name: EE4LTCH + - bit_offset: 19 + bit_size: 4 + description: External Event 4 filter + enum: EE1FLTR + name: EE4FLTR + - bit_offset: 24 + bit_size: 1 + description: External Event 5 latch + enum: EE1LTCH + name: EE5LTCH + - bit_offset: 25 + bit_size: 4 + description: External Event 5 filter + enum: EE1FLTR + name: EE5FLTR +fieldset/EEFER2: + description: "Timerx External Event Filtering Register\r 2" + fields: + - bit_offset: 0 + bit_size: 1 + description: External Event 6 latch + enum: EE6LTCH + name: EE6LTCH + - bit_offset: 1 + bit_size: 4 + description: External Event 6 filter + enum: EE6FLTR + name: EE6FLTR + - bit_offset: 6 + bit_size: 1 + description: External Event 7 latch + enum: EE6LTCH + name: EE7LTCH + - bit_offset: 7 + bit_size: 4 + description: External Event 7 filter + enum: EE6FLTR + name: EE7FLTR + - bit_offset: 12 + bit_size: 1 + description: External Event 8 latch + enum: EE6LTCH + name: EE8LTCH + - bit_offset: 13 + bit_size: 4 + description: External Event 8 filter + enum: EE6FLTR + name: EE8FLTR + - bit_offset: 18 + bit_size: 1 + description: External Event 9 latch + enum: EE6LTCH + name: EE9LTCH + - bit_offset: 19 + bit_size: 4 + description: External Event 9 filter + enum: EE6FLTR + name: EE9FLTR + - bit_offset: 24 + bit_size: 1 + description: External Event 10 latch + enum: EE6LTCH + name: EE10LTCH + - bit_offset: 25 + bit_size: 4 + description: External Event 10 filter + enum: EE6FLTR + name: EE10FLTR +fieldset/FLTAR: + description: Timerx Fault Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Fault 1 enable + enum: FLT1EN + name: FLT1EN + - bit_offset: 1 + bit_size: 1 + description: Fault 2 enable + enum: FLT1EN + name: FLT2EN + - bit_offset: 2 + bit_size: 1 + description: Fault 3 enable + enum: FLT1EN + name: FLT3EN + - bit_offset: 3 + bit_size: 1 + description: Fault 4 enable + enum: FLT1EN + name: FLT4EN + - bit_offset: 4 + bit_size: 1 + description: Fault 5 enable + enum: FLT1EN + name: FLT5EN + - bit_offset: 31 + bit_size: 1 + description: Fault sources Lock + enum: FLTLCK + name: FLTLCK +fieldset/FLTBR: + description: Timerx Fault Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Fault 1 enable + enum: FLT1EN + name: FLT1EN + - bit_offset: 1 + bit_size: 1 + description: Fault 2 enable + enum: FLT1EN + name: FLT2EN + - bit_offset: 2 + bit_size: 1 + description: Fault 3 enable + enum: FLT1EN + name: FLT3EN + - bit_offset: 3 + bit_size: 1 + description: Fault 4 enable + enum: FLT1EN + name: FLT4EN + - bit_offset: 4 + bit_size: 1 + description: Fault 5 enable + enum: FLT1EN + name: FLT5EN + - bit_offset: 31 + bit_size: 1 + description: Fault sources Lock + enum: FLTLCK + name: FLTLCK +fieldset/FLTCR: + description: Timerx Fault Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Fault 1 enable + enum: FLT1EN + name: FLT1EN + - bit_offset: 1 + bit_size: 1 + description: Fault 2 enable + enum: FLT1EN + name: FLT2EN + - bit_offset: 2 + bit_size: 1 + description: Fault 3 enable + enum: FLT1EN + name: FLT3EN + - bit_offset: 3 + bit_size: 1 + description: Fault 4 enable + enum: FLT1EN + name: FLT4EN + - bit_offset: 4 + bit_size: 1 + description: Fault 5 enable + enum: FLT1EN + name: FLT5EN + - bit_offset: 31 + bit_size: 1 + description: Fault sources Lock + enum: FLTLCK + name: FLTLCK +fieldset/FLTDR: + description: Timerx Fault Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Fault 1 enable + enum: FLT1EN + name: FLT1EN + - bit_offset: 1 + bit_size: 1 + description: Fault 2 enable + enum: FLT1EN + name: FLT2EN + - bit_offset: 2 + bit_size: 1 + description: Fault 3 enable + enum: FLT1EN + name: FLT3EN + - bit_offset: 3 + bit_size: 1 + description: Fault 4 enable + enum: FLT1EN + name: FLT4EN + - bit_offset: 4 + bit_size: 1 + description: Fault 5 enable + enum: FLT1EN + name: FLT5EN + - bit_offset: 31 + bit_size: 1 + description: Fault sources Lock + enum: FLTLCK + name: FLTLCK +fieldset/FLTER: + description: Timerx Fault Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Fault 1 enable + enum: FLT1EN + name: FLT1EN + - bit_offset: 1 + bit_size: 1 + description: Fault 2 enable + enum: FLT1EN + name: FLT2EN + - bit_offset: 2 + bit_size: 1 + description: Fault 3 enable + enum: FLT1EN + name: FLT3EN + - bit_offset: 3 + bit_size: 1 + description: Fault 4 enable + enum: FLT1EN + name: FLT4EN + - bit_offset: 4 + bit_size: 1 + description: Fault 5 enable + enum: FLT1EN + name: FLT5EN + - bit_offset: 31 + bit_size: 1 + description: Fault sources Lock + enum: FLTLCK + name: FLTLCK +fieldset/MCMP1R: + description: "Master Timer Compare 1\r Register" + fields: + - bit_offset: 0 + bit_size: 16 + description: "Master Timer Compare 1\r value" + name: MCMP1 +fieldset/MCMP2R: + description: "Master Timer Compare 2\r Register" + fields: + - bit_offset: 0 + bit_size: 16 + description: "Master Timer Compare 2\r value" + name: MCMP2 +fieldset/MCMP3R: + description: "Master Timer Compare 3\r Register" + fields: + - bit_offset: 0 + bit_size: 16 + description: "Master Timer Compare 3\r value" + name: MCMP3 +fieldset/MCMP4R: + description: "Master Timer Compare 4\r Register" + fields: + - bit_offset: 0 + bit_size: 16 + description: "Master Timer Compare 4\r value" + name: MCMP4 +fieldset/MCNTR: + description: Master Timer Counter Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Counter value + name: MCNT +fieldset/MCR: + description: Master Timer Control Register + fields: + - bit_offset: 0 + bit_size: 3 + description: "HRTIM Master Clock\r prescaler" + name: CKPSC + - bit_offset: 3 + bit_size: 1 + description: Master Continuous mode + enum: CONT + name: CONT + - bit_offset: 4 + bit_size: 1 + description: Master Re-triggerable mode + enum: RETRIG + name: RETRIG + - bit_offset: 5 + bit_size: 1 + description: Half mode enable + enum: HALF + name: HALF + - bit_offset: 8 + bit_size: 2 + description: ynchronization input + enum: SYNCIN + name: SYNCIN + - bit_offset: 10 + bit_size: 1 + description: "Synchronization Resets\r Master" + enum: SYNCRSTM + name: SYNCRSTM + - bit_offset: 11 + bit_size: 1 + description: "Synchronization Starts\r Master" + enum: SYNCSTRTM + name: SYNCSTRTM + - bit_offset: 12 + bit_size: 2 + description: Synchronization output + enum: SYNCOUT + name: SYNCOUT + - bit_offset: 14 + bit_size: 2 + description: Synchronization source + enum: SYNCSRC + name: SYNCSRC + - bit_offset: 16 + bit_size: 1 + description: Master Counter enable + enum: MCEN + name: MCEN + - bit_offset: 17 + bit_size: 1 + description: Timer A counter enable + enum: TACEN + name: TACEN + - bit_offset: 18 + bit_size: 1 + description: Timer B counter enable + enum: TACEN + name: TBCEN + - bit_offset: 19 + bit_size: 1 + description: Timer C counter enable + enum: TACEN + name: TCCEN + - bit_offset: 20 + bit_size: 1 + description: Timer D counter enable + enum: TACEN + name: TDCEN + - bit_offset: 21 + bit_size: 1 + description: Timer E counter enable + enum: TACEN + name: TECEN + - bit_offset: 25 + bit_size: 2 + description: AC Synchronization + enum: DACSYNC + name: DACSYNC + - bit_offset: 27 + bit_size: 1 + description: Preload enable + enum: PREEN + name: PREEN + - bit_offset: 29 + bit_size: 1 + description: "Master Timer Repetition\r update" + enum: MREPU + name: MREPU + - bit_offset: 30 + bit_size: 2 + description: Burst DMA Update + enum: BRSTDMA + name: BRSTDMA +fieldset/MDIER: + description: MDIER4 + fields: + - bit_offset: 0 + bit_size: 1 + description: MCMP1IE + enum: MCMP1IE + name: MCMP1IE + - bit_offset: 1 + bit_size: 1 + description: MCMP2IE + enum: MCMP1IE + name: MCMP2IE + - bit_offset: 2 + bit_size: 1 + description: MCMP3IE + enum: MCMP1IE + name: MCMP3IE + - bit_offset: 3 + bit_size: 1 + description: MCMP4IE + enum: MCMP1IE + name: MCMP4IE + - bit_offset: 4 + bit_size: 1 + description: MREPIE + enum: MCMP1IE + name: MREPIE + - bit_offset: 5 + bit_size: 1 + description: SYNCIE + enum: MCMP1IE + name: SYNCIE + - bit_offset: 6 + bit_size: 1 + description: MUPDIE + enum: MCMP1IE + name: MUPDIE + - bit_offset: 16 + bit_size: 1 + description: MCMP1DE + enum: MCMP1DE + name: MCMP1DE + - bit_offset: 17 + bit_size: 1 + description: MCMP2DE + enum: MCMP1DE + name: MCMP2DE + - bit_offset: 18 + bit_size: 1 + description: MCMP3DE + enum: MCMP1DE + name: MCMP3DE + - bit_offset: 19 + bit_size: 1 + description: MCMP4DE + enum: MCMP1DE + name: MCMP4DE + - bit_offset: 20 + bit_size: 1 + description: MREPDE + enum: MCMP1DE + name: MREPDE + - bit_offset: 21 + bit_size: 1 + description: SYNCDE + enum: MCMP1DE + name: SYNCDE + - bit_offset: 22 + bit_size: 1 + description: MUPDDE + enum: MCMP1DE + name: MUPDDE +fieldset/MICR: + description: "Master Timer Interrupt Clear\r Register" + fields: + - bit_offset: 0 + bit_size: 1 + description: "Master Compare 1 Interrupt flag\r clear" + enum_write: MCMP1C + name: MCMP1C + - bit_offset: 1 + bit_size: 1 + description: "Master Compare 2 Interrupt flag\r clear" + enum_write: MCMP1C + name: MCMP2C + - bit_offset: 2 + bit_size: 1 + description: "Master Compare 3 Interrupt flag\r clear" + enum_write: MCMP1C + name: MCMP3C + - bit_offset: 3 + bit_size: 1 + description: "Master Compare 4 Interrupt flag\r clear" + enum_write: MCMP1C + name: MCMP4C + - bit_offset: 4 + bit_size: 1 + description: "Repetition Interrupt flag\r clear" + enum_write: MCMP1C + name: MREPC + - bit_offset: 5 + bit_size: 1 + description: "Sync Input Interrupt flag\r clear" + enum_write: MCMP1C + name: SYNCC + - bit_offset: 6 + bit_size: 1 + description: "Master update Interrupt flag\r clear" + enum_write: MCMP1C + name: MUPDC +fieldset/MISR: + description: "Master Timer Interrupt Status\r Register" + fields: + - bit_offset: 0 + bit_size: 1 + description: "Master Compare 1 Interrupt\r Flag" + enum_read: MCMP1 + name: MCMP1 + - bit_offset: 1 + bit_size: 1 + description: "Master Compare 2 Interrupt\r Flag" + enum_read: MCMP1 + name: MCMP2 + - bit_offset: 2 + bit_size: 1 + description: "Master Compare 3 Interrupt\r Flag" + enum_read: MCMP1 + name: MCMP3 + - bit_offset: 3 + bit_size: 1 + description: "Master Compare 4 Interrupt\r Flag" + enum_read: MCMP1 + name: MCMP4 + - bit_offset: 4 + bit_size: 1 + description: "Master Repetition Interrupt\r Flag" + enum_read: MREP + name: MREP + - bit_offset: 5 + bit_size: 1 + description: Sync Input Interrupt Flag + enum_read: SYNC + name: SYNC + - bit_offset: 6 + bit_size: 1 + description: "Master Update Interrupt\r Flag" + enum_read: MUPD + name: MUPD +fieldset/MPER: + description: Master Timer Period Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Master Timer Period value + name: MPER +fieldset/MREP: + description: "Master Timer Repetition\r Register" + fields: + - bit_offset: 0 + bit_size: 8 + description: "Master Timer Repetition counter\r value" + name: MREP +fieldset/OUTAR: + description: Timerx Output Register + fields: + - bit_offset: 1 + bit_size: 1 + description: Output 1 polarity + enum: POL1 + name: POL1 + - bit_offset: 2 + bit_size: 1 + description: Output 1 Idle mode + enum: IDLEM1 + name: IDLEM1 + - bit_offset: 3 + bit_size: 1 + description: Output 1 Idle State + enum: IDLES1 + name: IDLES1 + - bit_offset: 4 + bit_size: 2 + description: Output 1 Fault state + enum: FAULT1 + name: FAULT1 + - bit_offset: 6 + bit_size: 1 + description: Output 1 Chopper enable + enum: CHP1 + name: CHP1 + - bit_offset: 7 + bit_size: 1 + description: "Output 1 Deadtime upon burst mode Idle\r entry" + enum: DIDL1 + name: DIDL1 + - bit_offset: 8 + bit_size: 1 + description: Deadtime enable + enum: DTEN + name: DTEN + - bit_offset: 9 + bit_size: 1 + description: Delayed Protection Enable + enum: DLYPRTEN + name: DLYPRTEN + - bit_offset: 10 + bit_size: 3 + description: Delayed Protection + enum: OUTAR_DLYPRT + name: DLYPRT + - bit_offset: 17 + bit_size: 1 + description: Output 2 polarity + enum: POL1 + name: POL2 + - bit_offset: 18 + bit_size: 1 + description: Output 2 Idle mode + enum: IDLEM1 + name: IDLEM2 + - bit_offset: 19 + bit_size: 1 + description: Output 2 Idle State + enum: IDLES1 + name: IDLES2 + - bit_offset: 20 + bit_size: 2 + description: Output 2 Fault state + enum: FAULT1 + name: FAULT2 + - bit_offset: 22 + bit_size: 1 + description: Output 2 Chopper enable + enum: CHP1 + name: CHP2 + - bit_offset: 23 + bit_size: 1 + description: "Output 2 Deadtime upon burst mode Idle\r entry" + enum: DIDL1 + name: DIDL2 +fieldset/OUTBR: + description: Timerx Output Register + fields: + - bit_offset: 1 + bit_size: 1 + description: Output 1 polarity + enum: POL1 + name: POL1 + - bit_offset: 2 + bit_size: 1 + description: Output 1 Idle mode + enum: IDLEM1 + name: IDLEM1 + - bit_offset: 3 + bit_size: 1 + description: Output 1 Idle State + enum: IDLES1 + name: IDLES1 + - bit_offset: 4 + bit_size: 2 + description: Output 1 Fault state + enum: FAULT1 + name: FAULT1 + - bit_offset: 6 + bit_size: 1 + description: Output 1 Chopper enable + enum: CHP1 + name: CHP1 + - bit_offset: 7 + bit_size: 1 + description: "Output 1 Deadtime upon burst mode Idle\r entry" + enum: DIDL1 + name: DIDL1 + - bit_offset: 8 + bit_size: 1 + description: Deadtime enable + enum: DTEN + name: DTEN + - bit_offset: 9 + bit_size: 1 + description: Delayed Protection Enable + enum: DLYPRTEN + name: DLYPRTEN + - bit_offset: 10 + bit_size: 3 + description: Delayed Protection + enum: OUTBR_DLYPRT + name: DLYPRT + - bit_offset: 17 + bit_size: 1 + description: Output 2 polarity + enum: POL1 + name: POL2 + - bit_offset: 18 + bit_size: 1 + description: Output 2 Idle mode + enum: IDLEM1 + name: IDLEM2 + - bit_offset: 19 + bit_size: 1 + description: Output 2 Idle State + enum: IDLES1 + name: IDLES2 + - bit_offset: 20 + bit_size: 2 + description: Output 2 Fault state + enum: FAULT1 + name: FAULT2 + - bit_offset: 22 + bit_size: 1 + description: Output 2 Chopper enable + enum: CHP1 + name: CHP2 + - bit_offset: 23 + bit_size: 1 + description: "Output 2 Deadtime upon burst mode Idle\r entry" + enum: DIDL1 + name: DIDL2 +fieldset/OUTCR: + description: Timerx Output Register + fields: + - bit_offset: 1 + bit_size: 1 + description: Output 1 polarity + enum: POL1 + name: POL1 + - bit_offset: 2 + bit_size: 1 + description: Output 1 Idle mode + enum: IDLEM1 + name: IDLEM1 + - bit_offset: 3 + bit_size: 1 + description: Output 1 Idle State + enum: IDLES1 + name: IDLES1 + - bit_offset: 4 + bit_size: 2 + description: Output 1 Fault state + enum: FAULT1 + name: FAULT1 + - bit_offset: 6 + bit_size: 1 + description: Output 1 Chopper enable + enum: CHP1 + name: CHP1 + - bit_offset: 7 + bit_size: 1 + description: "Output 1 Deadtime upon burst mode Idle\r entry" + enum: DIDL1 + name: DIDL1 + - bit_offset: 8 + bit_size: 1 + description: Deadtime enable + enum: DTEN + name: DTEN + - bit_offset: 9 + bit_size: 1 + description: Delayed Protection Enable + enum: DLYPRTEN + name: DLYPRTEN + - bit_offset: 10 + bit_size: 3 + description: Delayed Protection + enum: OUTCR_DLYPRT + name: DLYPRT + - bit_offset: 17 + bit_size: 1 + description: Output 2 polarity + enum: POL1 + name: POL2 + - bit_offset: 18 + bit_size: 1 + description: Output 2 Idle mode + enum: IDLEM1 + name: IDLEM2 + - bit_offset: 19 + bit_size: 1 + description: Output 2 Idle State + enum: IDLES1 + name: IDLES2 + - bit_offset: 20 + bit_size: 2 + description: Output 2 Fault state + enum: FAULT1 + name: FAULT2 + - bit_offset: 22 + bit_size: 1 + description: Output 2 Chopper enable + enum: CHP1 + name: CHP2 + - bit_offset: 23 + bit_size: 1 + description: "Output 2 Deadtime upon burst mode Idle\r entry" + enum: DIDL1 + name: DIDL2 +fieldset/OUTDR: + description: Timerx Output Register + fields: + - bit_offset: 1 + bit_size: 1 + description: Output 1 polarity + enum: POL1 + name: POL1 + - bit_offset: 2 + bit_size: 1 + description: Output 1 Idle mode + enum: IDLEM1 + name: IDLEM1 + - bit_offset: 3 + bit_size: 1 + description: Output 1 Idle State + enum: IDLES1 + name: IDLES1 + - bit_offset: 4 + bit_size: 2 + description: Output 1 Fault state + enum: FAULT1 + name: FAULT1 + - bit_offset: 6 + bit_size: 1 + description: Output 1 Chopper enable + enum: CHP1 + name: CHP1 + - bit_offset: 7 + bit_size: 1 + description: "Output 1 Deadtime upon burst mode Idle\r entry" + enum: DIDL1 + name: DIDL1 + - bit_offset: 8 + bit_size: 1 + description: Deadtime enable + enum: DTEN + name: DTEN + - bit_offset: 9 + bit_size: 1 + description: Delayed Protection Enable + enum: DLYPRTEN + name: DLYPRTEN + - bit_offset: 10 + bit_size: 3 + description: Delayed Protection + enum: OUTDR_DLYPRT + name: DLYPRT + - bit_offset: 17 + bit_size: 1 + description: Output 2 polarity + enum: POL1 + name: POL2 + - bit_offset: 18 + bit_size: 1 + description: Output 2 Idle mode + enum: IDLEM1 + name: IDLEM2 + - bit_offset: 19 + bit_size: 1 + description: Output 2 Idle State + enum: IDLES1 + name: IDLES2 + - bit_offset: 20 + bit_size: 2 + description: Output 2 Fault state + enum: FAULT1 + name: FAULT2 + - bit_offset: 22 + bit_size: 1 + description: Output 2 Chopper enable + enum: CHP1 + name: CHP2 + - bit_offset: 23 + bit_size: 1 + description: "Output 2 Deadtime upon burst mode Idle\r entry" + enum: DIDL1 + name: DIDL2 +fieldset/OUTER: + description: Timerx Output Register + fields: + - bit_offset: 1 + bit_size: 1 + description: Output 1 polarity + enum: POL1 + name: POL1 + - bit_offset: 2 + bit_size: 1 + description: Output 1 Idle mode + enum: IDLEM1 + name: IDLEM1 + - bit_offset: 3 + bit_size: 1 + description: Output 1 Idle State + enum: IDLES1 + name: IDLES1 + - bit_offset: 4 + bit_size: 2 + description: Output 1 Fault state + enum: FAULT1 + name: FAULT1 + - bit_offset: 6 + bit_size: 1 + description: Output 1 Chopper enable + enum: CHP1 + name: CHP1 + - bit_offset: 7 + bit_size: 1 + description: "Output 1 Deadtime upon burst mode Idle\r entry" + enum: DIDL1 + name: DIDL1 + - bit_offset: 8 + bit_size: 1 + description: Deadtime enable + enum: DTEN + name: DTEN + - bit_offset: 9 + bit_size: 1 + description: Delayed Protection Enable + enum: DLYPRTEN + name: DLYPRTEN + - bit_offset: 10 + bit_size: 3 + description: Delayed Protection + enum: OUTER_DLYPRT + name: DLYPRT + - bit_offset: 17 + bit_size: 1 + description: Output 2 polarity + enum: POL1 + name: POL2 + - bit_offset: 18 + bit_size: 1 + description: Output 2 Idle mode + enum: IDLEM1 + name: IDLEM2 + - bit_offset: 19 + bit_size: 1 + description: Output 2 Idle State + enum: IDLES1 + name: IDLES2 + - bit_offset: 20 + bit_size: 2 + description: Output 2 Fault state + enum: FAULT1 + name: FAULT2 + - bit_offset: 22 + bit_size: 1 + description: Output 2 Chopper enable + enum: CHP1 + name: CHP2 + - bit_offset: 23 + bit_size: 1 + description: "Output 2 Deadtime upon burst mode Idle\r entry" + enum: DIDL1 + name: DIDL2 +fieldset/PERAR: + description: Timerx Period Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Period value + name: PERx +fieldset/PERBR: + description: Timerx Period Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Period value + name: PERx +fieldset/PERCR: + description: Timerx Period Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Period value + name: PERx +fieldset/PERDR: + description: Timerx Period Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Period value + name: PERx +fieldset/PERER: + description: Timerx Period Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timerx Period value + name: PERx +fieldset/REPAR: + description: Timerx Repetition Register + fields: + - bit_offset: 0 + bit_size: 8 + description: "Timerx Repetition counter\r value" + name: REPx +fieldset/REPBR: + description: Timerx Repetition Register + fields: + - bit_offset: 0 + bit_size: 8 + description: "Timerx Repetition counter\r value" + name: REPx +fieldset/REPCR: + description: Timerx Repetition Register + fields: + - bit_offset: 0 + bit_size: 8 + description: "Timerx Repetition counter\r value" + name: REPx +fieldset/REPDR: + description: Timerx Repetition Register + fields: + - bit_offset: 0 + bit_size: 8 + description: "Timerx Repetition counter\r value" + name: REPx +fieldset/REPER: + description: Timerx Repetition Register + fields: + - bit_offset: 0 + bit_size: 8 + description: "Timerx Repetition counter\r value" + name: REPx +fieldset/RSTA1R: + description: Timerx Output1 Reset Register + fields: + - bit_offset: 0 + bit_size: 1 + description: SRT + enum: RSTA1R_SRT + name: SRT + - bit_offset: 1 + bit_size: 1 + description: RESYNC + enum: RSTA1R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: PER + enum: RSTA1R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: CMP1 + enum: RSTA1R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: CMP2 + enum: RSTA1R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: CMP3 + enum: RSTA1R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: CMP4 + enum: RSTA1R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: MSTPER + enum: RSTA1R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: MSTCMP1 + enum: RSTA1R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: MSTCMP2 + enum: RSTA1R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: MSTCMP3 + enum: RSTA1R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: MSTCMP4 + enum: RSTA1R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: TIMEVNT1 + enum: RSTA1R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: TIMEVNT2 + enum: RSTA1R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: TIMEVNT3 + enum: RSTA1R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: TIMEVNT4 + enum: RSTA1R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: TIMEVNT5 + enum: RSTA1R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: TIMEVNT6 + enum: RSTA1R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: TIMEVNT7 + enum: RSTA1R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: TIMEVNT8 + enum: RSTA1R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: TIMEVNT9 + enum: RSTA1R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: EXTEVNT1 + enum: RSTA1R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: EXTEVNT2 + enum: RSTA1R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: EXTEVNT3 + enum: RSTA1R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: EXTEVNT4 + enum: RSTA1R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: EXTEVNT5 + enum: RSTA1R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: EXTEVNT6 + enum: RSTA1R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: EXTEVNT7 + enum: RSTA1R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: EXTEVNT8 + enum: RSTA1R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: EXTEVNT9 + enum: RSTA1R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: EXTEVNT10 + enum: RSTA1R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: UPDATE + enum: RSTA1R_UPDATE + name: UPDATE +fieldset/RSTA2R: + description: Timerx Output2 Reset Register + fields: + - bit_offset: 0 + bit_size: 1 + description: SRT + enum: RSTA2R_SRT + name: SRT + - bit_offset: 1 + bit_size: 1 + description: RESYNC + enum: RSTA2R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: PER + enum: RSTA2R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: CMP1 + enum: RSTA2R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: CMP2 + enum: RSTA2R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: CMP3 + enum: RSTA2R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: CMP4 + enum: RSTA2R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: MSTPER + enum: RSTA2R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: MSTCMP1 + enum: RSTA2R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: MSTCMP2 + enum: RSTA2R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: MSTCMP3 + enum: RSTA2R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: MSTCMP4 + enum: RSTA2R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: TIMEVNT1 + enum: RSTA2R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: TIMEVNT2 + enum: RSTA2R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: TIMEVNT3 + enum: RSTA2R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: TIMEVNT4 + enum: RSTA2R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: TIMEVNT5 + enum: RSTA2R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: TIMEVNT6 + enum: RSTA2R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: TIMEVNT7 + enum: RSTA2R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: TIMEVNT8 + enum: RSTA2R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: TIMEVNT9 + enum: RSTA2R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: EXTEVNT1 + enum: RSTA2R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: EXTEVNT2 + enum: RSTA2R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: EXTEVNT3 + enum: RSTA2R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: EXTEVNT4 + enum: RSTA2R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: EXTEVNT5 + enum: RSTA2R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: EXTEVNT6 + enum: RSTA2R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: EXTEVNT7 + enum: RSTA2R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: EXTEVNT8 + enum: RSTA2R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: EXTEVNT9 + enum: RSTA2R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: EXTEVNT10 + enum: RSTA2R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: UPDATE + enum: RSTA2R_UPDATE + name: UPDATE +fieldset/RSTAR: + description: TimerA Reset Register + fields: + - bit_offset: 1 + bit_size: 1 + description: Timer A Update reset + enum: UPDT + name: UPDT + - bit_offset: 2 + bit_size: 1 + description: Timer A compare 2 reset + enum: CMP2 + name: CMP2 + - bit_offset: 3 + bit_size: 1 + description: Timer A compare 4 reset + enum: CMP2 + name: CMP4 + - bit_offset: 4 + bit_size: 1 + description: Master timer Period + enum: RSTAR_MSTPER + name: MSTPER + - bit_offset: 5 + bit_size: 1 + description: Master compare 1 + enum: RSTAR_MSTCMP1 + name: MSTCMP1 + - bit_offset: 6 + bit_size: 1 + description: Master compare 2 + enum: RSTAR_MSTCMP1 + name: MSTCMP2 + - bit_offset: 7 + bit_size: 1 + description: Master compare 3 + enum: RSTAR_MSTCMP1 + name: MSTCMP3 + - bit_offset: 8 + bit_size: 1 + description: Master compare 4 + enum: RSTAR_MSTCMP1 + name: MSTCMP4 + - bit_offset: 9 + bit_size: 1 + description: External Event 1 + enum: RSTAR_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 10 + bit_size: 1 + description: External Event 2 + enum: RSTAR_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 11 + bit_size: 1 + description: External Event 3 + enum: RSTAR_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 12 + bit_size: 1 + description: External Event 4 + enum: RSTAR_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 13 + bit_size: 1 + description: External Event 5 + enum: RSTAR_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 14 + bit_size: 1 + description: External Event 6 + enum: RSTAR_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 15 + bit_size: 1 + description: External Event 7 + enum: RSTAR_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 16 + bit_size: 1 + description: External Event 8 + enum: RSTAR_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 17 + bit_size: 1 + description: External Event 9 + enum: RSTAR_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 18 + bit_size: 1 + description: External Event 10 + enum: RSTAR_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 19 + bit_size: 1 + description: Timer B Compare 1 + enum: TIMBCMP1 + name: TIMBCMP1 + - bit_offset: 20 + bit_size: 1 + description: Timer B Compare 2 + enum: TIMBCMP1 + name: TIMBCMP2 + - bit_offset: 21 + bit_size: 1 + description: Timer B Compare 4 + enum: TIMBCMP1 + name: TIMBCMP4 + - bit_offset: 22 + bit_size: 1 + description: Timer C Compare 1 + enum: TIMBCMP1 + name: TIMCCMP1 + - bit_offset: 23 + bit_size: 1 + description: Timer C Compare 2 + enum: TIMBCMP1 + name: TIMCCMP2 + - bit_offset: 24 + bit_size: 1 + description: Timer C Compare 4 + enum: TIMBCMP1 + name: TIMCCMP4 + - bit_offset: 25 + bit_size: 1 + description: Timer D Compare 1 + enum: TIMBCMP1 + name: TIMDCMP1 + - bit_offset: 26 + bit_size: 1 + description: Timer D Compare 2 + enum: TIMBCMP1 + name: TIMDCMP2 + - bit_offset: 27 + bit_size: 1 + description: Timer D Compare 4 + enum: TIMBCMP1 + name: TIMDCMP4 + - bit_offset: 28 + bit_size: 1 + description: Timer E Compare 1 + enum: TIMBCMP1 + name: TIMECMP1 + - bit_offset: 29 + bit_size: 1 + description: Timer E Compare 2 + enum: TIMBCMP1 + name: TIMECMP2 + - bit_offset: 30 + bit_size: 1 + description: Timer E Compare 4 + enum: TIMBCMP1 + name: TIMECMP4 +fieldset/RSTB1R: + description: Timerx Output1 Reset Register + fields: + - bit_offset: 0 + bit_size: 1 + description: SRT + enum: RSTB1R_SRT + name: SRT + - bit_offset: 1 + bit_size: 1 + description: RESYNC + enum: RSTB1R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: PER + enum: RSTB1R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: CMP1 + enum: RSTB1R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: CMP2 + enum: RSTB1R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: CMP3 + enum: RSTB1R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: CMP4 + enum: RSTB1R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: MSTPER + enum: RSTB1R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: MSTCMP1 + enum: RSTB1R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: MSTCMP2 + enum: RSTB1R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: MSTCMP3 + enum: RSTB1R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: MSTCMP4 + enum: RSTB1R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: TIMEVNT1 + enum: RSTB1R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: TIMEVNT2 + enum: RSTB1R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: TIMEVNT3 + enum: RSTB1R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: TIMEVNT4 + enum: RSTB1R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: TIMEVNT5 + enum: RSTB1R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: TIMEVNT6 + enum: RSTB1R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: TIMEVNT7 + enum: RSTB1R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: TIMEVNT8 + enum: RSTB1R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: TIMEVNT9 + enum: RSTB1R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: EXTEVNT1 + enum: RSTB1R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: EXTEVNT2 + enum: RSTB1R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: EXTEVNT3 + enum: RSTB1R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: EXTEVNT4 + enum: RSTB1R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: EXTEVNT5 + enum: RSTB1R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: EXTEVNT6 + enum: RSTB1R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: EXTEVNT7 + enum: RSTB1R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: EXTEVNT8 + enum: RSTB1R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: EXTEVNT9 + enum: RSTB1R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: EXTEVNT10 + enum: RSTB1R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: UPDATE + enum: RSTB1R_UPDATE + name: UPDATE +fieldset/RSTB2R: + description: Timerx Output2 Reset Register + fields: + - bit_offset: 0 + bit_size: 1 + description: SRT + enum: RSTB2R_SRT + name: SRT + - bit_offset: 1 + bit_size: 1 + description: RESYNC + enum: RSTB2R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: PER + enum: RSTB2R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: CMP1 + enum: RSTB2R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: CMP2 + enum: RSTB2R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: CMP3 + enum: RSTB2R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: CMP4 + enum: RSTB2R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: MSTPER + enum: RSTB2R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: MSTCMP1 + enum: RSTB2R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: MSTCMP2 + enum: RSTB2R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: MSTCMP3 + enum: RSTB2R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: MSTCMP4 + enum: RSTB2R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: TIMEVNT1 + enum: RSTB2R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: TIMEVNT2 + enum: RSTB2R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: TIMEVNT3 + enum: RSTB2R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: TIMEVNT4 + enum: RSTB2R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: TIMEVNT5 + enum: RSTB2R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: TIMEVNT6 + enum: RSTB2R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: TIMEVNT7 + enum: RSTB2R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: TIMEVNT8 + enum: RSTB2R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: TIMEVNT9 + enum: RSTB2R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: EXTEVNT1 + enum: RSTB2R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: EXTEVNT2 + enum: RSTB2R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: EXTEVNT3 + enum: RSTB2R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: EXTEVNT4 + enum: RSTB2R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: EXTEVNT5 + enum: RSTB2R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: EXTEVNT6 + enum: RSTB2R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: EXTEVNT7 + enum: RSTB2R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: EXTEVNT8 + enum: RSTB2R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: EXTEVNT9 + enum: RSTB2R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: EXTEVNT10 + enum: RSTB2R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: UPDATE + enum: RSTB2R_UPDATE + name: UPDATE +fieldset/RSTBR: + description: TimerA Reset Register + fields: + - bit_offset: 1 + bit_size: 1 + description: Timer A Update reset + enum: UPDT + name: UPDT + - bit_offset: 2 + bit_size: 1 + description: Timer A compare 2 reset + enum: CMP2 + name: CMP2 + - bit_offset: 3 + bit_size: 1 + description: Timer A compare 4 reset + enum: CMP2 + name: CMP4 + - bit_offset: 4 + bit_size: 1 + description: Master timer Period + enum: RSTBR_MSTPER + name: MSTPER + - bit_offset: 5 + bit_size: 1 + description: Master compare 1 + enum: RSTBR_MSTCMP1 + name: MSTCMP1 + - bit_offset: 6 + bit_size: 1 + description: Master compare 2 + enum: RSTBR_MSTCMP1 + name: MSTCMP2 + - bit_offset: 7 + bit_size: 1 + description: Master compare 3 + enum: RSTBR_MSTCMP1 + name: MSTCMP3 + - bit_offset: 8 + bit_size: 1 + description: Master compare 4 + enum: RSTBR_MSTCMP1 + name: MSTCMP4 + - bit_offset: 9 + bit_size: 1 + description: External Event 1 + enum: RSTBR_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 10 + bit_size: 1 + description: External Event 2 + enum: RSTBR_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 11 + bit_size: 1 + description: External Event 3 + enum: RSTBR_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 12 + bit_size: 1 + description: External Event 4 + enum: RSTBR_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 13 + bit_size: 1 + description: External Event 5 + enum: RSTBR_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 14 + bit_size: 1 + description: External Event 6 + enum: RSTBR_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 15 + bit_size: 1 + description: External Event 7 + enum: RSTBR_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 16 + bit_size: 1 + description: External Event 8 + enum: RSTBR_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 17 + bit_size: 1 + description: External Event 9 + enum: RSTBR_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 18 + bit_size: 1 + description: External Event 10 + enum: RSTBR_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 19 + bit_size: 1 + description: Timer A Compare 1 + enum: TIMACMP1 + name: TIMACMP1 + - bit_offset: 20 + bit_size: 1 + description: Timer A Compare 2 + enum: TIMACMP1 + name: TIMACMP2 + - bit_offset: 21 + bit_size: 1 + description: Timer A Compare 4 + enum: TIMACMP1 + name: TIMACMP4 + - bit_offset: 22 + bit_size: 1 + description: Timer C Compare 1 + enum: TIMACMP1 + name: TIMCCMP1 + - bit_offset: 23 + bit_size: 1 + description: Timer C Compare 2 + enum: TIMACMP1 + name: TIMCCMP2 + - bit_offset: 24 + bit_size: 1 + description: Timer C Compare 4 + enum: TIMACMP1 + name: TIMCCMP4 + - bit_offset: 25 + bit_size: 1 + description: Timer D Compare 1 + enum: TIMACMP1 + name: TIMDCMP1 + - bit_offset: 26 + bit_size: 1 + description: Timer D Compare 2 + enum: TIMACMP1 + name: TIMDCMP2 + - bit_offset: 27 + bit_size: 1 + description: Timer D Compare 4 + enum: TIMACMP1 + name: TIMDCMP4 + - bit_offset: 28 + bit_size: 1 + description: Timer E Compare 1 + enum: TIMACMP1 + name: TIMECMP1 + - bit_offset: 29 + bit_size: 1 + description: Timer E Compare 2 + enum: TIMACMP1 + name: TIMECMP2 + - bit_offset: 30 + bit_size: 1 + description: Timer E Compare 4 + enum: TIMACMP1 + name: TIMECMP4 +fieldset/RSTC1R: + description: Timerx Output1 Reset Register + fields: + - bit_offset: 0 + bit_size: 1 + description: SRT + enum: RSTC1R_SRT + name: SRT + - bit_offset: 1 + bit_size: 1 + description: RESYNC + enum: RSTC1R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: PER + enum: RSTC1R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: CMP1 + enum: RSTC1R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: CMP2 + enum: RSTC1R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: CMP3 + enum: RSTC1R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: CMP4 + enum: RSTC1R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: MSTPER + enum: RSTC1R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: MSTCMP1 + enum: RSTC1R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: MSTCMP2 + enum: RSTC1R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: MSTCMP3 + enum: RSTC1R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: MSTCMP4 + enum: RSTC1R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: TIMEVNT1 + enum: RSTC1R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: TIMEVNT2 + enum: RSTC1R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: TIMEVNT3 + enum: RSTC1R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: TIMEVNT4 + enum: RSTC1R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: TIMEVNT5 + enum: RSTC1R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: TIMEVNT6 + enum: RSTC1R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: TIMEVNT7 + enum: RSTC1R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: TIMEVNT8 + enum: RSTC1R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: TIMEVNT9 + enum: RSTC1R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: EXTEVNT1 + enum: RSTC1R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: EXTEVNT2 + enum: RSTC1R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: EXTEVNT3 + enum: RSTC1R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: EXTEVNT4 + enum: RSTC1R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: EXTEVNT5 + enum: RSTC1R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: EXTEVNT6 + enum: RSTC1R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: EXTEVNT7 + enum: RSTC1R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: EXTEVNT8 + enum: RSTC1R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: EXTEVNT9 + enum: RSTC1R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: EXTEVNT10 + enum: RSTC1R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: UPDATE + enum: RSTC1R_UPDATE + name: UPDATE +fieldset/RSTC2R: + description: Timerx Output2 Reset Register + fields: + - bit_offset: 0 + bit_size: 1 + description: SRT + enum: RSTC2R_SRT + name: SRT + - bit_offset: 1 + bit_size: 1 + description: RESYNC + enum: RSTC2R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: PER + enum: RSTC2R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: CMP1 + enum: RSTC2R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: CMP2 + enum: RSTC2R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: CMP3 + enum: RSTC2R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: CMP4 + enum: RSTC2R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: MSTPER + enum: RSTC2R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: MSTCMP1 + enum: RSTC2R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: MSTCMP2 + enum: RSTC2R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: MSTCMP3 + enum: RSTC2R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: MSTCMP4 + enum: RSTC2R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: TIMEVNT1 + enum: RSTC2R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: TIMEVNT2 + enum: RSTC2R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: TIMEVNT3 + enum: RSTC2R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: TIMEVNT4 + enum: RSTC2R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: TIMEVNT5 + enum: RSTC2R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: TIMEVNT6 + enum: RSTC2R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: TIMEVNT7 + enum: RSTC2R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: TIMEVNT8 + enum: RSTC2R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: TIMEVNT9 + enum: RSTC2R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: EXTEVNT1 + enum: RSTC2R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: EXTEVNT2 + enum: RSTC2R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: EXTEVNT3 + enum: RSTC2R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: EXTEVNT4 + enum: RSTC2R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: EXTEVNT5 + enum: RSTC2R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: EXTEVNT6 + enum: RSTC2R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: EXTEVNT7 + enum: RSTC2R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: EXTEVNT8 + enum: RSTC2R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: EXTEVNT9 + enum: RSTC2R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: EXTEVNT10 + enum: RSTC2R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: UPDATE + enum: RSTC2R_UPDATE + name: UPDATE +fieldset/RSTCR: + description: TimerA Reset Register + fields: + - bit_offset: 1 + bit_size: 1 + description: Timer A Update reset + enum: UPDT + name: UPDT + - bit_offset: 2 + bit_size: 1 + description: Timer A compare 2 reset + enum: CMP2 + name: CMP2 + - bit_offset: 3 + bit_size: 1 + description: Timer A compare 4 reset + enum: CMP2 + name: CMP4 + - bit_offset: 4 + bit_size: 1 + description: Master timer Period + enum: RSTCR_MSTPER + name: MSTPER + - bit_offset: 5 + bit_size: 1 + description: Master compare 1 + enum: RSTCR_MSTCMP1 + name: MSTCMP1 + - bit_offset: 6 + bit_size: 1 + description: Master compare 2 + enum: RSTCR_MSTCMP1 + name: MSTCMP2 + - bit_offset: 7 + bit_size: 1 + description: Master compare 3 + enum: RSTCR_MSTCMP1 + name: MSTCMP3 + - bit_offset: 8 + bit_size: 1 + description: Master compare 4 + enum: RSTCR_MSTCMP1 + name: MSTCMP4 + - bit_offset: 9 + bit_size: 1 + description: External Event 1 + enum: RSTCR_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 10 + bit_size: 1 + description: External Event 2 + enum: RSTCR_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 11 + bit_size: 1 + description: External Event 3 + enum: RSTCR_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 12 + bit_size: 1 + description: External Event 4 + enum: RSTCR_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 13 + bit_size: 1 + description: External Event 5 + enum: RSTCR_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 14 + bit_size: 1 + description: External Event 6 + enum: RSTCR_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 15 + bit_size: 1 + description: External Event 7 + enum: RSTCR_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 16 + bit_size: 1 + description: External Event 8 + enum: RSTCR_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 17 + bit_size: 1 + description: External Event 9 + enum: RSTCR_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 18 + bit_size: 1 + description: External Event 10 + enum: RSTCR_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 19 + bit_size: 1 + description: Timer A Compare 1 + enum: TIMACMP1 + name: TIMACMP1 + - bit_offset: 20 + bit_size: 1 + description: Timer A Compare 2 + enum: TIMACMP1 + name: TIMACMP2 + - bit_offset: 21 + bit_size: 1 + description: Timer A Compare 4 + enum: TIMACMP1 + name: TIMACMP4 + - bit_offset: 22 + bit_size: 1 + description: Timer B Compare 1 + enum: TIMACMP1 + name: TIMBCMP1 + - bit_offset: 23 + bit_size: 1 + description: Timer B Compare 2 + enum: TIMACMP1 + name: TIMBCMP2 + - bit_offset: 24 + bit_size: 1 + description: Timer B Compare 4 + enum: TIMACMP1 + name: TIMBCMP4 + - bit_offset: 25 + bit_size: 1 + description: Timer D Compare 1 + enum: TIMACMP1 + name: TIMDCMP1 + - bit_offset: 26 + bit_size: 1 + description: Timer D Compare 2 + enum: TIMACMP1 + name: TIMDCMP2 + - bit_offset: 27 + bit_size: 1 + description: Timer D Compare 4 + enum: TIMACMP1 + name: TIMDCMP4 + - bit_offset: 28 + bit_size: 1 + description: Timer E Compare 1 + enum: TIMACMP1 + name: TIMECMP1 + - bit_offset: 29 + bit_size: 1 + description: Timer E Compare 2 + enum: TIMACMP1 + name: TIMECMP2 + - bit_offset: 30 + bit_size: 1 + description: Timer E Compare 4 + enum: TIMACMP1 + name: TIMECMP4 +fieldset/RSTD1R: + description: Timerx Output1 Reset Register + fields: + - bit_offset: 0 + bit_size: 1 + description: SRT + enum: RSTD1R_SRT + name: SRT + - bit_offset: 1 + bit_size: 1 + description: RESYNC + enum: RSTD1R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: PER + enum: RSTD1R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: CMP1 + enum: RSTD1R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: CMP2 + enum: RSTD1R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: CMP3 + enum: RSTD1R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: CMP4 + enum: RSTD1R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: MSTPER + enum: RSTD1R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: MSTCMP1 + enum: RSTD1R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: MSTCMP2 + enum: RSTD1R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: MSTCMP3 + enum: RSTD1R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: MSTCMP4 + enum: RSTD1R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: TIMEVNT1 + enum: RSTD1R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: TIMEVNT2 + enum: RSTD1R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: TIMEVNT3 + enum: RSTD1R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: TIMEVNT4 + enum: RSTD1R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: TIMEVNT5 + enum: RSTD1R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: TIMEVNT6 + enum: RSTD1R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: TIMEVNT7 + enum: RSTD1R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: TIMEVNT8 + enum: RSTD1R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: TIMEVNT9 + enum: RSTD1R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: EXTEVNT1 + enum: RSTD1R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: EXTEVNT2 + enum: RSTD1R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: EXTEVNT3 + enum: RSTD1R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: EXTEVNT4 + enum: RSTD1R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: EXTEVNT5 + enum: RSTD1R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: EXTEVNT6 + enum: RSTD1R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: EXTEVNT7 + enum: RSTD1R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: EXTEVNT8 + enum: RSTD1R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: EXTEVNT9 + enum: RSTD1R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: EXTEVNT10 + enum: RSTD1R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: UPDATE + enum: RSTD1R_UPDATE + name: UPDATE +fieldset/RSTD2R: + description: Timerx Output2 Reset Register + fields: + - bit_offset: 0 + bit_size: 1 + description: SRT + enum: RSTD2R_SRT + name: SRT + - bit_offset: 1 + bit_size: 1 + description: RESYNC + enum: RSTD2R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: PER + enum: RSTD2R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: CMP1 + enum: RSTD2R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: CMP2 + enum: RSTD2R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: CMP3 + enum: RSTD2R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: CMP4 + enum: RSTD2R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: MSTPER + enum: RSTD2R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: MSTCMP1 + enum: RSTD2R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: MSTCMP2 + enum: RSTD2R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: MSTCMP3 + enum: RSTD2R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: MSTCMP4 + enum: RSTD2R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: TIMEVNT1 + enum: RSTD2R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: TIMEVNT2 + enum: RSTD2R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: TIMEVNT3 + enum: RSTD2R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: TIMEVNT4 + enum: RSTD2R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: TIMEVNT5 + enum: RSTD2R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: TIMEVNT6 + enum: RSTD2R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: TIMEVNT7 + enum: RSTD2R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: TIMEVNT8 + enum: RSTD2R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: TIMEVNT9 + enum: RSTD2R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: EXTEVNT1 + enum: RSTD2R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: EXTEVNT2 + enum: RSTD2R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: EXTEVNT3 + enum: RSTD2R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: EXTEVNT4 + enum: RSTD2R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: EXTEVNT5 + enum: RSTD2R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: EXTEVNT6 + enum: RSTD2R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: EXTEVNT7 + enum: RSTD2R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: EXTEVNT8 + enum: RSTD2R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: EXTEVNT9 + enum: RSTD2R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: EXTEVNT10 + enum: RSTD2R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: UPDATE + enum: RSTD2R_UPDATE + name: UPDATE +fieldset/RSTDR: + description: TimerA Reset Register + fields: + - bit_offset: 1 + bit_size: 1 + description: Timer A Update reset + enum: UPDT + name: UPDT + - bit_offset: 2 + bit_size: 1 + description: Timer A compare 2 reset + enum: CMP2 + name: CMP2 + - bit_offset: 3 + bit_size: 1 + description: Timer A compare 4 reset + enum: CMP2 + name: CMP4 + - bit_offset: 4 + bit_size: 1 + description: Master timer Period + enum: RSTDR_MSTPER + name: MSTPER + - bit_offset: 5 + bit_size: 1 + description: Master compare 1 + enum: RSTDR_MSTCMP1 + name: MSTCMP1 + - bit_offset: 6 + bit_size: 1 + description: Master compare 2 + enum: RSTDR_MSTCMP1 + name: MSTCMP2 + - bit_offset: 7 + bit_size: 1 + description: Master compare 3 + enum: RSTDR_MSTCMP1 + name: MSTCMP3 + - bit_offset: 8 + bit_size: 1 + description: Master compare 4 + enum: RSTDR_MSTCMP1 + name: MSTCMP4 + - bit_offset: 9 + bit_size: 1 + description: External Event 1 + enum: RSTDR_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 10 + bit_size: 1 + description: External Event 2 + enum: RSTDR_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 11 + bit_size: 1 + description: External Event 3 + enum: RSTDR_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 12 + bit_size: 1 + description: External Event 4 + enum: RSTDR_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 13 + bit_size: 1 + description: External Event 5 + enum: RSTDR_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 14 + bit_size: 1 + description: External Event 6 + enum: RSTDR_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 15 + bit_size: 1 + description: External Event 7 + enum: RSTDR_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 16 + bit_size: 1 + description: External Event 8 + enum: RSTDR_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 17 + bit_size: 1 + description: External Event 9 + enum: RSTDR_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 18 + bit_size: 1 + description: External Event 10 + enum: RSTDR_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 19 + bit_size: 1 + description: Timer A Compare 1 + enum: TIMACMP1 + name: TIMACMP1 + - bit_offset: 20 + bit_size: 1 + description: Timer A Compare 2 + enum: TIMACMP1 + name: TIMACMP2 + - bit_offset: 21 + bit_size: 1 + description: Timer A Compare 4 + enum: TIMACMP1 + name: TIMACMP4 + - bit_offset: 22 + bit_size: 1 + description: Timer B Compare 1 + enum: TIMACMP1 + name: TIMBCMP1 + - bit_offset: 23 + bit_size: 1 + description: Timer B Compare 2 + enum: TIMACMP1 + name: TIMBCMP2 + - bit_offset: 24 + bit_size: 1 + description: Timer B Compare 4 + enum: TIMACMP1 + name: TIMBCMP4 + - bit_offset: 25 + bit_size: 1 + description: Timer C Compare 1 + enum: TIMACMP1 + name: TIMCCMP1 + - bit_offset: 26 + bit_size: 1 + description: Timer C Compare 2 + enum: TIMACMP1 + name: TIMCCMP2 + - bit_offset: 27 + bit_size: 1 + description: Timer C Compare 4 + enum: TIMACMP1 + name: TIMCCMP4 + - bit_offset: 28 + bit_size: 1 + description: Timer E Compare 1 + enum: TIMACMP1 + name: TIMECMP1 + - bit_offset: 29 + bit_size: 1 + description: Timer E Compare 2 + enum: TIMACMP1 + name: TIMECMP2 + - bit_offset: 30 + bit_size: 1 + description: Timer E Compare 4 + enum: TIMACMP1 + name: TIMECMP4 +fieldset/RSTE1R: + description: Timerx Output1 Reset Register + fields: + - bit_offset: 0 + bit_size: 1 + description: SRT + enum: RSTE1R_SRT + name: SRT + - bit_offset: 1 + bit_size: 1 + description: RESYNC + enum: RSTE1R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: PER + enum: RSTE1R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: CMP1 + enum: RSTE1R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: CMP2 + enum: RSTE1R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: CMP3 + enum: RSTE1R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: CMP4 + enum: RSTE1R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: MSTPER + enum: RSTE1R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: MSTCMP1 + enum: RSTE1R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: MSTCMP2 + enum: RSTE1R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: MSTCMP3 + enum: RSTE1R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: MSTCMP4 + enum: RSTE1R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: TIMEVNT1 + enum: RSTE1R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: TIMEVNT2 + enum: RSTE1R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: TIMEVNT3 + enum: RSTE1R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: TIMEVNT4 + enum: RSTE1R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: TIMEVNT5 + enum: RSTE1R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: TIMEVNT6 + enum: RSTE1R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: TIMEVNT7 + enum: RSTE1R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: TIMEVNT8 + enum: RSTE1R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: TIMEVNT9 + enum: RSTE1R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: EXTEVNT1 + enum: RSTE1R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: EXTEVNT2 + enum: RSTE1R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: EXTEVNT3 + enum: RSTE1R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: EXTEVNT4 + enum: RSTE1R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: EXTEVNT5 + enum: RSTE1R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: EXTEVNT6 + enum: RSTE1R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: EXTEVNT7 + enum: RSTE1R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: EXTEVNT8 + enum: RSTE1R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: EXTEVNT9 + enum: RSTE1R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: EXTEVNT10 + enum: RSTE1R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: UPDATE + enum: RSTE1R_UPDATE + name: UPDATE +fieldset/RSTE2R: + description: Timerx Output2 Reset Register + fields: + - bit_offset: 0 + bit_size: 1 + description: SRT + enum: RSTE2R_SRT + name: SRT + - bit_offset: 1 + bit_size: 1 + description: RESYNC + enum: RSTE2R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: PER + enum: RSTE2R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: CMP1 + enum: RSTE2R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: CMP2 + enum: RSTE2R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: CMP3 + enum: RSTE2R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: CMP4 + enum: RSTE2R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: MSTPER + enum: RSTE2R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: MSTCMP1 + enum: RSTE2R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: MSTCMP2 + enum: RSTE2R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: MSTCMP3 + enum: RSTE2R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: MSTCMP4 + enum: RSTE2R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: TIMEVNT1 + enum: RSTE2R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: TIMEVNT2 + enum: RSTE2R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: TIMEVNT3 + enum: RSTE2R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: TIMEVNT4 + enum: RSTE2R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: TIMEVNT5 + enum: RSTE2R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: TIMEVNT6 + enum: RSTE2R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: TIMEVNT7 + enum: RSTE2R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: TIMEVNT8 + enum: RSTE2R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: TIMEVNT9 + enum: RSTE2R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: EXTEVNT1 + enum: RSTE2R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: EXTEVNT2 + enum: RSTE2R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: EXTEVNT3 + enum: RSTE2R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: EXTEVNT4 + enum: RSTE2R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: EXTEVNT5 + enum: RSTE2R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: EXTEVNT6 + enum: RSTE2R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: EXTEVNT7 + enum: RSTE2R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: EXTEVNT8 + enum: RSTE2R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: EXTEVNT9 + enum: RSTE2R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: EXTEVNT10 + enum: RSTE2R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: UPDATE + enum: RSTE2R_UPDATE + name: UPDATE +fieldset/RSTER: + description: TimerA Reset Register + fields: + - bit_offset: 1 + bit_size: 1 + description: Timer A Update reset + enum: UPDT + name: UPDT + - bit_offset: 2 + bit_size: 1 + description: Timer A compare 2 reset + enum: CMP2 + name: CMP2 + - bit_offset: 3 + bit_size: 1 + description: Timer A compare 4 reset + enum: CMP2 + name: CMP4 + - bit_offset: 4 + bit_size: 1 + description: Master timer Period + enum: RSTER_MSTPER + name: MSTPER + - bit_offset: 5 + bit_size: 1 + description: Master compare 1 + enum: RSTER_MSTCMP1 + name: MSTCMP1 + - bit_offset: 6 + bit_size: 1 + description: Master compare 2 + enum: RSTER_MSTCMP1 + name: MSTCMP2 + - bit_offset: 7 + bit_size: 1 + description: Master compare 3 + enum: RSTER_MSTCMP1 + name: MSTCMP3 + - bit_offset: 8 + bit_size: 1 + description: Master compare 4 + enum: RSTER_MSTCMP1 + name: MSTCMP4 + - bit_offset: 9 + bit_size: 1 + description: External Event 1 + enum: RSTER_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 10 + bit_size: 1 + description: External Event 2 + enum: RSTER_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 11 + bit_size: 1 + description: External Event 3 + enum: RSTER_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 12 + bit_size: 1 + description: External Event 4 + enum: RSTER_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 13 + bit_size: 1 + description: External Event 5 + enum: RSTER_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 14 + bit_size: 1 + description: External Event 6 + enum: RSTER_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 15 + bit_size: 1 + description: External Event 7 + enum: RSTER_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 16 + bit_size: 1 + description: External Event 8 + enum: RSTER_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 17 + bit_size: 1 + description: External Event 9 + enum: RSTER_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 18 + bit_size: 1 + description: External Event 10 + enum: RSTER_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 19 + bit_size: 1 + description: Timer A Compare 1 + enum: TIMACMP1 + name: TIMACMP1 + - bit_offset: 20 + bit_size: 1 + description: Timer A Compare 2 + enum: TIMACMP1 + name: TIMACMP2 + - bit_offset: 21 + bit_size: 1 + description: Timer A Compare 4 + enum: TIMACMP1 + name: TIMACMP4 + - bit_offset: 22 + bit_size: 1 + description: Timer B Compare 1 + enum: TIMACMP1 + name: TIMBCMP1 + - bit_offset: 23 + bit_size: 1 + description: Timer B Compare 2 + enum: TIMACMP1 + name: TIMBCMP2 + - bit_offset: 24 + bit_size: 1 + description: Timer B Compare 4 + enum: TIMACMP1 + name: TIMBCMP4 + - bit_offset: 25 + bit_size: 1 + description: Timer C Compare 1 + enum: TIMACMP1 + name: TIMCCMP1 + - bit_offset: 26 + bit_size: 1 + description: Timer C Compare 2 + enum: TIMACMP1 + name: TIMCCMP2 + - bit_offset: 27 + bit_size: 1 + description: Timer C Compare 4 + enum: TIMACMP1 + name: TIMCCMP4 + - bit_offset: 28 + bit_size: 1 + description: Timer D Compare 1 + enum: TIMACMP1 + name: TIMDCMP1 + - bit_offset: 29 + bit_size: 1 + description: Timer D Compare 2 + enum: TIMACMP1 + name: TIMDCMP2 + - bit_offset: 30 + bit_size: 1 + description: Timer D Compare 4 + enum: TIMACMP1 + name: TIMDCMP4 +fieldset/SETA1R: + description: Timerx Output1 Set Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Software Set trigger + enum: SETA1R_SST + name: SST + - bit_offset: 1 + bit_size: 1 + description: Timer A resynchronizaton + enum: SETA1R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: Timer A Period + enum: SETA1R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: Timer A compare 1 + enum: SETA1R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: Timer A compare 2 + enum: SETA1R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: Timer A compare 3 + enum: SETA1R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: Timer A compare 4 + enum: SETA1R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: Master Period + enum: SETA1R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: Master Compare 1 + enum: SETA1R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: Master Compare 2 + enum: SETA1R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: Master Compare 3 + enum: SETA1R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: Master Compare 4 + enum: SETA1R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: Timer Event 1 + enum: SETA1R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: Timer Event 2 + enum: SETA1R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: Timer Event 3 + enum: SETA1R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: Timer Event 4 + enum: SETA1R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: Timer Event 5 + enum: SETA1R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: Timer Event 6 + enum: SETA1R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: Timer Event 7 + enum: SETA1R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: Timer Event 8 + enum: SETA1R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: Timer Event 9 + enum: SETA1R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: External Event 1 + enum: SETA1R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: External Event 2 + enum: SETA1R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: External Event 3 + enum: SETA1R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: External Event 4 + enum: SETA1R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: External Event 5 + enum: SETA1R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: External Event 6 + enum: SETA1R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: External Event 7 + enum: SETA1R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: External Event 8 + enum: SETA1R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: External Event 9 + enum: SETA1R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: External Event 10 + enum: SETA1R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: "Registers update (transfer preload to\r active)" + enum: SETA1R_UPDATE + name: UPDATE +fieldset/SETA2R: + description: Timerx Output2 Set Register + fields: + - bit_offset: 0 + bit_size: 1 + description: SST + enum: SETA2R_SST + name: SST + - bit_offset: 1 + bit_size: 1 + description: RESYNC + enum: SETA2R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: PER + enum: SETA2R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: CMP1 + enum: SETA2R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: CMP2 + enum: SETA2R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: CMP3 + enum: SETA2R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: CMP4 + enum: SETA2R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: MSTPER + enum: SETA2R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: MSTCMP1 + enum: SETA2R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: MSTCMP2 + enum: SETA2R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: MSTCMP3 + enum: SETA2R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: MSTCMP4 + enum: SETA2R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: TIMEVNT1 + enum: SETA2R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: TIMEVNT2 + enum: SETA2R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: TIMEVNT3 + enum: SETA2R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: TIMEVNT4 + enum: SETA2R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: TIMEVNT5 + enum: SETA2R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: TIMEVNT6 + enum: SETA2R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: TIMEVNT7 + enum: SETA2R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: TIMEVNT8 + enum: SETA2R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: TIMEVNT9 + enum: SETA2R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: EXTEVNT1 + enum: SETA2R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: EXTEVNT2 + enum: SETA2R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: EXTEVNT3 + enum: SETA2R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: EXTEVNT4 + enum: SETA2R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: EXTEVNT5 + enum: SETA2R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: EXTEVNT6 + enum: SETA2R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: EXTEVNT7 + enum: SETA2R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: EXTEVNT8 + enum: SETA2R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: EXTEVNT9 + enum: SETA2R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: EXTEVNT10 + enum: SETA2R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: UPDATE + enum: SETA2R_UPDATE + name: UPDATE +fieldset/SETB1R: + description: Timerx Output1 Set Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Software Set trigger + enum: SETB1R_SST + name: SST + - bit_offset: 1 + bit_size: 1 + description: Timer A resynchronizaton + enum: SETB1R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: Timer A Period + enum: SETB1R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: Timer A compare 1 + enum: SETB1R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: Timer A compare 2 + enum: SETB1R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: Timer A compare 3 + enum: SETB1R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: Timer A compare 4 + enum: SETB1R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: Master Period + enum: SETB1R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: Master Compare 1 + enum: SETB1R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: Master Compare 2 + enum: SETB1R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: Master Compare 3 + enum: SETB1R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: Master Compare 4 + enum: SETB1R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: Timer Event 1 + enum: SETB1R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: Timer Event 2 + enum: SETB1R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: Timer Event 3 + enum: SETB1R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: Timer Event 4 + enum: SETB1R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: Timer Event 5 + enum: SETB1R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: Timer Event 6 + enum: SETB1R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: Timer Event 7 + enum: SETB1R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: Timer Event 8 + enum: SETB1R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: Timer Event 9 + enum: SETB1R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: External Event 1 + enum: SETB1R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: External Event 2 + enum: SETB1R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: External Event 3 + enum: SETB1R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: External Event 4 + enum: SETB1R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: External Event 5 + enum: SETB1R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: External Event 6 + enum: SETB1R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: External Event 7 + enum: SETB1R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: External Event 8 + enum: SETB1R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: External Event 9 + enum: SETB1R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: External Event 10 + enum: SETB1R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: "Registers update (transfer preload to\r active)" + enum: SETB1R_UPDATE + name: UPDATE +fieldset/SETB2R: + description: Timerx Output2 Set Register + fields: + - bit_offset: 0 + bit_size: 1 + description: SST + enum: SETB2R_SST + name: SST + - bit_offset: 1 + bit_size: 1 + description: RESYNC + enum: SETB2R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: PER + enum: SETB2R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: CMP1 + enum: SETB2R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: CMP2 + enum: SETB2R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: CMP3 + enum: SETB2R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: CMP4 + enum: SETB2R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: MSTPER + enum: SETB2R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: MSTCMP1 + enum: SETB2R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: MSTCMP2 + enum: SETB2R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: MSTCMP3 + enum: SETB2R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: MSTCMP4 + enum: SETB2R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: TIMEVNT1 + enum: SETB2R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: TIMEVNT2 + enum: SETB2R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: TIMEVNT3 + enum: SETB2R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: TIMEVNT4 + enum: SETB2R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: TIMEVNT5 + enum: SETB2R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: TIMEVNT6 + enum: SETB2R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: TIMEVNT7 + enum: SETB2R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: TIMEVNT8 + enum: SETB2R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: TIMEVNT9 + enum: SETB2R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: EXTEVNT1 + enum: SETB2R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: EXTEVNT2 + enum: SETB2R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: EXTEVNT3 + enum: SETB2R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: EXTEVNT4 + enum: SETB2R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: EXTEVNT5 + enum: SETB2R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: EXTEVNT6 + enum: SETB2R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: EXTEVNT7 + enum: SETB2R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: EXTEVNT8 + enum: SETB2R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: EXTEVNT9 + enum: SETB2R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: EXTEVNT10 + enum: SETB2R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: UPDATE + enum: SETB2R_UPDATE + name: UPDATE +fieldset/SETC1R: + description: Timerx Output1 Set Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Software Set trigger + enum: SETC1R_SST + name: SST + - bit_offset: 1 + bit_size: 1 + description: Timer A resynchronizaton + enum: SETC1R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: Timer A Period + enum: SETC1R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: Timer A compare 1 + enum: SETC1R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: Timer A compare 2 + enum: SETC1R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: Timer A compare 3 + enum: SETC1R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: Timer A compare 4 + enum: SETC1R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: Master Period + enum: SETC1R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: Master Compare 1 + enum: SETC1R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: Master Compare 2 + enum: SETC1R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: Master Compare 3 + enum: SETC1R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: Master Compare 4 + enum: SETC1R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: Timer Event 1 + enum: SETC1R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: Timer Event 2 + enum: SETC1R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: Timer Event 3 + enum: SETC1R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: Timer Event 4 + enum: SETC1R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: Timer Event 5 + enum: SETC1R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: Timer Event 6 + enum: SETC1R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: Timer Event 7 + enum: SETC1R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: Timer Event 8 + enum: SETC1R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: Timer Event 9 + enum: SETC1R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: External Event 1 + enum: SETC1R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: External Event 2 + enum: SETC1R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: External Event 3 + enum: SETC1R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: External Event 4 + enum: SETC1R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: External Event 5 + enum: SETC1R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: External Event 6 + enum: SETC1R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: External Event 7 + enum: SETC1R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: External Event 8 + enum: SETC1R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: External Event 9 + enum: SETC1R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: External Event 10 + enum: SETC1R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: "Registers update (transfer preload to\r active)" + enum: SETC1R_UPDATE + name: UPDATE +fieldset/SETC2R: + description: Timerx Output2 Set Register + fields: + - bit_offset: 0 + bit_size: 1 + description: SST + enum: SETC2R_SST + name: SST + - bit_offset: 1 + bit_size: 1 + description: RESYNC + enum: SETC2R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: PER + enum: SETC2R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: CMP1 + enum: SETC2R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: CMP2 + enum: SETC2R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: CMP3 + enum: SETC2R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: CMP4 + enum: SETC2R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: MSTPER + enum: SETC2R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: MSTCMP1 + enum: SETC2R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: MSTCMP2 + enum: SETC2R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: MSTCMP3 + enum: SETC2R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: MSTCMP4 + enum: SETC2R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: TIMEVNT1 + enum: SETC2R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: TIMEVNT2 + enum: SETC2R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: TIMEVNT3 + enum: SETC2R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: TIMEVNT4 + enum: SETC2R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: TIMEVNT5 + enum: SETC2R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: TIMEVNT6 + enum: SETC2R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: TIMEVNT7 + enum: SETC2R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: TIMEVNT8 + enum: SETC2R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: TIMEVNT9 + enum: SETC2R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: EXTEVNT1 + enum: SETC2R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: EXTEVNT2 + enum: SETC2R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: EXTEVNT3 + enum: SETC2R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: EXTEVNT4 + enum: SETC2R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: EXTEVNT5 + enum: SETC2R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: EXTEVNT6 + enum: SETC2R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: EXTEVNT7 + enum: SETC2R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: EXTEVNT8 + enum: SETC2R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: EXTEVNT9 + enum: SETC2R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: EXTEVNT10 + enum: SETC2R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: UPDATE + enum: SETC2R_UPDATE + name: UPDATE +fieldset/SETD1R: + description: Timerx Output1 Set Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Software Set trigger + enum: SETD1R_SST + name: SST + - bit_offset: 1 + bit_size: 1 + description: Timer A resynchronizaton + enum: SETD1R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: Timer A Period + enum: SETD1R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: Timer A compare 1 + enum: SETD1R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: Timer A compare 2 + enum: SETD1R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: Timer A compare 3 + enum: SETD1R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: Timer A compare 4 + enum: SETD1R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: Master Period + enum: SETD1R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: Master Compare 1 + enum: SETD1R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: Master Compare 2 + enum: SETD1R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: Master Compare 3 + enum: SETD1R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: Master Compare 4 + enum: SETD1R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: Timer Event 1 + enum: SETD1R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: Timer Event 2 + enum: SETD1R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: Timer Event 3 + enum: SETD1R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: Timer Event 4 + enum: SETD1R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: Timer Event 5 + enum: SETD1R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: Timer Event 6 + enum: SETD1R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: Timer Event 7 + enum: SETD1R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: Timer Event 8 + enum: SETD1R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: Timer Event 9 + enum: SETD1R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: External Event 1 + enum: SETD1R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: External Event 2 + enum: SETD1R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: External Event 3 + enum: SETD1R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: External Event 4 + enum: SETD1R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: External Event 5 + enum: SETD1R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: External Event 6 + enum: SETD1R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: External Event 7 + enum: SETD1R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: External Event 8 + enum: SETD1R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: External Event 9 + enum: SETD1R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: External Event 10 + enum: SETD1R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: "Registers update (transfer preload to\r active)" + enum: SETD1R_UPDATE + name: UPDATE +fieldset/SETD2R: + description: Timerx Output2 Set Register + fields: + - bit_offset: 0 + bit_size: 1 + description: SST + enum: SETD2R_SST + name: SST + - bit_offset: 1 + bit_size: 1 + description: RESYNC + enum: SETD2R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: PER + enum: SETD2R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: CMP1 + enum: SETD2R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: CMP2 + enum: SETD2R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: CMP3 + enum: SETD2R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: CMP4 + enum: SETD2R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: MSTPER + enum: SETD2R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: MSTCMP1 + enum: SETD2R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: MSTCMP2 + enum: SETD2R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: MSTCMP3 + enum: SETD2R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: MSTCMP4 + enum: SETD2R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: TIMEVNT1 + enum: SETD2R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: TIMEVNT2 + enum: SETD2R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: TIMEVNT3 + enum: SETD2R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: TIMEVNT4 + enum: SETD2R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: TIMEVNT5 + enum: SETD2R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: TIMEVNT6 + enum: SETD2R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: TIMEVNT7 + enum: SETD2R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: TIMEVNT8 + enum: SETD2R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: TIMEVNT9 + enum: SETD2R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: EXTEVNT1 + enum: SETD2R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: EXTEVNT2 + enum: SETD2R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: EXTEVNT3 + enum: SETD2R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: EXTEVNT4 + enum: SETD2R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: EXTEVNT5 + enum: SETD2R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: EXTEVNT6 + enum: SETD2R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: EXTEVNT7 + enum: SETD2R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: EXTEVNT8 + enum: SETD2R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: EXTEVNT9 + enum: SETD2R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: EXTEVNT10 + enum: SETD2R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: UPDATE + enum: SETD2R_UPDATE + name: UPDATE +fieldset/SETE1R: + description: Timerx Output1 Set Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Software Set trigger + enum: SETE1R_SST + name: SST + - bit_offset: 1 + bit_size: 1 + description: Timer A resynchronizaton + enum: SETE1R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: Timer A Period + enum: SETE1R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: Timer A compare 1 + enum: SETE1R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: Timer A compare 2 + enum: SETE1R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: Timer A compare 3 + enum: SETE1R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: Timer A compare 4 + enum: SETE1R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: Master Period + enum: SETE1R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: Master Compare 1 + enum: SETE1R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: Master Compare 2 + enum: SETE1R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: Master Compare 3 + enum: SETE1R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: Master Compare 4 + enum: SETE1R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: Timer Event 1 + enum: SETE1R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: Timer Event 2 + enum: SETE1R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: Timer Event 3 + enum: SETE1R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: Timer Event 4 + enum: SETE1R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: Timer Event 5 + enum: SETE1R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: Timer Event 6 + enum: SETE1R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: Timer Event 7 + enum: SETE1R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: Timer Event 8 + enum: SETE1R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: Timer Event 9 + enum: SETE1R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: External Event 1 + enum: SETE1R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: External Event 2 + enum: SETE1R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: External Event 3 + enum: SETE1R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: External Event 4 + enum: SETE1R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: External Event 5 + enum: SETE1R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: External Event 6 + enum: SETE1R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: External Event 7 + enum: SETE1R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: External Event 8 + enum: SETE1R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: External Event 9 + enum: SETE1R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: External Event 10 + enum: SETE1R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: "Registers update (transfer preload to\r active)" + enum: SETE1R_UPDATE + name: UPDATE +fieldset/SETE2R: + description: Timerx Output2 Set Register + fields: + - bit_offset: 0 + bit_size: 1 + description: SST + enum: SETE2R_SST + name: SST + - bit_offset: 1 + bit_size: 1 + description: RESYNC + enum: SETE2R_RESYNC + name: RESYNC + - bit_offset: 2 + bit_size: 1 + description: PER + enum: SETE2R_PER + name: PER + - bit_offset: 3 + bit_size: 1 + description: CMP1 + enum: SETE2R_CMP1 + name: CMP1 + - bit_offset: 4 + bit_size: 1 + description: CMP2 + enum: SETE2R_CMP1 + name: CMP2 + - bit_offset: 5 + bit_size: 1 + description: CMP3 + enum: SETE2R_CMP1 + name: CMP3 + - bit_offset: 6 + bit_size: 1 + description: CMP4 + enum: SETE2R_CMP1 + name: CMP4 + - bit_offset: 7 + bit_size: 1 + description: MSTPER + enum: SETE2R_MSTPER + name: MSTPER + - bit_offset: 8 + bit_size: 1 + description: MSTCMP1 + enum: SETE2R_MSTCMP1 + name: MSTCMP1 + - bit_offset: 9 + bit_size: 1 + description: MSTCMP2 + enum: SETE2R_MSTCMP1 + name: MSTCMP2 + - bit_offset: 10 + bit_size: 1 + description: MSTCMP3 + enum: SETE2R_MSTCMP1 + name: MSTCMP3 + - bit_offset: 11 + bit_size: 1 + description: MSTCMP4 + enum: SETE2R_MSTCMP1 + name: MSTCMP4 + - bit_offset: 12 + bit_size: 1 + description: TIMEVNT1 + enum: SETE2R_TIMEVNT1 + name: TIMEVNT1 + - bit_offset: 13 + bit_size: 1 + description: TIMEVNT2 + enum: SETE2R_TIMEVNT1 + name: TIMEVNT2 + - bit_offset: 14 + bit_size: 1 + description: TIMEVNT3 + enum: SETE2R_TIMEVNT1 + name: TIMEVNT3 + - bit_offset: 15 + bit_size: 1 + description: TIMEVNT4 + enum: SETE2R_TIMEVNT1 + name: TIMEVNT4 + - bit_offset: 16 + bit_size: 1 + description: TIMEVNT5 + enum: SETE2R_TIMEVNT1 + name: TIMEVNT5 + - bit_offset: 17 + bit_size: 1 + description: TIMEVNT6 + enum: SETE2R_TIMEVNT1 + name: TIMEVNT6 + - bit_offset: 18 + bit_size: 1 + description: TIMEVNT7 + enum: SETE2R_TIMEVNT1 + name: TIMEVNT7 + - bit_offset: 19 + bit_size: 1 + description: TIMEVNT8 + enum: SETE2R_TIMEVNT1 + name: TIMEVNT8 + - bit_offset: 20 + bit_size: 1 + description: TIMEVNT9 + enum: SETE2R_TIMEVNT1 + name: TIMEVNT9 + - bit_offset: 21 + bit_size: 1 + description: EXTEVNT1 + enum: SETE2R_EXTEVNT1 + name: EXTEVNT1 + - bit_offset: 22 + bit_size: 1 + description: EXTEVNT2 + enum: SETE2R_EXTEVNT1 + name: EXTEVNT2 + - bit_offset: 23 + bit_size: 1 + description: EXTEVNT3 + enum: SETE2R_EXTEVNT1 + name: EXTEVNT3 + - bit_offset: 24 + bit_size: 1 + description: EXTEVNT4 + enum: SETE2R_EXTEVNT1 + name: EXTEVNT4 + - bit_offset: 25 + bit_size: 1 + description: EXTEVNT5 + enum: SETE2R_EXTEVNT1 + name: EXTEVNT5 + - bit_offset: 26 + bit_size: 1 + description: EXTEVNT6 + enum: SETE2R_EXTEVNT1 + name: EXTEVNT6 + - bit_offset: 27 + bit_size: 1 + description: EXTEVNT7 + enum: SETE2R_EXTEVNT1 + name: EXTEVNT7 + - bit_offset: 28 + bit_size: 1 + description: EXTEVNT8 + enum: SETE2R_EXTEVNT1 + name: EXTEVNT8 + - bit_offset: 29 + bit_size: 1 + description: EXTEVNT9 + enum: SETE2R_EXTEVNT1 + name: EXTEVNT9 + - bit_offset: 30 + bit_size: 1 + description: EXTEVNT10 + enum: SETE2R_EXTEVNT1 + name: EXTEVNT10 + - bit_offset: 31 + bit_size: 1 + description: UPDATE + enum: SETE2R_UPDATE + name: UPDATE +fieldset/TIMACR: + description: Timerx Control Register + fields: + - bit_offset: 0 + bit_size: 3 + description: "HRTIM Timer x Clock\r prescaler" + name: CKPSCx + - bit_offset: 3 + bit_size: 1 + description: Continuous mode + enum: CONT + name: CONT + - bit_offset: 4 + bit_size: 1 + description: Re-triggerable mode + enum: RETRIG + name: RETRIG + - bit_offset: 5 + bit_size: 1 + description: Half mode enable + enum: HALF + name: HALF + - bit_offset: 6 + bit_size: 1 + description: Push-Pull mode enable + enum: PSHPLL + name: PSHPLL + - bit_offset: 10 + bit_size: 1 + description: "Synchronization Resets Timer\r x" + enum: SYNCRSTx + name: SYNCRSTx + - bit_offset: 11 + bit_size: 1 + description: "Synchronization Starts Timer\r x" + enum: SYNCSTRTx + name: SYNCSTRTx + - bit_offset: 12 + bit_size: 2 + description: Delayed CMP2 mode + enum: DELCMP2 + name: DELCMP2 + - bit_offset: 14 + bit_size: 2 + description: Delayed CMP4 mode + enum: DELCMP4 + name: DELCMP4 + - bit_offset: 17 + bit_size: 1 + description: Timer x Repetition update + enum: TxREPU + name: TxREPU + - bit_offset: 18 + bit_size: 1 + description: Timerx reset update + enum: TxRSTU + name: TxRSTU + - bit_offset: 20 + bit_size: 1 + description: TBU + enum: TBU + name: TBU + - bit_offset: 21 + bit_size: 1 + description: TCU + enum: TBU + name: TCU + - bit_offset: 22 + bit_size: 1 + description: TDU + enum: TBU + name: TDU + - bit_offset: 23 + bit_size: 1 + description: TEU + enum: TBU + name: TEU + - bit_offset: 24 + bit_size: 1 + description: Master Timer update + enum: MSTU + name: MSTU + - bit_offset: 25 + bit_size: 2 + description: AC Synchronization + enum: DACSYNC + name: DACSYNC + - bit_offset: 27 + bit_size: 1 + description: Preload enable + enum: PREEN + name: PREEN + - bit_offset: 28 + bit_size: 4 + description: Update Gating + enum: UPDGAT + name: UPDGAT +fieldset/TIMADIER: + description: TIMxDIER5 + fields: + - bit_offset: 0 + bit_size: 1 + description: CMP1IE + enum: CMP1IE + name: CMP1IE + - bit_offset: 1 + bit_size: 1 + description: CMP2IE + enum: CMP1IE + name: CMP2IE + - bit_offset: 2 + bit_size: 1 + description: CMP3IE + enum: CMP1IE + name: CMP3IE + - bit_offset: 3 + bit_size: 1 + description: CMP4IE + enum: CMP1IE + name: CMP4IE + - bit_offset: 4 + bit_size: 1 + description: REPIE + enum: REPIE + name: REPIE + - bit_offset: 6 + bit_size: 1 + description: UPDIE + enum: UPDIE + name: UPDIE + - bit_offset: 7 + bit_size: 1 + description: CPT1IE + enum: CPT1IE + name: CPT1IE + - bit_offset: 8 + bit_size: 1 + description: CPT2IE + enum: CPT1IE + name: CPT2IE + - bit_offset: 9 + bit_size: 1 + description: SET1xIE + enum: SETx1IE + name: SETx1IE + - bit_offset: 10 + bit_size: 1 + description: RSTx1IE + enum: RSTx1IE + name: RSTx1IE + - bit_offset: 11 + bit_size: 1 + description: SETx2IE + enum: SETx1IE + name: SETx2IE + - bit_offset: 12 + bit_size: 1 + description: RSTx2IE + enum: RSTx1IE + name: RSTx2IE + - bit_offset: 13 + bit_size: 1 + description: RSTIE + enum: RSTIE + name: RSTIE + - bit_offset: 14 + bit_size: 1 + description: DLYPRTIE + enum: DLYPRTIE + name: DLYPRTIE + - bit_offset: 16 + bit_size: 1 + description: CMP1DE + enum: CMP1DE + name: CMP1DE + - bit_offset: 17 + bit_size: 1 + description: CMP2DE + enum: CMP1DE + name: CMP2DE + - bit_offset: 18 + bit_size: 1 + description: CMP3DE + enum: CMP1DE + name: CMP3DE + - bit_offset: 19 + bit_size: 1 + description: CMP4DE + enum: CMP1DE + name: CMP4DE + - bit_offset: 20 + bit_size: 1 + description: REPDE + enum: REPDE + name: REPDE + - bit_offset: 22 + bit_size: 1 + description: UPDDE + enum: UPDDE + name: UPDDE + - bit_offset: 23 + bit_size: 1 + description: CPT1DE + enum: CPT1DE + name: CPT1DE + - bit_offset: 24 + bit_size: 1 + description: CPT2DE + enum: CPT1DE + name: CPT2DE + - bit_offset: 25 + bit_size: 1 + description: SET1xDE + enum: SETx1DE + name: SETx1DE + - bit_offset: 26 + bit_size: 1 + description: RSTx1DE + enum: RSTx1DE + name: RSTx1DE + - bit_offset: 27 + bit_size: 1 + description: SETx2DE + enum: SETx1DE + name: SETx2DE + - bit_offset: 28 + bit_size: 1 + description: RSTx2DE + enum: RSTx1DE + name: RSTx2DE + - bit_offset: 29 + bit_size: 1 + description: RSTDE + enum: RSTDE + name: RSTDE + - bit_offset: 30 + bit_size: 1 + description: DLYPRTDE + enum: DLYPRTDE + name: DLYPRTDE +fieldset/TIMAICR: + description: "Timerx Interrupt Clear\r Register" + fields: + - bit_offset: 0 + bit_size: 1 + description: "Compare 1 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP1C + - bit_offset: 1 + bit_size: 1 + description: "Compare 2 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP2C + - bit_offset: 2 + bit_size: 1 + description: "Compare 3 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP3C + - bit_offset: 3 + bit_size: 1 + description: "Compare 4 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP4C + - bit_offset: 4 + bit_size: 1 + description: "Repetition Interrupt flag\r Clear" + enum_write: CMP1C + name: REPC + - bit_offset: 6 + bit_size: 1 + description: "Update Interrupt flag\r Clear" + enum_write: CMP1C + name: UPDC + - bit_offset: 7 + bit_size: 1 + description: "Capture1 Interrupt flag\r Clear" + enum_write: CMP1C + name: CPT1C + - bit_offset: 8 + bit_size: 1 + description: "Capture2 Interrupt flag\r Clear" + enum_write: CMP1C + name: CPT2C + - bit_offset: 9 + bit_size: 1 + description: Output 1 Set flag Clear + enum_write: CMP1C + name: SET1xC + - bit_offset: 10 + bit_size: 1 + description: Output 1 Reset flag Clear + enum_write: CMP1C + name: RSTx1C + - bit_offset: 11 + bit_size: 1 + description: Output 2 Set flag Clear + enum_write: CMP1C + name: SET2xC + - bit_offset: 12 + bit_size: 1 + description: Output 2 Reset flag Clear + enum_write: CMP1C + name: RSTx2C + - bit_offset: 13 + bit_size: 1 + description: Reset Interrupt flag Clear + enum_write: CMP1C + name: RSTC + - bit_offset: 14 + bit_size: 1 + description: "Delayed Protection Flag\r Clear" + enum_write: CMP1C + name: DLYPRTC +fieldset/TIMAISR: + description: "Timerx Interrupt Status\r Register" + fields: + - bit_offset: 0 + bit_size: 1 + description: Compare 1 Interrupt Flag + enum_read: TIMAISR_CMP1 + name: CMP1 + - bit_offset: 1 + bit_size: 1 + description: Compare 2 Interrupt Flag + enum_read: TIMAISR_CMP1 + name: CMP2 + - bit_offset: 2 + bit_size: 1 + description: Compare 3 Interrupt Flag + enum_read: TIMAISR_CMP1 + name: CMP3 + - bit_offset: 3 + bit_size: 1 + description: Compare 4 Interrupt Flag + enum_read: TIMAISR_CMP1 + name: CMP4 + - bit_offset: 4 + bit_size: 1 + description: Repetition Interrupt Flag + enum_read: REP + name: REP + - bit_offset: 6 + bit_size: 1 + description: Update Interrupt Flag + enum_read: UPD + name: UPD + - bit_offset: 7 + bit_size: 1 + description: Capture1 Interrupt Flag + enum_read: CPT1 + name: CPT1 + - bit_offset: 8 + bit_size: 1 + description: Capture2 Interrupt Flag + enum_read: CPT1 + name: CPT2 + - bit_offset: 9 + bit_size: 1 + description: "Output 1 Set Interrupt\r Flag" + enum_read: SETx1 + name: SETx1 + - bit_offset: 10 + bit_size: 1 + description: "Output 1 Reset Interrupt\r Flag" + enum_read: RSTx1 + name: RSTx1 + - bit_offset: 11 + bit_size: 1 + description: "Output 2 Set Interrupt\r Flag" + enum_read: SETx1 + name: SETx2 + - bit_offset: 12 + bit_size: 1 + description: "Output 2 Reset Interrupt\r Flag" + enum_read: RSTx1 + name: RSTx2 + - bit_offset: 13 + bit_size: 1 + description: Reset Interrupt Flag + enum_read: RST + name: RST + - bit_offset: 14 + bit_size: 1 + description: Delayed Protection Flag + enum_read: TIMAISR_DLYPRT + name: DLYPRT + - bit_offset: 16 + bit_size: 1 + description: Current Push Pull Status + enum_read: CPPSTAT + name: CPPSTAT + - bit_offset: 17 + bit_size: 1 + description: Idle Push Pull Status + enum_read: IPPSTAT + name: IPPSTAT + - bit_offset: 18 + bit_size: 1 + description: Output 1 State + enum_read: O1STAT + name: O1STAT + - bit_offset: 19 + bit_size: 1 + description: Output 2 State + enum_read: O1STAT + name: O2STAT + - bit_offset: 20 + bit_size: 1 + description: Output 1 Copy + enum_read: O1CPY + name: O1CPY + - bit_offset: 21 + bit_size: 1 + description: Output 2 Copy + enum_read: O1CPY + name: O2CPY +fieldset/TIMBCR: + description: Timerx Control Register + fields: + - bit_offset: 0 + bit_size: 3 + description: "HRTIM Timer x Clock\r prescaler" + name: CKPSCx + - bit_offset: 3 + bit_size: 1 + description: Continuous mode + enum: CONT + name: CONT + - bit_offset: 4 + bit_size: 1 + description: Re-triggerable mode + enum: RETRIG + name: RETRIG + - bit_offset: 5 + bit_size: 1 + description: Half mode enable + enum: HALF + name: HALF + - bit_offset: 6 + bit_size: 1 + description: Push-Pull mode enable + enum: PSHPLL + name: PSHPLL + - bit_offset: 10 + bit_size: 1 + description: "Synchronization Resets Timer\r x" + enum: SYNCRSTx + name: SYNCRSTx + - bit_offset: 11 + bit_size: 1 + description: "Synchronization Starts Timer\r x" + enum: SYNCSTRTx + name: SYNCSTRTx + - bit_offset: 12 + bit_size: 2 + description: Delayed CMP2 mode + enum: DELCMP2 + name: DELCMP2 + - bit_offset: 14 + bit_size: 2 + description: Delayed CMP4 mode + enum: DELCMP4 + name: DELCMP4 + - bit_offset: 17 + bit_size: 1 + description: Timer x Repetition update + enum: TxREPU + name: TxREPU + - bit_offset: 18 + bit_size: 1 + description: Timerx reset update + enum: TxRSTU + name: TxRSTU + - bit_offset: 20 + bit_size: 1 + description: TBU + enum: TBU + name: TBU + - bit_offset: 21 + bit_size: 1 + description: TCU + enum: TBU + name: TCU + - bit_offset: 22 + bit_size: 1 + description: TDU + enum: TBU + name: TDU + - bit_offset: 23 + bit_size: 1 + description: TEU + enum: TBU + name: TEU + - bit_offset: 24 + bit_size: 1 + description: Master Timer update + enum: MSTU + name: MSTU + - bit_offset: 25 + bit_size: 2 + description: AC Synchronization + enum: DACSYNC + name: DACSYNC + - bit_offset: 27 + bit_size: 1 + description: Preload enable + enum: PREEN + name: PREEN + - bit_offset: 28 + bit_size: 4 + description: Update Gating + enum: UPDGAT + name: UPDGAT +fieldset/TIMBDIER: + description: TIMxDIER5 + fields: + - bit_offset: 0 + bit_size: 1 + description: CMP1IE + enum: CMP1IE + name: CMP1IE + - bit_offset: 1 + bit_size: 1 + description: CMP2IE + enum: CMP1IE + name: CMP2IE + - bit_offset: 2 + bit_size: 1 + description: CMP3IE + enum: CMP1IE + name: CMP3IE + - bit_offset: 3 + bit_size: 1 + description: CMP4IE + enum: CMP1IE + name: CMP4IE + - bit_offset: 4 + bit_size: 1 + description: REPIE + enum: REPIE + name: REPIE + - bit_offset: 6 + bit_size: 1 + description: UPDIE + enum: UPDIE + name: UPDIE + - bit_offset: 7 + bit_size: 1 + description: CPT1IE + enum: CPT1IE + name: CPT1IE + - bit_offset: 8 + bit_size: 1 + description: CPT2IE + enum: CPT1IE + name: CPT2IE + - bit_offset: 9 + bit_size: 1 + description: SET1xIE + enum: SETx1IE + name: SETx1IE + - bit_offset: 10 + bit_size: 1 + description: RSTx1IE + enum: RSTx1IE + name: RSTx1IE + - bit_offset: 11 + bit_size: 1 + description: SETx2IE + enum: SETx1IE + name: SETx2IE + - bit_offset: 12 + bit_size: 1 + description: RSTx2IE + enum: RSTx1IE + name: RSTx2IE + - bit_offset: 13 + bit_size: 1 + description: RSTIE + enum: RSTIE + name: RSTIE + - bit_offset: 14 + bit_size: 1 + description: DLYPRTIE + enum: DLYPRTIE + name: DLYPRTIE + - bit_offset: 16 + bit_size: 1 + description: CMP1DE + enum: CMP1DE + name: CMP1DE + - bit_offset: 17 + bit_size: 1 + description: CMP2DE + enum: CMP1DE + name: CMP2DE + - bit_offset: 18 + bit_size: 1 + description: CMP3DE + enum: CMP1DE + name: CMP3DE + - bit_offset: 19 + bit_size: 1 + description: CMP4DE + enum: CMP1DE + name: CMP4DE + - bit_offset: 20 + bit_size: 1 + description: REPDE + enum: REPDE + name: REPDE + - bit_offset: 22 + bit_size: 1 + description: UPDDE + enum: UPDDE + name: UPDDE + - bit_offset: 23 + bit_size: 1 + description: CPT1DE + enum: CPT1DE + name: CPT1DE + - bit_offset: 24 + bit_size: 1 + description: CPT2DE + enum: CPT1DE + name: CPT2DE + - bit_offset: 25 + bit_size: 1 + description: SET1xDE + enum: SETx1DE + name: SETx1DE + - bit_offset: 26 + bit_size: 1 + description: RSTx1DE + enum: RSTx1DE + name: RSTx1DE + - bit_offset: 27 + bit_size: 1 + description: SETx2DE + enum: SETx1DE + name: SETx2DE + - bit_offset: 28 + bit_size: 1 + description: RSTx2DE + enum: RSTx1DE + name: RSTx2DE + - bit_offset: 29 + bit_size: 1 + description: RSTDE + enum: RSTDE + name: RSTDE + - bit_offset: 30 + bit_size: 1 + description: DLYPRTDE + enum: DLYPRTDE + name: DLYPRTDE +fieldset/TIMBICR: + description: "Timerx Interrupt Clear\r Register" + fields: + - bit_offset: 0 + bit_size: 1 + description: "Compare 1 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP1C + - bit_offset: 1 + bit_size: 1 + description: "Compare 2 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP2C + - bit_offset: 2 + bit_size: 1 + description: "Compare 3 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP3C + - bit_offset: 3 + bit_size: 1 + description: "Compare 4 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP4C + - bit_offset: 4 + bit_size: 1 + description: "Repetition Interrupt flag\r Clear" + enum_write: CMP1C + name: REPC + - bit_offset: 6 + bit_size: 1 + description: "Update Interrupt flag\r Clear" + enum_write: CMP1C + name: UPDC + - bit_offset: 7 + bit_size: 1 + description: "Capture1 Interrupt flag\r Clear" + enum_write: CMP1C + name: CPT1C + - bit_offset: 8 + bit_size: 1 + description: "Capture2 Interrupt flag\r Clear" + enum_write: CMP1C + name: CPT2C + - bit_offset: 9 + bit_size: 1 + description: Output 1 Set flag Clear + enum_write: CMP1C + name: SET1xC + - bit_offset: 10 + bit_size: 1 + description: Output 1 Reset flag Clear + enum_write: CMP1C + name: RSTx1C + - bit_offset: 11 + bit_size: 1 + description: Output 2 Set flag Clear + enum_write: CMP1C + name: SET2xC + - bit_offset: 12 + bit_size: 1 + description: Output 2 Reset flag Clear + enum_write: CMP1C + name: RSTx2C + - bit_offset: 13 + bit_size: 1 + description: Reset Interrupt flag Clear + enum_write: CMP1C + name: RSTC + - bit_offset: 14 + bit_size: 1 + description: "Delayed Protection Flag\r Clear" + enum_write: CMP1C + name: DLYPRTC +fieldset/TIMBISR: + description: "Timerx Interrupt Status\r Register" + fields: + - bit_offset: 0 + bit_size: 1 + description: Compare 1 Interrupt Flag + enum_read: TIMBISR_CMP1 + name: CMP1 + - bit_offset: 1 + bit_size: 1 + description: Compare 2 Interrupt Flag + enum_read: TIMBISR_CMP1 + name: CMP2 + - bit_offset: 2 + bit_size: 1 + description: Compare 3 Interrupt Flag + enum_read: TIMBISR_CMP1 + name: CMP3 + - bit_offset: 3 + bit_size: 1 + description: Compare 4 Interrupt Flag + enum_read: TIMBISR_CMP1 + name: CMP4 + - bit_offset: 4 + bit_size: 1 + description: Repetition Interrupt Flag + enum_read: REP + name: REP + - bit_offset: 6 + bit_size: 1 + description: Update Interrupt Flag + enum_read: UPD + name: UPD + - bit_offset: 7 + bit_size: 1 + description: Capture1 Interrupt Flag + enum_read: CPT1 + name: CPT1 + - bit_offset: 8 + bit_size: 1 + description: Capture2 Interrupt Flag + enum_read: CPT1 + name: CPT2 + - bit_offset: 9 + bit_size: 1 + description: "Output 1 Set Interrupt\r Flag" + enum_read: SETx1 + name: SETx1 + - bit_offset: 10 + bit_size: 1 + description: "Output 1 Reset Interrupt\r Flag" + enum_read: RSTx1 + name: RSTx1 + - bit_offset: 11 + bit_size: 1 + description: "Output 2 Set Interrupt\r Flag" + enum_read: SETx1 + name: SETx2 + - bit_offset: 12 + bit_size: 1 + description: "Output 2 Reset Interrupt\r Flag" + enum_read: RSTx1 + name: RSTx2 + - bit_offset: 13 + bit_size: 1 + description: Reset Interrupt Flag + enum_read: RST + name: RST + - bit_offset: 14 + bit_size: 1 + description: Delayed Protection Flag + enum_read: TIMBISR_DLYPRT + name: DLYPRT + - bit_offset: 16 + bit_size: 1 + description: Current Push Pull Status + enum_read: CPPSTAT + name: CPPSTAT + - bit_offset: 17 + bit_size: 1 + description: Idle Push Pull Status + enum_read: IPPSTAT + name: IPPSTAT + - bit_offset: 18 + bit_size: 1 + description: Output 1 State + enum_read: O1STAT + name: O1STAT + - bit_offset: 19 + bit_size: 1 + description: Output 2 State + enum_read: O1STAT + name: O2STAT + - bit_offset: 20 + bit_size: 1 + description: Output 1 Copy + enum_read: O1CPY + name: O1CPY + - bit_offset: 21 + bit_size: 1 + description: Output 2 Copy + enum_read: O1CPY + name: O2CPY +fieldset/TIMCCR: + description: Timerx Control Register + fields: + - bit_offset: 0 + bit_size: 3 + description: "HRTIM Timer x Clock\r prescaler" + name: CKPSCx + - bit_offset: 3 + bit_size: 1 + description: Continuous mode + enum: CONT + name: CONT + - bit_offset: 4 + bit_size: 1 + description: Re-triggerable mode + enum: RETRIG + name: RETRIG + - bit_offset: 5 + bit_size: 1 + description: Half mode enable + enum: HALF + name: HALF + - bit_offset: 6 + bit_size: 1 + description: Push-Pull mode enable + enum: PSHPLL + name: PSHPLL + - bit_offset: 10 + bit_size: 1 + description: "Synchronization Resets Timer\r x" + enum: SYNCRSTx + name: SYNCRSTx + - bit_offset: 11 + bit_size: 1 + description: "Synchronization Starts Timer\r x" + enum: SYNCSTRTx + name: SYNCSTRTx + - bit_offset: 12 + bit_size: 2 + description: Delayed CMP2 mode + enum: DELCMP2 + name: DELCMP2 + - bit_offset: 14 + bit_size: 2 + description: Delayed CMP4 mode + enum: DELCMP4 + name: DELCMP4 + - bit_offset: 17 + bit_size: 1 + description: Timer x Repetition update + enum: TxREPU + name: TxREPU + - bit_offset: 18 + bit_size: 1 + description: Timerx reset update + enum: TxRSTU + name: TxRSTU + - bit_offset: 20 + bit_size: 1 + description: TBU + enum: TBU + name: TBU + - bit_offset: 21 + bit_size: 1 + description: TCU + enum: TBU + name: TCU + - bit_offset: 22 + bit_size: 1 + description: TDU + enum: TBU + name: TDU + - bit_offset: 23 + bit_size: 1 + description: TEU + enum: TBU + name: TEU + - bit_offset: 24 + bit_size: 1 + description: Master Timer update + enum: MSTU + name: MSTU + - bit_offset: 25 + bit_size: 2 + description: AC Synchronization + enum: DACSYNC + name: DACSYNC + - bit_offset: 27 + bit_size: 1 + description: Preload enable + enum: PREEN + name: PREEN + - bit_offset: 28 + bit_size: 4 + description: Update Gating + enum: UPDGAT + name: UPDGAT +fieldset/TIMCDIER: + description: TIMxDIER5 + fields: + - bit_offset: 0 + bit_size: 1 + description: CMP1IE + enum: CMP1IE + name: CMP1IE + - bit_offset: 1 + bit_size: 1 + description: CMP2IE + enum: CMP1IE + name: CMP2IE + - bit_offset: 2 + bit_size: 1 + description: CMP3IE + enum: CMP1IE + name: CMP3IE + - bit_offset: 3 + bit_size: 1 + description: CMP4IE + enum: CMP1IE + name: CMP4IE + - bit_offset: 4 + bit_size: 1 + description: REPIE + enum: REPIE + name: REPIE + - bit_offset: 6 + bit_size: 1 + description: UPDIE + enum: UPDIE + name: UPDIE + - bit_offset: 7 + bit_size: 1 + description: CPT1IE + enum: CPT1IE + name: CPT1IE + - bit_offset: 8 + bit_size: 1 + description: CPT2IE + enum: CPT1IE + name: CPT2IE + - bit_offset: 9 + bit_size: 1 + description: SET1xIE + enum: SETx1IE + name: SETx1IE + - bit_offset: 10 + bit_size: 1 + description: RSTx1IE + enum: RSTx1IE + name: RSTx1IE + - bit_offset: 11 + bit_size: 1 + description: SETx2IE + enum: SETx1IE + name: SETx2IE + - bit_offset: 12 + bit_size: 1 + description: RSTx2IE + enum: RSTx1IE + name: RSTx2IE + - bit_offset: 13 + bit_size: 1 + description: RSTIE + enum: RSTIE + name: RSTIE + - bit_offset: 14 + bit_size: 1 + description: DLYPRTIE + enum: DLYPRTIE + name: DLYPRTIE + - bit_offset: 16 + bit_size: 1 + description: CMP1DE + enum: CMP1DE + name: CMP1DE + - bit_offset: 17 + bit_size: 1 + description: CMP2DE + enum: CMP1DE + name: CMP2DE + - bit_offset: 18 + bit_size: 1 + description: CMP3DE + enum: CMP1DE + name: CMP3DE + - bit_offset: 19 + bit_size: 1 + description: CMP4DE + enum: CMP1DE + name: CMP4DE + - bit_offset: 20 + bit_size: 1 + description: REPDE + enum: REPDE + name: REPDE + - bit_offset: 22 + bit_size: 1 + description: UPDDE + enum: UPDDE + name: UPDDE + - bit_offset: 23 + bit_size: 1 + description: CPT1DE + enum: CPT1DE + name: CPT1DE + - bit_offset: 24 + bit_size: 1 + description: CPT2DE + enum: CPT1DE + name: CPT2DE + - bit_offset: 25 + bit_size: 1 + description: SET1xDE + enum: SETx1DE + name: SETx1DE + - bit_offset: 26 + bit_size: 1 + description: RSTx1DE + enum: RSTx1DE + name: RSTx1DE + - bit_offset: 27 + bit_size: 1 + description: SETx2DE + enum: SETx1DE + name: SETx2DE + - bit_offset: 28 + bit_size: 1 + description: RSTx2DE + enum: RSTx1DE + name: RSTx2DE + - bit_offset: 29 + bit_size: 1 + description: RSTDE + enum: RSTDE + name: RSTDE + - bit_offset: 30 + bit_size: 1 + description: DLYPRTDE + enum: DLYPRTDE + name: DLYPRTDE +fieldset/TIMCICR: + description: "Timerx Interrupt Clear\r Register" + fields: + - bit_offset: 0 + bit_size: 1 + description: "Compare 1 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP1C + - bit_offset: 1 + bit_size: 1 + description: "Compare 2 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP2C + - bit_offset: 2 + bit_size: 1 + description: "Compare 3 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP3C + - bit_offset: 3 + bit_size: 1 + description: "Compare 4 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP4C + - bit_offset: 4 + bit_size: 1 + description: "Repetition Interrupt flag\r Clear" + enum_write: CMP1C + name: REPC + - bit_offset: 6 + bit_size: 1 + description: "Update Interrupt flag\r Clear" + enum_write: CMP1C + name: UPDC + - bit_offset: 7 + bit_size: 1 + description: "Capture1 Interrupt flag\r Clear" + enum_write: CMP1C + name: CPT1C + - bit_offset: 8 + bit_size: 1 + description: "Capture2 Interrupt flag\r Clear" + enum_write: CMP1C + name: CPT2C + - bit_offset: 9 + bit_size: 1 + description: Output 1 Set flag Clear + enum_write: CMP1C + name: SET1xC + - bit_offset: 10 + bit_size: 1 + description: Output 1 Reset flag Clear + enum_write: CMP1C + name: RSTx1C + - bit_offset: 11 + bit_size: 1 + description: Output 2 Set flag Clear + enum_write: CMP1C + name: SET2xC + - bit_offset: 12 + bit_size: 1 + description: Output 2 Reset flag Clear + enum_write: CMP1C + name: RSTx2C + - bit_offset: 13 + bit_size: 1 + description: Reset Interrupt flag Clear + enum_write: CMP1C + name: RSTC + - bit_offset: 14 + bit_size: 1 + description: "Delayed Protection Flag\r Clear" + enum_write: CMP1C + name: DLYPRTC +fieldset/TIMCISR: + description: "Timerx Interrupt Status\r Register" + fields: + - bit_offset: 0 + bit_size: 1 + description: Compare 1 Interrupt Flag + enum_read: TIMCISR_CMP1 + name: CMP1 + - bit_offset: 1 + bit_size: 1 + description: Compare 2 Interrupt Flag + enum_read: TIMCISR_CMP1 + name: CMP2 + - bit_offset: 2 + bit_size: 1 + description: Compare 3 Interrupt Flag + enum_read: TIMCISR_CMP1 + name: CMP3 + - bit_offset: 3 + bit_size: 1 + description: Compare 4 Interrupt Flag + enum_read: TIMCISR_CMP1 + name: CMP4 + - bit_offset: 4 + bit_size: 1 + description: Repetition Interrupt Flag + enum_read: REP + name: REP + - bit_offset: 6 + bit_size: 1 + description: Update Interrupt Flag + enum_read: UPD + name: UPD + - bit_offset: 7 + bit_size: 1 + description: Capture1 Interrupt Flag + enum_read: CPT1 + name: CPT1 + - bit_offset: 8 + bit_size: 1 + description: Capture2 Interrupt Flag + enum_read: CPT1 + name: CPT2 + - bit_offset: 9 + bit_size: 1 + description: "Output 1 Set Interrupt\r Flag" + enum_read: SETx1 + name: SETx1 + - bit_offset: 10 + bit_size: 1 + description: "Output 1 Reset Interrupt\r Flag" + enum_read: RSTx1 + name: RSTx1 + - bit_offset: 11 + bit_size: 1 + description: "Output 2 Set Interrupt\r Flag" + enum_read: SETx1 + name: SETx2 + - bit_offset: 12 + bit_size: 1 + description: "Output 2 Reset Interrupt\r Flag" + enum_read: RSTx1 + name: RSTx2 + - bit_offset: 13 + bit_size: 1 + description: Reset Interrupt Flag + enum_read: RST + name: RST + - bit_offset: 14 + bit_size: 1 + description: Delayed Protection Flag + enum_read: TIMCISR_DLYPRT + name: DLYPRT + - bit_offset: 16 + bit_size: 1 + description: Current Push Pull Status + enum_read: CPPSTAT + name: CPPSTAT + - bit_offset: 17 + bit_size: 1 + description: Idle Push Pull Status + enum_read: IPPSTAT + name: IPPSTAT + - bit_offset: 18 + bit_size: 1 + description: Output 1 State + enum_read: O1STAT + name: O1STAT + - bit_offset: 19 + bit_size: 1 + description: Output 2 State + enum_read: O1STAT + name: O2STAT + - bit_offset: 20 + bit_size: 1 + description: Output 1 Copy + enum_read: O1CPY + name: O1CPY + - bit_offset: 21 + bit_size: 1 + description: Output 2 Copy + enum_read: O1CPY + name: O2CPY +fieldset/TIMDCR: + description: Timerx Control Register + fields: + - bit_offset: 0 + bit_size: 3 + description: "HRTIM Timer x Clock\r prescaler" + name: CKPSCx + - bit_offset: 3 + bit_size: 1 + description: Continuous mode + enum: CONT + name: CONT + - bit_offset: 4 + bit_size: 1 + description: Re-triggerable mode + enum: RETRIG + name: RETRIG + - bit_offset: 5 + bit_size: 1 + description: Half mode enable + enum: HALF + name: HALF + - bit_offset: 6 + bit_size: 1 + description: Push-Pull mode enable + enum: PSHPLL + name: PSHPLL + - bit_offset: 10 + bit_size: 1 + description: "Synchronization Resets Timer\r x" + enum: SYNCRSTx + name: SYNCRSTx + - bit_offset: 11 + bit_size: 1 + description: "Synchronization Starts Timer\r x" + enum: SYNCSTRTx + name: SYNCSTRTx + - bit_offset: 12 + bit_size: 2 + description: Delayed CMP2 mode + enum: DELCMP2 + name: DELCMP2 + - bit_offset: 14 + bit_size: 2 + description: Delayed CMP4 mode + enum: DELCMP4 + name: DELCMP4 + - bit_offset: 17 + bit_size: 1 + description: Timer x Repetition update + enum: TxREPU + name: TxREPU + - bit_offset: 18 + bit_size: 1 + description: Timerx reset update + enum: TxRSTU + name: TxRSTU + - bit_offset: 20 + bit_size: 1 + description: TBU + enum: TBU + name: TBU + - bit_offset: 21 + bit_size: 1 + description: TCU + enum: TBU + name: TCU + - bit_offset: 22 + bit_size: 1 + description: TDU + enum: TBU + name: TDU + - bit_offset: 23 + bit_size: 1 + description: TEU + enum: TBU + name: TEU + - bit_offset: 24 + bit_size: 1 + description: Master Timer update + enum: MSTU + name: MSTU + - bit_offset: 25 + bit_size: 2 + description: AC Synchronization + enum: DACSYNC + name: DACSYNC + - bit_offset: 27 + bit_size: 1 + description: Preload enable + enum: PREEN + name: PREEN + - bit_offset: 28 + bit_size: 4 + description: Update Gating + enum: UPDGAT + name: UPDGAT +fieldset/TIMDDIER: + description: TIMxDIER5 + fields: + - bit_offset: 0 + bit_size: 1 + description: CMP1IE + enum: CMP1IE + name: CMP1IE + - bit_offset: 1 + bit_size: 1 + description: CMP2IE + enum: CMP1IE + name: CMP2IE + - bit_offset: 2 + bit_size: 1 + description: CMP3IE + enum: CMP1IE + name: CMP3IE + - bit_offset: 3 + bit_size: 1 + description: CMP4IE + enum: CMP1IE + name: CMP4IE + - bit_offset: 4 + bit_size: 1 + description: REPIE + enum: REPIE + name: REPIE + - bit_offset: 6 + bit_size: 1 + description: UPDIE + enum: UPDIE + name: UPDIE + - bit_offset: 7 + bit_size: 1 + description: CPT1IE + enum: CPT1IE + name: CPT1IE + - bit_offset: 8 + bit_size: 1 + description: CPT2IE + enum: CPT1IE + name: CPT2IE + - bit_offset: 9 + bit_size: 1 + description: SET1xIE + enum: SETx1IE + name: SETx1IE + - bit_offset: 10 + bit_size: 1 + description: RSTx1IE + enum: RSTx1IE + name: RSTx1IE + - bit_offset: 11 + bit_size: 1 + description: SETx2IE + enum: SETx1IE + name: SETx2IE + - bit_offset: 12 + bit_size: 1 + description: RSTx2IE + enum: RSTx1IE + name: RSTx2IE + - bit_offset: 13 + bit_size: 1 + description: RSTIE + enum: RSTIE + name: RSTIE + - bit_offset: 14 + bit_size: 1 + description: DLYPRTIE + enum: DLYPRTIE + name: DLYPRTIE + - bit_offset: 16 + bit_size: 1 + description: CMP1DE + enum: CMP1DE + name: CMP1DE + - bit_offset: 17 + bit_size: 1 + description: CMP2DE + enum: CMP1DE + name: CMP2DE + - bit_offset: 18 + bit_size: 1 + description: CMP3DE + enum: CMP1DE + name: CMP3DE + - bit_offset: 19 + bit_size: 1 + description: CMP4DE + enum: CMP1DE + name: CMP4DE + - bit_offset: 20 + bit_size: 1 + description: REPDE + enum: REPDE + name: REPDE + - bit_offset: 22 + bit_size: 1 + description: UPDDE + enum: UPDDE + name: UPDDE + - bit_offset: 23 + bit_size: 1 + description: CPT1DE + enum: CPT1DE + name: CPT1DE + - bit_offset: 24 + bit_size: 1 + description: CPT2DE + enum: CPT1DE + name: CPT2DE + - bit_offset: 25 + bit_size: 1 + description: SET1xDE + enum: SETx1DE + name: SETx1DE + - bit_offset: 26 + bit_size: 1 + description: RSTx1DE + enum: RSTx1DE + name: RSTx1DE + - bit_offset: 27 + bit_size: 1 + description: SETx2DE + enum: SETx1DE + name: SETx2DE + - bit_offset: 28 + bit_size: 1 + description: RSTx2DE + enum: RSTx1DE + name: RSTx2DE + - bit_offset: 29 + bit_size: 1 + description: RSTDE + enum: RSTDE + name: RSTDE + - bit_offset: 30 + bit_size: 1 + description: DLYPRTDE + enum: DLYPRTDE + name: DLYPRTDE +fieldset/TIMDICR: + description: "Timerx Interrupt Clear\r Register" + fields: + - bit_offset: 0 + bit_size: 1 + description: "Compare 1 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP1C + - bit_offset: 1 + bit_size: 1 + description: "Compare 2 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP2C + - bit_offset: 2 + bit_size: 1 + description: "Compare 3 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP3C + - bit_offset: 3 + bit_size: 1 + description: "Compare 4 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP4C + - bit_offset: 4 + bit_size: 1 + description: "Repetition Interrupt flag\r Clear" + enum_write: CMP1C + name: REPC + - bit_offset: 6 + bit_size: 1 + description: "Update Interrupt flag\r Clear" + enum_write: CMP1C + name: UPDC + - bit_offset: 7 + bit_size: 1 + description: "Capture1 Interrupt flag\r Clear" + enum_write: CMP1C + name: CPT1C + - bit_offset: 8 + bit_size: 1 + description: "Capture2 Interrupt flag\r Clear" + enum_write: CMP1C + name: CPT2C + - bit_offset: 9 + bit_size: 1 + description: Output 1 Set flag Clear + enum_write: CMP1C + name: SET1xC + - bit_offset: 10 + bit_size: 1 + description: Output 1 Reset flag Clear + enum_write: CMP1C + name: RSTx1C + - bit_offset: 11 + bit_size: 1 + description: Output 2 Set flag Clear + enum_write: CMP1C + name: SET2xC + - bit_offset: 12 + bit_size: 1 + description: Output 2 Reset flag Clear + enum_write: CMP1C + name: RSTx2C + - bit_offset: 13 + bit_size: 1 + description: Reset Interrupt flag Clear + enum_write: CMP1C + name: RSTC + - bit_offset: 14 + bit_size: 1 + description: "Delayed Protection Flag\r Clear" + enum_write: CMP1C + name: DLYPRTC +fieldset/TIMDISR: + description: "Timerx Interrupt Status\r Register" + fields: + - bit_offset: 0 + bit_size: 1 + description: Compare 1 Interrupt Flag + enum_read: TIMDISR_CMP1 + name: CMP1 + - bit_offset: 1 + bit_size: 1 + description: Compare 2 Interrupt Flag + enum_read: TIMDISR_CMP1 + name: CMP2 + - bit_offset: 2 + bit_size: 1 + description: Compare 3 Interrupt Flag + enum_read: TIMDISR_CMP1 + name: CMP3 + - bit_offset: 3 + bit_size: 1 + description: Compare 4 Interrupt Flag + enum_read: TIMDISR_CMP1 + name: CMP4 + - bit_offset: 4 + bit_size: 1 + description: Repetition Interrupt Flag + enum_read: REP + name: REP + - bit_offset: 6 + bit_size: 1 + description: Update Interrupt Flag + enum_read: UPD + name: UPD + - bit_offset: 7 + bit_size: 1 + description: Capture1 Interrupt Flag + enum_read: CPT1 + name: CPT1 + - bit_offset: 8 + bit_size: 1 + description: Capture2 Interrupt Flag + enum_read: CPT1 + name: CPT2 + - bit_offset: 9 + bit_size: 1 + description: "Output 1 Set Interrupt\r Flag" + enum_read: SETx1 + name: SETx1 + - bit_offset: 10 + bit_size: 1 + description: "Output 1 Reset Interrupt\r Flag" + enum_read: RSTx1 + name: RSTx1 + - bit_offset: 11 + bit_size: 1 + description: "Output 2 Set Interrupt\r Flag" + enum_read: SETx1 + name: SETx2 + - bit_offset: 12 + bit_size: 1 + description: "Output 2 Reset Interrupt\r Flag" + enum_read: RSTx1 + name: RSTx2 + - bit_offset: 13 + bit_size: 1 + description: Reset Interrupt Flag + enum_read: RST + name: RST + - bit_offset: 14 + bit_size: 1 + description: Delayed Protection Flag + enum_read: TIMDISR_DLYPRT + name: DLYPRT + - bit_offset: 16 + bit_size: 1 + description: Current Push Pull Status + enum_read: CPPSTAT + name: CPPSTAT + - bit_offset: 17 + bit_size: 1 + description: Idle Push Pull Status + enum_read: IPPSTAT + name: IPPSTAT + - bit_offset: 18 + bit_size: 1 + description: Output 1 State + enum_read: O1STAT + name: O1STAT + - bit_offset: 19 + bit_size: 1 + description: Output 2 State + enum_read: O1STAT + name: O2STAT + - bit_offset: 20 + bit_size: 1 + description: Output 1 Copy + enum_read: O1CPY + name: O1CPY + - bit_offset: 21 + bit_size: 1 + description: Output 2 Copy + enum_read: O1CPY + name: O2CPY +fieldset/TIMECR: + description: Timerx Control Register + fields: + - bit_offset: 0 + bit_size: 3 + description: "HRTIM Timer x Clock\r prescaler" + name: CKPSCx + - bit_offset: 3 + bit_size: 1 + description: Continuous mode + enum: CONT + name: CONT + - bit_offset: 4 + bit_size: 1 + description: Re-triggerable mode + enum: RETRIG + name: RETRIG + - bit_offset: 5 + bit_size: 1 + description: Half mode enable + enum: HALF + name: HALF + - bit_offset: 6 + bit_size: 1 + description: Push-Pull mode enable + enum: PSHPLL + name: PSHPLL + - bit_offset: 10 + bit_size: 1 + description: "Synchronization Resets Timer\r x" + enum: SYNCRSTx + name: SYNCRSTx + - bit_offset: 11 + bit_size: 1 + description: "Synchronization Starts Timer\r x" + enum: SYNCSTRTx + name: SYNCSTRTx + - bit_offset: 12 + bit_size: 2 + description: Delayed CMP2 mode + enum: DELCMP2 + name: DELCMP2 + - bit_offset: 14 + bit_size: 2 + description: Delayed CMP4 mode + enum: DELCMP4 + name: DELCMP4 + - bit_offset: 17 + bit_size: 1 + description: Timer x Repetition update + enum: TxREPU + name: TxREPU + - bit_offset: 18 + bit_size: 1 + description: Timerx reset update + enum: TxRSTU + name: TxRSTU + - bit_offset: 20 + bit_size: 1 + description: TBU + enum: TBU + name: TBU + - bit_offset: 21 + bit_size: 1 + description: TCU + enum: TBU + name: TCU + - bit_offset: 22 + bit_size: 1 + description: TDU + enum: TBU + name: TDU + - bit_offset: 23 + bit_size: 1 + description: TEU + enum: TBU + name: TEU + - bit_offset: 24 + bit_size: 1 + description: Master Timer update + enum: MSTU + name: MSTU + - bit_offset: 25 + bit_size: 2 + description: AC Synchronization + enum: DACSYNC + name: DACSYNC + - bit_offset: 27 + bit_size: 1 + description: Preload enable + enum: PREEN + name: PREEN + - bit_offset: 28 + bit_size: 4 + description: Update Gating + enum: UPDGAT + name: UPDGAT +fieldset/TIMEDIER: + description: TIMxDIER5 + fields: + - bit_offset: 0 + bit_size: 1 + description: CMP1IE + enum: CMP1IE + name: CMP1IE + - bit_offset: 1 + bit_size: 1 + description: CMP2IE + enum: CMP1IE + name: CMP2IE + - bit_offset: 2 + bit_size: 1 + description: CMP3IE + enum: CMP1IE + name: CMP3IE + - bit_offset: 3 + bit_size: 1 + description: CMP4IE + enum: CMP1IE + name: CMP4IE + - bit_offset: 4 + bit_size: 1 + description: REPIE + enum: REPIE + name: REPIE + - bit_offset: 6 + bit_size: 1 + description: UPDIE + enum: UPDIE + name: UPDIE + - bit_offset: 7 + bit_size: 1 + description: CPT1IE + enum: CPT1IE + name: CPT1IE + - bit_offset: 8 + bit_size: 1 + description: CPT2IE + enum: CPT1IE + name: CPT2IE + - bit_offset: 9 + bit_size: 1 + description: SET1xIE + enum: SETx1IE + name: SETx1IE + - bit_offset: 10 + bit_size: 1 + description: RSTx1IE + enum: RSTx1IE + name: RSTx1IE + - bit_offset: 11 + bit_size: 1 + description: SETx2IE + enum: SETx1IE + name: SETx2IE + - bit_offset: 12 + bit_size: 1 + description: RSTx2IE + enum: RSTx1IE + name: RSTx2IE + - bit_offset: 13 + bit_size: 1 + description: RSTIE + enum: RSTIE + name: RSTIE + - bit_offset: 14 + bit_size: 1 + description: DLYPRTIE + enum: DLYPRTIE + name: DLYPRTIE + - bit_offset: 16 + bit_size: 1 + description: CMP1DE + enum: CMP1DE + name: CMP1DE + - bit_offset: 17 + bit_size: 1 + description: CMP2DE + enum: CMP1DE + name: CMP2DE + - bit_offset: 18 + bit_size: 1 + description: CMP3DE + enum: CMP1DE + name: CMP3DE + - bit_offset: 19 + bit_size: 1 + description: CMP4DE + enum: CMP1DE + name: CMP4DE + - bit_offset: 20 + bit_size: 1 + description: REPDE + enum: REPDE + name: REPDE + - bit_offset: 22 + bit_size: 1 + description: UPDDE + enum: UPDDE + name: UPDDE + - bit_offset: 23 + bit_size: 1 + description: CPT1DE + enum: CPT1DE + name: CPT1DE + - bit_offset: 24 + bit_size: 1 + description: CPT2DE + enum: CPT1DE + name: CPT2DE + - bit_offset: 25 + bit_size: 1 + description: SET1xDE + enum: SETx1DE + name: SETx1DE + - bit_offset: 26 + bit_size: 1 + description: RSTx1DE + enum: RSTx1DE + name: RSTx1DE + - bit_offset: 27 + bit_size: 1 + description: SETx2DE + enum: SETx1DE + name: SETx2DE + - bit_offset: 28 + bit_size: 1 + description: RSTx2DE + enum: RSTx1DE + name: RSTx2DE + - bit_offset: 29 + bit_size: 1 + description: RSTDE + enum: RSTDE + name: RSTDE + - bit_offset: 30 + bit_size: 1 + description: DLYPRTDE + enum: DLYPRTDE + name: DLYPRTDE +fieldset/TIMEICR: + description: "Timerx Interrupt Clear\r Register" + fields: + - bit_offset: 0 + bit_size: 1 + description: "Compare 1 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP1C + - bit_offset: 1 + bit_size: 1 + description: "Compare 2 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP2C + - bit_offset: 2 + bit_size: 1 + description: "Compare 3 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP3C + - bit_offset: 3 + bit_size: 1 + description: "Compare 4 Interrupt flag\r Clear" + enum_write: CMP1C + name: CMP4C + - bit_offset: 4 + bit_size: 1 + description: "Repetition Interrupt flag\r Clear" + enum_write: CMP1C + name: REPC + - bit_offset: 6 + bit_size: 1 + description: "Update Interrupt flag\r Clear" + enum_write: CMP1C + name: UPDC + - bit_offset: 7 + bit_size: 1 + description: "Capture1 Interrupt flag\r Clear" + enum_write: CMP1C + name: CPT1C + - bit_offset: 8 + bit_size: 1 + description: "Capture2 Interrupt flag\r Clear" + enum_write: CMP1C + name: CPT2C + - bit_offset: 9 + bit_size: 1 + description: Output 1 Set flag Clear + enum_write: CMP1C + name: SET1xC + - bit_offset: 10 + bit_size: 1 + description: Output 1 Reset flag Clear + enum_write: CMP1C + name: RSTx1C + - bit_offset: 11 + bit_size: 1 + description: Output 2 Set flag Clear + enum_write: CMP1C + name: SET2xC + - bit_offset: 12 + bit_size: 1 + description: Output 2 Reset flag Clear + enum_write: CMP1C + name: RSTx2C + - bit_offset: 13 + bit_size: 1 + description: Reset Interrupt flag Clear + enum_write: CMP1C + name: RSTC + - bit_offset: 14 + bit_size: 1 + description: "Delayed Protection Flag\r Clear" + enum_write: CMP1C + name: DLYPRTC +fieldset/TIMEISR: + description: "Timerx Interrupt Status\r Register" + fields: + - bit_offset: 0 + bit_size: 1 + description: Compare 1 Interrupt Flag + enum_read: TIMEISR_CMP1 + name: CMP1 + - bit_offset: 1 + bit_size: 1 + description: Compare 2 Interrupt Flag + enum_read: TIMEISR_CMP1 + name: CMP2 + - bit_offset: 2 + bit_size: 1 + description: Compare 3 Interrupt Flag + enum_read: TIMEISR_CMP1 + name: CMP3 + - bit_offset: 3 + bit_size: 1 + description: Compare 4 Interrupt Flag + enum_read: TIMEISR_CMP1 + name: CMP4 + - bit_offset: 4 + bit_size: 1 + description: Repetition Interrupt Flag + enum_read: REP + name: REP + - bit_offset: 6 + bit_size: 1 + description: Update Interrupt Flag + enum_read: UPD + name: UPD + - bit_offset: 7 + bit_size: 1 + description: Capture1 Interrupt Flag + enum_read: CPT1 + name: CPT1 + - bit_offset: 8 + bit_size: 1 + description: Capture2 Interrupt Flag + enum_read: CPT1 + name: CPT2 + - bit_offset: 9 + bit_size: 1 + description: "Output 1 Set Interrupt\r Flag" + enum_read: SETx1 + name: SETx1 + - bit_offset: 10 + bit_size: 1 + description: "Output 1 Reset Interrupt\r Flag" + enum_read: RSTx1 + name: RSTx1 + - bit_offset: 11 + bit_size: 1 + description: "Output 2 Set Interrupt\r Flag" + enum_read: SETx1 + name: SETx2 + - bit_offset: 12 + bit_size: 1 + description: "Output 2 Reset Interrupt\r Flag" + enum_read: RSTx1 + name: RSTx2 + - bit_offset: 13 + bit_size: 1 + description: Reset Interrupt Flag + enum_read: RST + name: RST + - bit_offset: 14 + bit_size: 1 + description: Delayed Protection Flag + enum_read: TIMEISR_DLYPRT + name: DLYPRT + - bit_offset: 16 + bit_size: 1 + description: Current Push Pull Status + enum_read: CPPSTAT + name: CPPSTAT + - bit_offset: 17 + bit_size: 1 + description: Idle Push Pull Status + enum_read: IPPSTAT + name: IPPSTAT + - bit_offset: 18 + bit_size: 1 + description: Output 1 State + enum_read: O1STAT + name: O1STAT + - bit_offset: 19 + bit_size: 1 + description: Output 2 State + enum_read: O1STAT + name: O2STAT + - bit_offset: 20 + bit_size: 1 + description: Output 1 Copy + enum_read: O1CPY + name: O1CPY + - bit_offset: 21 + bit_size: 1 + description: Output 2 Copy + enum_read: O1CPY + name: O2CPY diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index eddefa6..15bbbfa 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -198,6 +198,7 @@ impl PeriMatcher { (".*:WWDG:wwdg1_v1_0", ("wwdg", "v1", "WWDG")), (".*:JPEG:jpeg1_v1_0", ("jpeg", "v1", "JPEG")), (".*:LPTIM:F7_lptimer1_v1_1", ("lptim", "v1", "LPTIM")), + (".*:HRTIM:hrtim_v1_0", ("hrtim", "v1", "HRTIM")), (".*:LTDC:lcdtft1_v1_1", ("ltdc", "v1", "LTDC")), (".*:MDIOS:mdios1_v1_0", ("mdios", "v1", "MDIOS")), (".*:QUADSPI:quadspi1_v1_0", ("quadspi", "v1", "QUADSPI")),