From 53c636386bcffcf5a6172151277d5eab48a03b5e Mon Sep 17 00:00:00 2001 From: JackN Date: Fri, 13 Oct 2023 16:55:44 -0400 Subject: [PATCH] GFXMMU: New peripheral yamls --- data/registers/gfxmmu_v1.yaml | 141 ++++++++++++++++++++++++ data/registers/gfxmmu_v2.yaml | 200 ++++++++++++++++++++++++++++++++++ 2 files changed, 341 insertions(+) create mode 100644 data/registers/gfxmmu_v1.yaml create mode 100644 data/registers/gfxmmu_v2.yaml diff --git a/data/registers/gfxmmu_v1.yaml b/data/registers/gfxmmu_v1.yaml new file mode 100644 index 0000000..91c0bfe --- /dev/null +++ b/data/registers/gfxmmu_v1.yaml @@ -0,0 +1,141 @@ +block/GFXMMU: + description: GFXMMU. + items: + - name: CR + description: GFXMMU configuration register. + byte_offset: 0 + fieldset: CR + - name: SR + description: GFXMMU status register. + byte_offset: 4 + access: Read + fieldset: SR + - name: FCR + description: GFXMMU flag clear register. + byte_offset: 8 + access: Write + fieldset: FCR + - name: DVR + description: GFXMMU default value register. + byte_offset: 16 + fieldset: DVR + - name: BCR + description: GFXMMU buffer 0 configuration register. + array: + len: 4 + stride: 4 + byte_offset: 32 + fieldset: BCR + - name: LUTL + description: GFXMMU LUT entry 0 low. + array: + len: 1024 + stride: 8 + byte_offset: 4096 + fieldset: LUTL + - name: LUTH + description: GFXMMU LUT entry 0 high. + array: + len: 1024 + stride: 8 + byte_offset: 4100 + fieldset: LUTH +fieldset/BCR: + description: GFXMMU buffer configuration register. + fields: + - name: PBO + description: Physical buffer offset. Offset of the physical buffer. + bit_offset: 4 + bit_size: 19 + - name: PBBA + description: Physical buffer base address. Base address MSB of the physical buffer. + bit_offset: 23 + bit_size: 9 +fieldset/CR: + description: GFXMMU configuration register. + fields: + - name: BOIE + description: Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt. + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: AMEIE + description: AHB master error interrupt enable. This bit enables the AHB master error interrupt. + bit_offset: 4 + bit_size: 1 + - name: BM + description: 192 Block mode. This bit defines the number of blocks per line. + bit_offset: 6 + bit_size: 1 + array: + len: 1 + stride: 0 + enum: BM192 +fieldset/DVR: + description: GFXMMU default value register. + fields: + - name: DV + description: Default value. This field indicates the default 32-bit value which is returned when a master accesses a virtual memory location not physically mapped. + bit_offset: 0 + bit_size: 32 +fieldset/FCR: + description: GFXMMU flag clear register. + fields: + - name: CBOF + description: Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register. + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: CAMEF + description: Clear AHB master error flag. Writing 1 clears the AHB master error flag in the GFXMMU_SR register. + bit_offset: 4 + bit_size: 1 +fieldset/LUTH: + description: GFXMMU LUT entry high. + fields: + - name: LO + description: Line offset. Line offset of line number x (i.e. offset of block 0 of line x). + bit_offset: 4 + bit_size: 18 +fieldset/LUTL: + description: GFXMMU LUT entry low. + fields: + - name: EN + description: Line enable. + bit_offset: 0 + bit_size: 1 + - name: FVB + description: First Valid Block. Number of the first valid block of line number x. + bit_offset: 8 + bit_size: 8 + - name: LVB + description: Last Valid Block. Number of the last valid block of line number X. + bit_offset: 16 + bit_size: 8 +fieldset/SR: + description: GFXMMU status register. + fields: + - name: BOF + description: Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF. + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: AMEF + description: AHB master error flag. This bit is set when an AHB error happens during a transaction. It is cleared by writing 1 to CAMEF. + bit_offset: 4 + bit_size: 1 +enum/BM192: + bit_size: 1 + variants: + - name: 256BlocksPerLine + description: 256 blocks per line. + value: 0 + - name: 192BlocksPerLine + description: 192 blocks per line. + value: 1 diff --git a/data/registers/gfxmmu_v2.yaml b/data/registers/gfxmmu_v2.yaml new file mode 100644 index 0000000..9d39281 --- /dev/null +++ b/data/registers/gfxmmu_v2.yaml @@ -0,0 +1,200 @@ +block/GFXMMU: + description: GFXMMU. + items: + - name: CR + description: GFXMMU configuration register. + byte_offset: 0 + fieldset: CR + - name: SR + description: GFXMMU status register. + byte_offset: 4 + access: Read + fieldset: SR + - name: FCR + description: GFXMMU flag clear register. + byte_offset: 8 + access: Write + fieldset: FCR + - name: CCR + description: GFXMMU cache control register. + byte_offset: 12 + fieldset: CCR + - name: DVR + description: GFXMMU default value register. + byte_offset: 16 + fieldset: DVR + - name: BCR + description: GFXMMU buffer 0 configuration register. + array: + len: 4 + stride: 4 + byte_offset: 32 + fieldset: BCR + - name: LUTL + description: GFXMMU LUT entry 0 low. + array: + len: 1024 + stride: 8 + byte_offset: 4096 + fieldset: LUTL + - name: LUTH + description: GFXMMU LUT entry 0 high. + array: + len: 1024 + stride: 8 + byte_offset: 4100 + fieldset: LUTH +fieldset/BCR: + description: GFXMMU buffer configuration register. + fields: + - name: PBO + description: Physical buffer offset. Offset of the physical buffer. + bit_offset: 4 + bit_size: 19 + - name: PBBA + description: Physical buffer base address. Base address MSB of the physical buffer. + bit_offset: 23 + bit_size: 9 +fieldset/CCR: + description: GFXMMU cache control register. + fields: + - name: FF + description: Force flush. When set, the cache entries are flushed. This bit is reset by hardware when the flushing is complete. Write 0 has no effect. + bit_offset: 0 + bit_size: 1 + - name: FI + description: Force invalidate. When set, the cache entries are invalidated. This bit is reset by hardware when the invalidation is complete. Write 0 has no effect. + bit_offset: 1 + bit_size: 1 +fieldset/CR: + description: GFXMMU configuration register. + fields: + - name: BOIE + description: Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt. + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: AMEIE + description: AHB master error interrupt enable. This bit enables the AHB master error interrupt. + bit_offset: 4 + bit_size: 1 + - name: BM + description: 192 Block mode. This bit defines the number of blocks per line. + bit_offset: 6 + bit_size: 1 + array: + len: 1 + stride: 0 + enum: BM192 + - name: CE + description: Cache enable. This bit enables the cache unit. + bit_offset: 7 + bit_size: 1 + - name: CL + description: Cache lock. This bit lock the cache onto the buffer defined in the CLB field. + bit_offset: 8 + bit_size: 1 + - name: CLB + description: Cache lock buffer. This field select the buffer on which the cache is locked. + bit_offset: 9 + bit_size: 2 + enum: CLB + - name: FC + description: Force caching. This bit force the caching into the cache regardless of the MPU attributes. The cache must be enable (CE bit set). + bit_offset: 11 + bit_size: 1 + - name: PD + description: Prefetch disable. This bit disables the prefetch of the cache. + bit_offset: 12 + bit_size: 1 + - name: OC + description: Outter cachability. This bit configure the cachability of an access generated by the GFXMMU cache. + bit_offset: 16 + bit_size: 1 + - name: OB + description: Outter bufferability. This bit configure the bufferability of an access generated by the GFXMMU cache. + bit_offset: 17 + bit_size: 1 +fieldset/DVR: + description: GFXMMU default value register. + fields: + - name: DV + description: Default value. This field indicates the default 32-bit value which is returned when a master accesses a virtual memory location not physically mapped. + bit_offset: 0 + bit_size: 32 +fieldset/FCR: + description: GFXMMU flag clear register. + fields: + - name: CBOF + description: Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register. + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: CAMEF + description: Clear AHB master error flag. Writing 1 clears the AHB master error flag in the GFXMMU_SR register. + bit_offset: 4 + bit_size: 1 +fieldset/LUTH: + description: GFXMMU LUT entry high. + fields: + - name: LO + description: Line offset. Line offset of line number x (i.e. offset of block 0 of line x). + bit_offset: 4 + bit_size: 18 +fieldset/LUTL: + description: GFXMMU LUT entry low. + fields: + - name: EN + description: Line enable. + bit_offset: 0 + bit_size: 1 + - name: FVB + description: First Valid Block. Number of the first valid block of line number x. + bit_offset: 8 + bit_size: 8 + - name: LVB + description: Last Valid Block. Number of the last valid block of line number X. + bit_offset: 16 + bit_size: 8 +fieldset/SR: + description: GFXMMU status register. + fields: + - name: BOF + description: Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF. + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: AMEF + description: AHB master error flag. This bit is set when an AHB error happens during a transaction. It is cleared by writing 1 to CAMEF. + bit_offset: 4 + bit_size: 1 +enum/BM192: + bit_size: 1 + variants: + - name: 256BlocksPerLine + description: 256 blocks per line. + value: 0 + - name: 192BlocksPerLine + description: 192 blocks per line. + value: 1 +enum/CLB: + bit_size: 2 + variants: + - name: LockedOnBuffer0 + description: Cache locked on buffer 0. + value: 0 + - name: LockedOnBuffer1 + description: Cache locked on buffer 1. + value: 1 + - name: LockedOnBuffer2 + description: Cache locked on buffer 2. + value: 2 + - name: LockedOnBuffer3 + description: Cache locked on buffer 3. + value: 3