From 5365ea053a0398ee0702512d5894bd81d15af07c Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Mon, 7 Feb 2022 22:45:00 +0100 Subject: [PATCH] split "magic" block string into an object, so consumers don't have to do tricky parsing. --- data/extra/family/STM32L4+.yaml | 5 +- data/extra/family/STM32L4.yaml | 5 +- data/extra/family/STM32WB.yaml | 5 +- stm32data/__main__.py | 373 ++++++++++++++++---------------- 4 files changed, 201 insertions(+), 187 deletions(-) diff --git a/data/extra/family/STM32L4+.yaml b/data/extra/family/STM32L4+.yaml index 8c58ebd..7275af6 100644 --- a/data/extra/family/STM32L4+.yaml +++ b/data/extra/family/STM32L4+.yaml @@ -2,4 +2,7 @@ peripherals: - name: VREFINTCAL address: 0x1FFF75AA - block: vrefintcal_v1/VREFINTCAL + registers: + kind: vrefintcal + version: v1 + block: VREFINTCAL diff --git a/data/extra/family/STM32L4.yaml b/data/extra/family/STM32L4.yaml index 8c58ebd..7275af6 100644 --- a/data/extra/family/STM32L4.yaml +++ b/data/extra/family/STM32L4.yaml @@ -2,4 +2,7 @@ peripherals: - name: VREFINTCAL address: 0x1FFF75AA - block: vrefintcal_v1/VREFINTCAL + registers: + kind: vrefintcal + version: v1 + block: VREFINTCAL diff --git a/data/extra/family/STM32WB.yaml b/data/extra/family/STM32WB.yaml index 8c58ebd..7275af6 100644 --- a/data/extra/family/STM32WB.yaml +++ b/data/extra/family/STM32WB.yaml @@ -2,4 +2,7 @@ peripherals: - name: VREFINTCAL address: 0x1FFF75AA - block: vrefintcal_v1/VREFINTCAL + registers: + kind: vrefintcal + version: v1 + block: VREFINTCAL diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 1482e63..755e5df 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -2,7 +2,7 @@ import sys import xmltodict - +import functools import re import json import os @@ -80,206 +80,206 @@ FAKE_PERIPHERALS = [ ] perimap = [ - ('.*:USART:sci2_v1_1', 'usart_v1/USART'), - ('.*:USART:sci2_v1_2_F1', 'usart_v1/USART'), - ('.*:USART:sci2_v1_2', 'usart_v1/USART'), - ('.*:USART:sci2_v2_0', 'usart_v2/USART'), - ('.*:USART:sci2_v2_1', 'usart_v2/USART'), - ('.*:USART:sci2_v2_2', 'usart_v2/USART'), - ('.*:USART:sci3_v1_0', 'usart_v2/USART'), - ('.*:USART:sci3_v1_1', 'usart_v2/USART'), - ('.*:USART:sci3_v1_2', 'usart_v2/USART'), - ('.*:USART:sci3_v2_0', 'usart_v2/USART'), - ('.*:USART:sci3_v2_1', 'usart_v2/USART'), - ('.*:UART:sci2_v2_1', 'usart_v2/USART'), - ('.*:UART:sci2_v3_0', 'usart_v2/USART'), - ('.*:UART:sci2_v3_1', 'usart_v2/USART'), - ('.*:LPUART:sci3_v1_1', 'lpuart_v1/LPUART'), - ('.*:LPUART:sci3_v1_2', 'lpuart_v2/LPUART'), - ('.*:LPUART:sci3_v1_3', 'lpuart_v2/LPUART'), - ('.*:LPUART:sci3_v1_4', 'lpuart_v2/LPUART'), - ('.*:RNG:rng1_v1_1', 'rng_v1/RNG'), - ('.*:RNG:rng1_v2_0', 'rng_v1/RNG'), - ('.*:RNG:rng1_v2_1', 'rng_v1/RNG'), - ('.*:RNG:rng1_v3_1', 'rng_v1/RNG'), - ('.*:SPI:spi2_v1_4', 'spi_f1/SPI'), - ('.*:SPI:spi2s1_v2_2', 'spi_v1/SPI'), - ('.*:SPI:spi2s1_v3_2', 'spi_v2/SPI'), - ('.*:SPI:spi2s1_v3_3', 'spi_v2/SPI'), - ('.*:SPI:spi2s1_v3_5', 'spi_v2/SPI'), - ('.*:SUBGHZSPI:.*', 'spi_v2/SPI'), - ('.*:SPI:spi2s1_v3_1', 'spi_v2/SPI'), - ('.*:SPI:spi2s2_v1_1', 'spi_v3/SPI'), - ('.*:SPI:spi2s2_v1_0', 'spi_v3/SPI'), - ('.*:I2C:i2c1_v1_5', 'i2c_v1/I2C'), - ('.*:I2C:i2c2_v1_1', 'i2c_v2/I2C'), - ('.*:I2C:i2c2_v1_1F7', 'i2c_v2/I2C'), - ('.*:I2C:i2c2_v1_1U5', 'i2c_v2/I2C'), - ('.*:DAC:dacif_v1_1', 'dac_v1/DAC'), - ('.*:DAC:dacif_v2_0', 'dac_v2/DAC'), - ('.*:DAC:dacif_v3_0', 'dac_v2/DAC'), - ('.*:ADC:aditf_v2_5F1', 'adc_f1/ADC'), - ('.*:ADC:aditf2_v1_1', 'adc_v2/ADC'), - ('.*:ADC:aditf5_v2_0', 'adc_v3/ADC'), - ('STM32G0.*:ADC:.*', 'adc_g0/ADC'), - ('STM32G0.*:ADC_COMMON:.*', 'adccommon_v3/ADC_COMMON'), - ('.*:ADC_COMMON:aditf2_v1_1', 'adccommon_v2/ADC_COMMON'), - ('.*:ADC_COMMON:aditf5_v2_0', 'adccommon_v3/ADC_COMMON'), - ('.*:ADC_COMMON:aditf4_v3_0_WL', 'adccommon_v3/ADC_COMMON'), - ('.*:DCMI:.*', 'dcmi_v1/DCMI'), - ('STM32F0.*:SYSCFG:.*', 'syscfg_f0/SYSCFG'), - ('STM32F3.*:SYSCFG:.*', 'syscfg_f3/SYSCFG'), - ('STM32F4.*:SYSCFG:.*', 'syscfg_f4/SYSCFG'), - ('STM32F7.*:SYSCFG:.*', 'syscfg_f7/SYSCFG'), - ('STM32L4.*:SYSCFG:.*', 'syscfg_l4/SYSCFG'), - ('STM32L0.*:SYSCFG:.*', 'syscfg_l0/SYSCFG'), - ('STM32L1.*:SYSCFG:.*', 'syscfg_l1/SYSCFG'), - ('STM32G0.*:SYSCFG:.*', 'syscfg_g0/SYSCFG'), - ('STM32G4.*:SYSCFG:.*', 'syscfg_g4/SYSCFG'), - ('STM32H7.*:SYSCFG:.*', 'syscfg_h7/SYSCFG'), - ('STM32U5.*:SYSCFG:.*', 'syscfg_u5/SYSCFG'), - ('STM32WB.*:SYSCFG:.*', 'syscfg_wb/SYSCFG'), - ('STM32WL5.*:SYSCFG:.*', 'syscfg_wl5/SYSCFG'), - ('STM32WLE.*:SYSCFG:.*', 'syscfg_wle/SYSCFG'), + ('.*:USART:sci2_v1_1', ('usart', 'v1', 'USART')), + ('.*:USART:sci2_v1_2_F1', ('usart', 'v1', 'USART')), + ('.*:USART:sci2_v1_2', ('usart', 'v1', 'USART')), + ('.*:USART:sci2_v2_0', ('usart', 'v2', 'USART')), + ('.*:USART:sci2_v2_1', ('usart', 'v2', 'USART')), + ('.*:USART:sci2_v2_2', ('usart', 'v2', 'USART')), + ('.*:USART:sci3_v1_0', ('usart', 'v2', 'USART')), + ('.*:USART:sci3_v1_1', ('usart', 'v2', 'USART')), + ('.*:USART:sci3_v1_2', ('usart', 'v2', 'USART')), + ('.*:USART:sci3_v2_0', ('usart', 'v2', 'USART')), + ('.*:USART:sci3_v2_1', ('usart', 'v2', 'USART')), + ('.*:UART:sci2_v2_1', ('usart', 'v2', 'USART')), + ('.*:UART:sci2_v3_0', ('usart', 'v2', 'USART')), + ('.*:UART:sci2_v3_1', ('usart', 'v2', 'USART')), + ('.*:LPUART:sci3_v1_1', ('lpuart', 'v1', 'LPUART')), + ('.*:LPUART:sci3_v1_2', ('lpuart', 'v2', 'LPUART')), + ('.*:LPUART:sci3_v1_3', ('lpuart', 'v2', 'LPUART')), + ('.*:LPUART:sci3_v1_4', ('lpuart', 'v2', 'LPUART')), + ('.*:RNG:rng1_v1_1', ('rng', 'v1', 'RNG')), + ('.*:RNG:rng1_v2_0', ('rng', 'v1', 'RNG')), + ('.*:RNG:rng1_v2_1', ('rng', 'v1', 'RNG')), + ('.*:RNG:rng1_v3_1', ('rng', 'v1', 'RNG')), + ('.*:SPI:spi2_v1_4', ('spi', 'f1', 'SPI')), + ('.*:SPI:spi2s1_v2_2', ('spi', 'v1', 'SPI')), + ('.*:SPI:spi2s1_v3_2', ('spi', 'v2', 'SPI')), + ('.*:SPI:spi2s1_v3_3', ('spi', 'v2', 'SPI')), + ('.*:SPI:spi2s1_v3_5', ('spi', 'v2', 'SPI')), + ('.*:SUBGHZSPI:.*', ('spi', 'v2', 'SPI')), + ('.*:SPI:spi2s1_v3_1', ('spi', 'v2', 'SPI')), + ('.*:SPI:spi2s2_v1_1', ('spi', 'v3', 'SPI')), + ('.*:SPI:spi2s2_v1_0', ('spi', 'v3', 'SPI')), + ('.*:I2C:i2c1_v1_5', ('i2c', 'v1', 'I2C')), + ('.*:I2C:i2c2_v1_1', ('i2c', 'v2', 'I2C')), + ('.*:I2C:i2c2_v1_1F7', ('i2c', 'v2', 'I2C')), + ('.*:I2C:i2c2_v1_1U5', ('i2c', 'v2', 'I2C')), + ('.*:DAC:dacif_v1_1', ('dac', 'v1', 'DAC')), + ('.*:DAC:dacif_v2_0', ('dac', 'v2', 'DAC')), + ('.*:DAC:dacif_v3_0', ('dac', 'v2', 'DAC')), + ('.*:ADC:aditf_v2_5F1', ('adc', 'f1', 'ADC')), + ('.*:ADC:aditf2_v1_1', ('adc', 'v2', 'ADC')), + ('.*:ADC:aditf5_v2_0', ('adc', 'v3', 'ADC')), + ('STM32G0.*:ADC:.*', ('adc', 'g0', 'ADC')), + ('STM32G0.*:ADC_COMMON:.*', ('adccommon', 'v3', 'ADC_COMMON')), + ('.*:ADC_COMMON:aditf2_v1_1', ('adccommon', 'v2', 'ADC_COMMON')), + ('.*:ADC_COMMON:aditf5_v2_0', ('adccommon', 'v3', 'ADC_COMMON')), + ('.*:ADC_COMMON:aditf4_v3_0_WL', ('adccommon', 'v3', 'ADC_COMMON')), + ('.*:DCMI:.*', ('dcmi', 'v1', 'DCMI')), + ('STM32F0.*:SYSCFG:.*', ('syscfg', 'f0', 'SYSCFG')), + ('STM32F3.*:SYSCFG:.*', ('syscfg', 'f3', 'SYSCFG')), + ('STM32F4.*:SYSCFG:.*', ('syscfg', 'f4', 'SYSCFG')), + ('STM32F7.*:SYSCFG:.*', ('syscfg', 'f7', 'SYSCFG')), + ('STM32L4.*:SYSCFG:.*', ('syscfg', 'l4', 'SYSCFG')), + ('STM32L0.*:SYSCFG:.*', ('syscfg', 'l0', 'SYSCFG')), + ('STM32L1.*:SYSCFG:.*', ('syscfg', 'l1', 'SYSCFG')), + ('STM32G0.*:SYSCFG:.*', ('syscfg', 'g0', 'SYSCFG')), + ('STM32G4.*:SYSCFG:.*', ('syscfg', 'g4', 'SYSCFG')), + ('STM32H7.*:SYSCFG:.*', ('syscfg', 'h7', 'SYSCFG')), + ('STM32U5.*:SYSCFG:.*', ('syscfg', 'u5', 'SYSCFG')), + ('STM32WB.*:SYSCFG:.*', ('syscfg', 'wb', 'SYSCFG')), + ('STM32WL5.*:SYSCFG:.*', ('syscfg', 'wl5', 'SYSCFG')), + ('STM32WLE.*:SYSCFG:.*', ('syscfg', 'wle', 'SYSCFG')), - ('.*:IWDG:iwdg1_v2_0', 'iwdg_v2/IWDG'), - ('.*:WWDG:wwdg1_v1_0', 'wwdg_v1/WWDG'), - ('.*:JPEG:jpeg1_v1_0', 'jpeg_v1/JPEG'), - ('.*:LPTIM:F7_lptimer1_v1_1', 'lptim_v1/LPTIM'), - ('.*:LTDC:lcdtft1_v1_1', 'ltdc_v1/LTDC'), - ('.*:MDIOS:mdios1_v1_0', 'mdios_v1/MDIOS'), - ('.*:QUADSPI:quadspi1_v1_0', 'quadspi_v1/QUADSPI'), - ('.*:RTC:rtc2_v2_6', 'rtc_v2/RTC'), - ('.*:RTC:rtc2_v2_WB', 'rtc_wb/RTC'), - ('.*:SAI:sai1_v1_1', 'sai_v1/SAI'), - ('.*:SDMMC:sdmmc_v1_3', 'sdmmc_v1/SDMMC'), - ('.*:SPDIFRX:spdifrx1_v1_0', 'spdifrx_v1/SPDIFRX'), - ('.*:USB_OTG_FS:otgfs1_v1_2', 'otgfs_v1/OTG_FS'), - ('.*:USB_OTG_HS:otghs1_v1_1', 'otghs_v1/OTG_HS'), + ('.*:IWDG:iwdg1_v2_0', ('iwdg', 'v2', 'IWDG')), + ('.*:WWDG:wwdg1_v1_0', ('wwdg', 'v1', 'WWDG')), + ('.*:JPEG:jpeg1_v1_0', ('jpeg', 'v1', 'JPEG')), + ('.*:LPTIM:F7_lptimer1_v1_1', ('lptim', 'v1', 'LPTIM')), + ('.*:LTDC:lcdtft1_v1_1', ('ltdc', 'v1', 'LTDC')), + ('.*:MDIOS:mdios1_v1_0', ('mdios', 'v1', 'MDIOS')), + ('.*:QUADSPI:quadspi1_v1_0', ('quadspi', 'v1', 'QUADSPI')), + ('.*:RTC:rtc2_v2_6', ('rtc', 'v2', 'RTC')), + ('.*:RTC:rtc2_v2_WB', ('rtc', 'wb', 'RTC')), + ('.*:SAI:sai1_v1_1', ('sai', 'v1', 'SAI')), + ('.*:SDMMC:sdmmc_v1_3', ('sdmmc', 'v1', 'SDMMC')), + ('.*:SPDIFRX:spdifrx1_v1_0', ('spdifrx', 'v1', 'SPDIFRX')), + ('.*:USB_OTG_FS:otgfs1_v1_2', ('otgfs', 'v1', 'OTG_FS')), + ('.*:USB_OTG_HS:otghs1_v1_1', ('otghs', 'v1', 'OTG_HS')), - ('STM32F0.0.*:RCC:.*', 'rcc_f0x0/RCC'), - ('STM32F0.*:RCC:.*', 'rcc_f0/RCC'), - ('STM32F1.*:RCC:.*', 'rcc_f1/RCC'), - ('STM32F2.*:RCC:.*', 'rcc_f2/RCC'), - ('STM32F3.*:RCC:.*', 'rcc_f3/RCC'), - ('STM32F410.*:RCC:.*', 'rcc_f410/RCC'), - ('STM32F4.*:RCC:.*', 'rcc_f4/RCC'), - ('STM32F7.*:RCC:.*', 'rcc_f7/RCC'), - ('STM32G0.*:RCC:.*', 'rcc_g0/RCC'), - ('STM32G4.*:RCC:.*', 'rcc_g4/RCC'), - ('STM32H7[AB].*:RCC:.*', 'rcc_h7ab/RCC'), - ('STM32H7.*:RCC:.*', 'rcc_h7/RCC'), - ('STM32L0.*:RCC:.*', 'rcc_l0/RCC'), - ('STM32L1.*:RCC:.*', 'rcc_l1/RCC'), - ('STM32L4.*:RCC:.*', 'rcc_l4/RCC'), - ('STM32L5.*:RCC:.*', 'rcc_l5/RCC'), - ('STM32U5.*:RCC:.*', 'rcc_u5/RCC'), - ('STM32WB.*:RCC:.*', 'rcc_wb/RCC'), - ('STM32WL5.*:RCC:.*', 'rcc_wl5/RCC'), - ('STM32WLE.*:RCC:.*', 'rcc_wle/RCC'), + ('STM32F0.0.*:RCC:.*', ('rcc', 'f0x0', 'RCC')), + ('STM32F0.*:RCC:.*', ('rcc', 'f0', 'RCC')), + ('STM32F1.*:RCC:.*', ('rcc', 'f1', 'RCC')), + ('STM32F2.*:RCC:.*', ('rcc', 'f2', 'RCC')), + ('STM32F3.*:RCC:.*', ('rcc', 'f3', 'RCC')), + ('STM32F410.*:RCC:.*', ('rcc', 'f410', 'RCC')), + ('STM32F4.*:RCC:.*', ('rcc', 'f4', 'RCC')), + ('STM32F7.*:RCC:.*', ('rcc', 'f7', 'RCC')), + ('STM32G0.*:RCC:.*', ('rcc', 'g0', 'RCC')), + ('STM32G4.*:RCC:.*', ('rcc', 'g4', 'RCC')), + ('STM32H7[AB].*:RCC:.*', ('rcc', 'h7ab', 'RCC')), + ('STM32H7.*:RCC:.*', ('rcc', 'h7', 'RCC')), + ('STM32L0.*:RCC:.*', ('rcc', 'l0', 'RCC')), + ('STM32L1.*:RCC:.*', ('rcc', 'l1', 'RCC')), + ('STM32L4.*:RCC:.*', ('rcc', 'l4', 'RCC')), + ('STM32L5.*:RCC:.*', ('rcc', 'l5', 'RCC')), + ('STM32U5.*:RCC:.*', ('rcc', 'u5', 'RCC')), + ('STM32WB.*:RCC:.*', ('rcc', 'wb', 'RCC')), + ('STM32WL5.*:RCC:.*', ('rcc', 'wl5', 'RCC')), + ('STM32WLE.*:RCC:.*', ('rcc', 'wle', 'RCC')), - ('STM32F3.*:SPI[1234]:.*', 'spi_v2/SPI'), + ('STM32F3.*:SPI[1234]:.*', ('spi', 'v2', 'SPI')), - ('STM32F1.*:AFIO:.*', 'afio_f1/AFIO'), + ('STM32F1.*:AFIO:.*', ('afio', 'f1', 'AFIO')), - ('STM32L5.*:EXTI:.*', 'exti_l5/EXTI'), - ('STM32G0.*:EXTI:.*', 'exti_g0/EXTI'), - ('STM32H7.*:EXTI:.*', 'exti_h7/EXTI'), - ('STM32U5.*:EXTI:.*', 'exti_u5/EXTI'), - ('STM32WB.*:EXTI:.*', 'exti_w/EXTI'), - ('STM32WL5.*:EXTI:.*', 'exti_w/EXTI'), - ('STM32WLE.*:EXTI:.*', 'exti_wle/EXTI'), - ('.*:EXTI:.*', 'exti_v1/EXTI'), + ('STM32L5.*:EXTI:.*', ('exti', 'l5', 'EXTI')), + ('STM32G0.*:EXTI:.*', ('exti', 'g0', 'EXTI')), + ('STM32H7.*:EXTI:.*', ('exti', 'h7', 'EXTI')), + ('STM32U5.*:EXTI:.*', ('exti', 'u5', 'EXTI')), + ('STM32WB.*:EXTI:.*', ('exti', 'w', 'EXTI')), + ('STM32WL5.*:EXTI:.*', ('exti', 'w', 'EXTI')), + ('STM32WLE.*:EXTI:.*', ('exti', 'wle', 'EXTI')), + ('.*:EXTI:.*', ('exti', 'v1', 'EXTI')), - ('STM32L0.*:CRS:.*', 'crs_l0/CRS'), - ('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'), - ('STM32G0.*:PWR:.*', 'pwr_g0/PWR'), - ('STM32G4.*:PWR:.*', 'pwr_g4/PWR'), - ('STM32H7(42|43|53|50).*:PWR:.*', 'pwr_h7/PWR'), - ('STM32H7.*:PWR:.*', 'pwr_h7smps/PWR'), - ('STM32F3.*:PWR:.*', 'pwr_f3/PWR'), - ('STM32F4.*:PWR:.*', 'pwr_f4/PWR'), - ('STM32F7.*:PWR:.*', 'pwr_f7/PWR'), - ('STM32L1.*:PWR:.*', 'pwr_l1/PWR'), - ('STM32U5.*:PWR:.*', 'pwr_u5/PWR'), - ('STM32WL.*:PWR:.*', 'pwr_wl5/PWR'), - ('STM32WB.*:PWR:.*', 'pwr_wb55/PWR'), - ('STM32H7.*:FLASH:.*', 'flash_h7/FLASH'), - ('STM32F0.*:FLASH:.*', 'flash_f0/FLASH'), - ('STM32F1.*:FLASH:.*', 'flash_f1/FLASH'), - ('STM32F3.*:FLASH:.*', 'flash_f3/FLASH'), - ('STM32F4.*:FLASH:.*', 'flash_f4/FLASH'), - ('STM32F7.*:FLASH:.*', 'flash_f7/FLASH'), - ('STM32L1.*:FLASH:.*', 'flash_l1/FLASH'), - ('STM32L4.*:FLASH:.*', 'flash_l4/FLASH'), - ('STM32U5.*:FLASH:.*', 'flash_u5/FLASH'), - ('STM32WB.*:FLASH:.*', 'flash_wb55/FLASH'), - ('STM32F7.*:ETH:ETH:ethermac110_v2_0', 'eth_v1c/ETH'), - ('.*ETH:ethermac110_v3_0', 'eth_v2/ETH'), + ('STM32L0.*:CRS:.*', ('crs', 'l0', 'CRS')), + ('.*SDMMC:sdmmc2_v1_0', ('sdmmc', 'v2', 'SDMMC')), + ('STM32G0.*:PWR:.*', ('pwr', 'g0', 'PWR')), + ('STM32G4.*:PWR:.*', ('pwr', 'g4', 'PWR')), + ('STM32H7(42|43|53|50).*:PWR:.*', ('pwr', 'h7', 'PWR')), + ('STM32H7.*:PWR:.*', ('pwr', 'h7smps', 'PWR')), + ('STM32F3.*:PWR:.*', ('pwr', 'f3', 'PWR')), + ('STM32F4.*:PWR:.*', ('pwr', 'f4', 'PWR')), + ('STM32F7.*:PWR:.*', ('pwr', 'f7', 'PWR')), + ('STM32L1.*:PWR:.*', ('pwr', 'l1', 'PWR')), + ('STM32U5.*:PWR:.*', ('pwr', 'u5', 'PWR')), + ('STM32WL.*:PWR:.*', ('pwr', 'wl5', 'PWR')), + ('STM32WB.*:PWR:.*', ('pwr', 'wb55', 'PWR')), + ('STM32H7.*:FLASH:.*', ('flash', 'h7', 'FLASH')), + ('STM32F0.*:FLASH:.*', ('flash', 'f0', 'FLASH')), + ('STM32F1.*:FLASH:.*', ('flash', 'f1', 'FLASH')), + ('STM32F3.*:FLASH:.*', ('flash', 'f3', 'FLASH')), + ('STM32F4.*:FLASH:.*', ('flash', 'f4', 'FLASH')), + ('STM32F7.*:FLASH:.*', ('flash', 'f7', 'FLASH')), + ('STM32L1.*:FLASH:.*', ('flash', 'l1', 'FLASH')), + ('STM32L4.*:FLASH:.*', ('flash', 'l4', 'FLASH')), + ('STM32U5.*:FLASH:.*', ('flash', 'u5', 'FLASH')), + ('STM32WB.*:FLASH:.*', ('flash', 'wb55', 'FLASH')), + ('STM32F7.*:ETH:ETH:ethermac110_v2_0', ('eth', 'v1c', 'ETH')), + ('.*ETH:ethermac110_v3_0', ('eth', 'v2', 'ETH')), - ('STM32H7.*:FMC:.*', 'fmc_h7/FMC'), + ('STM32H7.*:FMC:.*', ('fmc', 'h7', 'FMC')), - ('.*LPTIM\d.*:G0xx_lptimer1_v1_4', 'lptim_g0/LPTIM'), + ('.*LPTIM\d.*:G0xx_lptimer1_v1_4', ('lptim', 'g0', 'LPTIM')), - ('STM32H7.*:TIM1:.*', 'timer_v1/TIM_ADV'), - ('STM32H7.*:TIM2:.*', 'timer_v1/TIM_GP32'), - ('STM32H7.*:TIM5:.*', 'timer_v1/TIM_GP32'), - ('STM32H7.*:TIM6:.*', 'timer_v1/TIM_BASIC'), - ('STM32H7.*:TIM7:.*', 'timer_v1/TIM_BASIC'), - ('STM32H7.*:TIM8:.*', 'timer_v1/TIM_ADV'), + ('STM32H7.*:TIM1:.*', ('timer', 'v1', 'TIM_ADV')), + ('STM32H7.*:TIM2:.*', ('timer', 'v1', 'TIM_GP32')), + ('STM32H7.*:TIM5:.*', ('timer', 'v1', 'TIM_GP32')), + ('STM32H7.*:TIM6:.*', ('timer', 'v1', 'TIM_BASIC')), + ('STM32H7.*:TIM7:.*', ('timer', 'v1', 'TIM_BASIC')), + ('STM32H7.*:TIM8:.*', ('timer', 'v1', 'TIM_ADV')), - ('STM32F3.*:TIM(6|7){1}:.*', 'timer_v1/TIM_BASIC'), - ('STM32F3.*:TIM(3|4|15|16|17){1}:.*', 'timer_v1/TIM_GP16'), - ('STM32F3.*:TIM2:.*', 'timer_v1/TIM_GP32'), - ('STM32F3.*:TIM(1|8|20){1}:.*', 'timer_v1/TIM_ADV'), + ('STM32F3.*:TIM(6|7){1}:.*', ('timer', 'v1', 'TIM_BASIC')), + ('STM32F3.*:TIM(3|4|15|16|17){1}:.*', ('timer', 'v1', 'TIM_GP16')), + ('STM32F3.*:TIM2:.*', ('timer', 'v1', 'TIM_GP32')), + ('STM32F3.*:TIM(1|8|20){1}:.*', ('timer', 'v1', 'TIM_ADV')), - ('STM32F7.*:TIM1:.*', 'timer_v1/TIM_ADV'), - ('STM32F7.*:TIM8:.*', 'timer_v1/TIM_ADV'), - ('.*TIM\d.*:gptimer.*', 'timer_v1/TIM_GP16'), + ('STM32F7.*:TIM1:.*', ('timer', 'v1', 'TIM_ADV')), + ('STM32F7.*:TIM8:.*', ('timer', 'v1', 'TIM_ADV')), + ('.*TIM\d.*:gptimer.*', ('timer', 'v1', 'TIM_GP16')), - ('STM32F0.*:DBGMCU:.*', 'dbgmcu_f0/DBGMCU'), - ('STM32F1.*:DBGMCU:.*', 'dbgmcu_f1/DBGMCU'), - ('STM32F2.*:DBGMCU:.*', 'dbgmcu_f2/DBGMCU'), - ('STM32F3.*:DBGMCU:.*', 'dbgmcu_f3/DBGMCU'), - ('STM32F4.*:DBGMCU:.*', 'dbgmcu_f4/DBGMCU'), - ('STM32F7.*:DBGMCU:.*', 'dbgmcu_f7/DBGMCU'), - ('STM32G0.*:DBGMCU:.*', 'dbgmcu_g0/DBGMCU'), - ('STM32G4.*:DBGMCU:.*', 'dbgmcu_g4/DBGMCU'), - ('STM32H7.*:DBGMCU:.*', 'dbgmcu_h7/DBGMCU'), - ('STM32L0.*:DBGMCU:.*', 'dbgmcu_l0/DBGMCU'), - ('STM32L1.*:DBGMCU:.*', 'dbgmcu_l1/DBGMCU'), - ('STM32L4.*:DBGMCU:.*', 'dbgmcu_l4/DBGMCU'), - ('STM32U5.*:DBGMCU:.*', 'dbgmcu_u5/DBGMCU'), - ('STM32WB.*:DBGMCU:.*', 'dbgmcu_wb/DBGMCU'), - ('STM32WL.*:DBGMCU:.*', 'dbgmcu_wl/DBGMCU'), + ('STM32F0.*:DBGMCU:.*', ('dbgmcu', 'f0', 'DBGMCU')), + ('STM32F1.*:DBGMCU:.*', ('dbgmcu', 'f1', 'DBGMCU')), + ('STM32F2.*:DBGMCU:.*', ('dbgmcu', 'f2', 'DBGMCU')), + ('STM32F3.*:DBGMCU:.*', ('dbgmcu', 'f3', 'DBGMCU')), + ('STM32F4.*:DBGMCU:.*', ('dbgmcu', 'f4', 'DBGMCU')), + ('STM32F7.*:DBGMCU:.*', ('dbgmcu', 'f7', 'DBGMCU')), + ('STM32G0.*:DBGMCU:.*', ('dbgmcu', 'g0', 'DBGMCU')), + ('STM32G4.*:DBGMCU:.*', ('dbgmcu', 'g4', 'DBGMCU')), + ('STM32H7.*:DBGMCU:.*', ('dbgmcu', 'h7', 'DBGMCU')), + ('STM32L0.*:DBGMCU:.*', ('dbgmcu', 'l0', 'DBGMCU')), + ('STM32L1.*:DBGMCU:.*', ('dbgmcu', 'l1', 'DBGMCU')), + ('STM32L4.*:DBGMCU:.*', ('dbgmcu', 'l4', 'DBGMCU')), + ('STM32U5.*:DBGMCU:.*', ('dbgmcu', 'u5', 'DBGMCU')), + ('STM32WB.*:DBGMCU:.*', ('dbgmcu', 'wb', 'DBGMCU')), + ('STM32WL.*:DBGMCU:.*', ('dbgmcu', 'wl', 'DBGMCU')), - ('STM32F1.*:GPIO.*', 'gpio_v1/GPIO'), - ('.*:GPIO.*', 'gpio_v2/GPIO'), + ('STM32F1.*:GPIO.*', ('gpio', 'v1', 'GPIO')), + ('.*:GPIO.*', ('gpio', 'v2', 'GPIO')), - ('.*:IPCC:v1_0', 'ipcc_v1/IPCC'), - ('.*:DMAMUX.*', 'dmamux_v1/DMAMUX'), + ('.*:IPCC:v1_0', ('ipcc', 'v1', 'IPCC')), + ('.*:DMAMUX.*', ('dmamux', 'v1', 'DMAMUX')), - ('.*:BDMA:.*', 'bdma_v1/DMA'), - ('STM32H7.*:DMA2D:DMA2D:dma2d1_v1_0', 'dma2d_v2/DMA2D'), - ('.*:DMA2D:dma2d1_v1_0', 'dma2d_v1/DMA2D'), - ('STM32L4[PQRS].*:DMA.*', 'bdma_v1/DMA'), # L4+ - ('STM32L[04].*:DMA.*', 'bdma_v2/DMA'), # L0, L4 non-plus (since plus is handled above) - ('STM32F030.C.*:DMA.*', 'bdma_v2/DMA'), # Weird F0 - ('STM32F09.*:DMA.*', 'bdma_v2/DMA'), # Weird F0 - ('STM32F[247].*:DMA.*', 'dma_v2/DMA'), - ('STM32H7.*:DMA.*', 'dma_v1/DMA'), - ('.*:DMA.*', 'bdma_v1/DMA'), + ('.*:BDMA:.*', ('bdma', 'v1', 'DMA')), + ('STM32H7.*:DMA2D:DMA2D:dma2d1_v1_0', ('dma2d', 'v2', 'DMA2D')), + ('.*:DMA2D:dma2d1_v1_0', ('dma2d', 'v1', 'DMA2D')), + ('STM32L4[PQRS].*:DMA.*', ('bdma', 'v1', 'DMA')), # L4+ + ('STM32L[04].*:DMA.*', ('bdma', 'v2', 'DMA')), # L0, L4 non-plus (since plus is handled above) + ('STM32F030.C.*:DMA.*', ('bdma', 'v2', 'DMA')), # Weird F0 + ('STM32F09.*:DMA.*', ('bdma', 'v2', 'DMA')), # Weird F0 + ('STM32F[247].*:DMA.*', ('dma', 'v2', 'DMA')), + ('STM32H7.*:DMA.*', ('dma', 'v1', 'DMA')), + ('.*:DMA.*', ('bdma', 'v1', 'DMA')), - ('.*:CAN:bxcan1_v1_1.*', 'can_bxcan/CAN'), + ('.*:CAN:bxcan1_v1_1.*', ('can', 'bxcan', 'CAN')), # stm32F4 CRC peripheral # ("STM32F4*:CRC:CRC:crc_f4") # v1: F1, F2, F4, L1 # v2, adds INIT reg: F0 # v3, adds POL reg: F3, F7, G0, G4, H7, L0, L4, L5, WB, WL - ('.*:CRC:integtest1_v1_0', 'crc_v1/CRC'), - ('STM32L[04].*:CRC:integtest1_v2_0', 'crc_v3/CRC'), - ('.*:CRC:integtest1_v2_0', 'crc_v2/CRC'), - ('.*:CRC:integtest1_v2_2', 'crc_v3/CRC'), + ('.*:CRC:integtest1_v1_0', ('crc', 'v1', 'CRC')), + ('STM32L[04].*:CRC:integtest1_v2_0', ('crc', 'v3', 'CRC')), + ('.*:CRC:integtest1_v2_0', ('crc', 'v2', 'CRC')), + ('.*:CRC:integtest1_v2_2', ('crc', 'v3', 'CRC')), ] peri_rename = { @@ -323,6 +323,7 @@ def lookup_address(defines, name, d): return addr +@functools.cache def match_peri(peri): for r, block in perimap: if re.match('^' + r + '$', peri): @@ -701,12 +702,16 @@ def parse_chips(): 'address': addr, } + if block := match_peri(chip_name + ':' + pname + ':' + pkind): + p['registers'] = { + 'kind': block[0], + 'version': block[1], + 'block': block[2], + } + if rcc_info := match_peri_clock(rcc_block, pname): p['rcc'] = rcc_info - if block := match_peri(chip_name + ':' + pname + ':' + pkind): - p['block'] = block - if pins := periph_pins.get(pname): # merge the core xml info with GPIO xml info to hopefully get the full picture # if the peripheral does not exist in the GPIO xml (one of the notable one is ADC) @@ -1165,7 +1170,7 @@ def parse_rcc_regs(): 'registers': regs } - peripheral_to_clock['rcc_' + ff + '/RCC'] = family_clocks + peripheral_to_clock[('rcc', ff, 'RCC')] = family_clocks def match_peri_clock(rcc_block, peri_name):