diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml index ec19d39..4750f86 100644 --- a/data/registers/rcc_f4.yaml +++ b/data/registers/rcc_f4.yaml @@ -1,1970 +1,2877 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: clock control register - byte_offset: 0 - fieldset: CR - - name: PLLCFGR - description: PLL configuration register - byte_offset: 4 - fieldset: PLLCFGR - - name: CFGR - description: clock configuration register - byte_offset: 8 - fieldset: CFGR - - name: CIR - description: clock interrupt register - byte_offset: 12 - fieldset: CIR - - name: AHB1RSTR - description: AHB1 peripheral reset register - byte_offset: 16 - fieldset: AHB1RSTR - - name: AHB2RSTR - description: AHB2 peripheral reset register - byte_offset: 20 - fieldset: AHB2RSTR - - name: AHB3RSTR - description: AHB3 peripheral reset register - byte_offset: 24 - fieldset: AHB3RSTR - - name: APB1RSTR - description: APB1 peripheral reset register - byte_offset: 32 - fieldset: APB1RSTR - - name: APB2RSTR - description: APB2 peripheral reset register - byte_offset: 36 - fieldset: APB2RSTR - - name: AHB1ENR - description: AHB1 peripheral clock register - byte_offset: 48 - fieldset: AHB1ENR - - name: AHB2ENR - description: AHB2 peripheral clock enable register - byte_offset: 52 - fieldset: AHB2ENR - - name: AHB3ENR - description: AHB3 peripheral clock enable register - byte_offset: 56 - fieldset: AHB3ENR - - name: APB1ENR - description: APB1 peripheral clock enable register - byte_offset: 64 - fieldset: APB1ENR - - name: APB2ENR - description: APB2 peripheral clock enable register - byte_offset: 68 - fieldset: APB2ENR - - name: AHB1LPENR - description: AHB1 peripheral clock enable in low power mode register - byte_offset: 80 - fieldset: AHB1LPENR - - name: AHB2LPENR - description: AHB2 peripheral clock enable in low power mode register - byte_offset: 84 - fieldset: AHB2LPENR - - name: AHB3LPENR - description: AHB3 peripheral clock enable in low power mode register - byte_offset: 88 - fieldset: AHB3LPENR - - name: APB1LPENR - description: APB1 peripheral clock enable in low power mode register - byte_offset: 96 - fieldset: APB1LPENR - - name: APB2LPENR - description: APB2 peripheral clock enabled in low power mode register - byte_offset: 100 - fieldset: APB2LPENR - - name: BDCR - description: Backup domain control register - byte_offset: 112 - fieldset: BDCR - - name: CSR - description: clock control & status register - byte_offset: 116 - fieldset: CSR - - name: SSCGR - description: spread spectrum clock generation register - byte_offset: 128 - fieldset: SSCGR - - name: PLLI2SCFGR - description: PLLI2S configuration register - byte_offset: 132 - fieldset: PLLI2SCFGR - - name: PLLSAICFGR - description: RCC PLL configuration register - byte_offset: 136 - fieldset: PLLSAICFGR - - name: DCKCFGR - description: RCC Dedicated Clock Configuration Register - byte_offset: 140 - fieldset: DCKCFGR -fieldset/AHB1ENR: - description: AHB1 peripheral clock register - fields: - - name: GPIOAEN - description: IO port A clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: IO port B clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: IO port C clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: IO port D clock enable - bit_offset: 3 - bit_size: 1 - - name: GPIOEEN - description: IO port E clock enable - bit_offset: 4 - bit_size: 1 - - name: GPIOFEN - description: IO port F clock enable - bit_offset: 5 - bit_size: 1 - - name: GPIOGEN - description: IO port G clock enable - bit_offset: 6 - bit_size: 1 - - name: GPIOHEN - description: IO port H clock enable - bit_offset: 7 - bit_size: 1 - - name: GPIOIEN - description: IO port I clock enable - bit_offset: 8 - bit_size: 1 - - name: GPIOJEN - description: IO port J clock enable - bit_offset: 9 - bit_size: 1 - - name: GPIOKEN - description: IO port K clock enable - bit_offset: 10 - bit_size: 1 - - name: CRCEN - description: CRC clock enable - bit_offset: 12 - bit_size: 1 - - name: BKPSRAMEN - description: Backup SRAM interface clock enable - bit_offset: 18 - bit_size: 1 - - name: CCMDATARAMEN - description: CCM data RAM clock enable - bit_offset: 20 - bit_size: 1 - - name: DMA1EN - description: DMA1 clock enable - bit_offset: 21 - bit_size: 1 - - name: DMA2EN - description: DMA2 clock enable - bit_offset: 22 - bit_size: 1 - - name: DMA2DEN - description: DMA2D clock enable - bit_offset: 23 - bit_size: 1 - - name: ETHMACEN - description: Ethernet MAC clock enable - bit_offset: 25 - bit_size: 1 - - name: ETHMACTXEN - description: Ethernet Transmission clock enable - bit_offset: 26 - bit_size: 1 - - name: ETHMACRXEN - description: Ethernet Reception clock enable - bit_offset: 27 - bit_size: 1 - - name: ETHMACPTPEN - description: Ethernet PTP clock enable - bit_offset: 28 - bit_size: 1 - - name: OTGHSEN - description: USB OTG HS clock enable - bit_offset: 29 - bit_size: 1 - - name: OTGHSULPIEN - description: USB OTG HSULPI clock enable - bit_offset: 30 - bit_size: 1 -fieldset/AHB1LPENR: - description: AHB1 peripheral clock enable in low power mode register - fields: - - name: GPIOALPEN - description: IO port A clock enable during sleep mode - bit_offset: 0 - bit_size: 1 - - name: GPIOBLPEN - description: IO port B clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: GPIOCLPEN - description: IO port C clock enable during Sleep mode - bit_offset: 2 - bit_size: 1 - - name: GPIODLPEN - description: IO port D clock enable during Sleep mode - bit_offset: 3 - bit_size: 1 - - name: GPIOELPEN - description: IO port E clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: GPIOFLPEN - description: IO port F clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: GPIOGLPEN - description: IO port G clock enable during Sleep mode - bit_offset: 6 - bit_size: 1 - - name: GPIOHLPEN - description: IO port H clock enable during Sleep mode - bit_offset: 7 - bit_size: 1 - - name: GPIOILPEN - description: IO port I clock enable during Sleep mode - bit_offset: 8 - bit_size: 1 - - name: GPIOJLPEN - description: IO port J clock enable during Sleep mode - bit_offset: 9 - bit_size: 1 - - name: GPIOKLPEN - description: IO port K clock enable during Sleep mode - bit_offset: 10 - bit_size: 1 - - name: CRCLPEN - description: CRC clock enable during Sleep mode - bit_offset: 12 - bit_size: 1 - - name: FLITFLPEN - description: Flash interface clock enable during Sleep mode - bit_offset: 15 - bit_size: 1 - - name: SRAM1LPEN - description: SRAM 1interface clock enable during Sleep mode - bit_offset: 16 - bit_size: 1 - - name: SRAM2LPEN - description: SRAM 2 interface clock enable during Sleep mode - bit_offset: 17 - bit_size: 1 - - name: BKPSRAMLPEN - description: Backup SRAM interface clock enable during Sleep mode - bit_offset: 18 - bit_size: 1 - - name: SRAM3LPEN - description: SRAM3 interface clock enable during Sleep mode - bit_offset: 19 - bit_size: 1 - - name: DMA1LPEN - description: DMA1 clock enable during Sleep mode - bit_offset: 21 - bit_size: 1 - - name: DMA2LPEN - description: DMA2 clock enable during Sleep mode - bit_offset: 22 - bit_size: 1 - - name: DMA2DLPEN - description: DMA2D clock enable during Sleep mode - bit_offset: 23 - bit_size: 1 - - name: ETHMACLPEN - description: Ethernet MAC clock enable during Sleep mode - bit_offset: 25 - bit_size: 1 - - name: ETHMACTXLPEN - description: Ethernet transmission clock enable during Sleep mode - bit_offset: 26 - bit_size: 1 - - name: ETHMACRXLPEN - description: Ethernet reception clock enable during Sleep mode - bit_offset: 27 - bit_size: 1 - - name: ETHMACPTPLPEN - description: Ethernet PTP clock enable during Sleep mode - bit_offset: 28 - bit_size: 1 - - name: OTGHSLPEN - description: USB OTG HS clock enable during Sleep mode - bit_offset: 29 - bit_size: 1 - - name: OTGHSULPILPEN - description: USB OTG HS ULPI clock enable during Sleep mode - bit_offset: 30 - bit_size: 1 -fieldset/AHB1RSTR: - description: AHB1 peripheral reset register - fields: - - name: GPIOARST - description: IO port A reset - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: IO port B reset - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: IO port C reset - bit_offset: 2 - bit_size: 1 - - name: GPIODRST - description: IO port D reset - bit_offset: 3 - bit_size: 1 - - name: GPIOERST - description: IO port E reset - bit_offset: 4 - bit_size: 1 - - name: GPIOFRST - description: IO port F reset - bit_offset: 5 - bit_size: 1 - - name: GPIOGRST - description: IO port G reset - bit_offset: 6 - bit_size: 1 - - name: GPIOHRST - description: IO port H reset - bit_offset: 7 - bit_size: 1 - - name: GPIOIRST - description: IO port I reset - bit_offset: 8 - bit_size: 1 - - name: GPIOJRST - description: IO port J reset - bit_offset: 9 - bit_size: 1 - - name: GPIOKRST - description: IO port K reset - bit_offset: 10 - bit_size: 1 - - name: CRCRST - description: CRC reset - bit_offset: 12 - bit_size: 1 - - name: DMA1RST - description: DMA2 reset - bit_offset: 21 - bit_size: 1 - - name: DMA2RST - description: DMA2 reset - bit_offset: 22 - bit_size: 1 - - name: DMA2DRST - description: DMA2D reset - bit_offset: 23 - bit_size: 1 - - name: ETHMACRST - description: Ethernet MAC reset - bit_offset: 25 - bit_size: 1 - - name: OTGHSRST - description: USB OTG HS module reset - bit_offset: 29 - bit_size: 1 -fieldset/AHB2ENR: - description: AHB2 peripheral clock enable register - fields: - - name: DCMIEN - description: Camera interface enable - bit_offset: 0 - bit_size: 1 - - name: CRYPEN - description: Cryptographic modules clock enable - bit_offset: 4 - bit_size: 1 - - name: HASHEN - description: Hash modules clock enable - bit_offset: 5 - bit_size: 1 - - name: RNGEN - description: Random number generator clock enable - bit_offset: 6 - bit_size: 1 - - name: OTGFSEN - description: USB OTG FS clock enable - bit_offset: 7 - bit_size: 1 -fieldset/AHB2LPENR: - description: AHB2 peripheral clock enable in low power mode register - fields: - - name: DCMILPEN - description: Camera interface enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: CRYPLPEN - description: Cryptography modules clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: HASHLPEN - description: Hash modules clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: RNGLPEN - description: Random number generator clock enable during Sleep mode - bit_offset: 6 - bit_size: 1 - - name: OTGFSLPEN - description: USB OTG FS clock enable during Sleep mode - bit_offset: 7 - bit_size: 1 -fieldset/AHB2RSTR: - description: AHB2 peripheral reset register - fields: - - name: DCMIRST - description: Camera interface reset - bit_offset: 0 - bit_size: 1 - - name: CRYPRST - description: Cryptographic module reset - bit_offset: 4 - bit_size: 1 - - name: HSAHRST - description: Hash module reset - bit_offset: 5 - bit_size: 1 - - name: RNGRST - description: Random number generator module reset - bit_offset: 6 - bit_size: 1 - - name: OTGFSRST - description: USB OTG FS module reset - bit_offset: 7 - bit_size: 1 -fieldset/AHB3ENR: - description: AHB3 peripheral clock enable register - fields: - - name: FMCEN - description: Flexible memory controller module clock enable - bit_offset: 0 - bit_size: 1 -fieldset/AHB3LPENR: - description: AHB3 peripheral clock enable in low power mode register - fields: - - name: FMCLPEN - description: Flexible memory controller module clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 -fieldset/AHB3RSTR: - description: AHB3 peripheral reset register - fields: - - name: FMCRST - description: Flexible memory controller module reset - bit_offset: 0 - bit_size: 1 -fieldset/APB1ENR: - description: APB1 peripheral clock enable register - fields: - - name: TIM2EN - description: TIM2 clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: TIM3 clock enable - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: TIM4 clock enable - bit_offset: 2 - bit_size: 1 - - name: TIM5EN - description: TIM5 clock enable - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: TIM6 clock enable - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: TIM7 clock enable - bit_offset: 5 - bit_size: 1 - - name: TIM12EN - description: TIM12 clock enable - bit_offset: 6 - bit_size: 1 - - name: TIM13EN - description: TIM13 clock enable - bit_offset: 7 - bit_size: 1 - - name: TIM14EN - description: TIM14 clock enable - bit_offset: 8 - bit_size: 1 - - name: WWDGEN - description: Window watchdog clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI2 clock enable - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: SPI3 clock enable - bit_offset: 15 - bit_size: 1 - - name: USART2EN - description: USART 2 clock enable - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: USART3 clock enable - bit_offset: 18 - bit_size: 1 - - name: UART4EN - description: UART4 clock enable - bit_offset: 19 - bit_size: 1 - - name: UART5EN - description: UART5 clock enable - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C1 clock enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C2 clock enable - bit_offset: 22 - bit_size: 1 - - name: I2C3EN - description: I2C3 clock enable - bit_offset: 23 - bit_size: 1 - - name: CAN1EN - description: CAN 1 clock enable - bit_offset: 25 - bit_size: 1 - - name: CAN2EN - description: CAN 2 clock enable - bit_offset: 26 - bit_size: 1 - - name: PWREN - description: Power interface clock enable - bit_offset: 28 - bit_size: 1 - - name: DACEN - description: DAC interface clock enable - bit_offset: 29 - bit_size: 1 - - name: UART7EN - description: UART7 clock enable - bit_offset: 30 - bit_size: 1 - - name: UART8EN - description: UART8 clock enable - bit_offset: 31 - bit_size: 1 -fieldset/APB1LPENR: - description: APB1 peripheral clock enable in low power mode register - fields: - - name: TIM2LPEN - description: TIM2 clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM3LPEN - description: TIM3 clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: TIM4LPEN - description: TIM4 clock enable during Sleep mode - bit_offset: 2 - bit_size: 1 - - name: TIM5LPEN - description: TIM5 clock enable during Sleep mode - bit_offset: 3 - bit_size: 1 - - name: TIM6LPEN - description: TIM6 clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: TIM7LPEN - description: TIM7 clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: TIM12LPEN - description: TIM12 clock enable during Sleep mode - bit_offset: 6 - bit_size: 1 - - name: TIM13LPEN - description: TIM13 clock enable during Sleep mode - bit_offset: 7 - bit_size: 1 - - name: TIM14LPEN - description: TIM14 clock enable during Sleep mode - bit_offset: 8 - bit_size: 1 - - name: WWDGLPEN - description: Window watchdog clock enable during Sleep mode - bit_offset: 11 - bit_size: 1 - - name: SPI2LPEN - description: SPI2 clock enable during Sleep mode - bit_offset: 14 - bit_size: 1 - - name: SPI3LPEN - description: SPI3 clock enable during Sleep mode - bit_offset: 15 - bit_size: 1 - - name: USART2LPEN - description: USART2 clock enable during Sleep mode - bit_offset: 17 - bit_size: 1 - - name: USART3LPEN - description: USART3 clock enable during Sleep mode - bit_offset: 18 - bit_size: 1 - - name: UART4LPEN - description: UART4 clock enable during Sleep mode - bit_offset: 19 - bit_size: 1 - - name: UART5LPEN - description: UART5 clock enable during Sleep mode - bit_offset: 20 - bit_size: 1 - - name: I2C1LPEN - description: I2C1 clock enable during Sleep mode - bit_offset: 21 - bit_size: 1 - - name: I2C2LPEN - description: I2C2 clock enable during Sleep mode - bit_offset: 22 - bit_size: 1 - - name: I2C3LPEN - description: I2C3 clock enable during Sleep mode - bit_offset: 23 - bit_size: 1 - - name: CAN1LPEN - description: CAN 1 clock enable during Sleep mode - bit_offset: 25 - bit_size: 1 - - name: CAN2LPEN - description: CAN 2 clock enable during Sleep mode - bit_offset: 26 - bit_size: 1 - - name: PWRLPEN - description: Power interface clock enable during Sleep mode - bit_offset: 28 - bit_size: 1 - - name: DACLPEN - description: DAC interface clock enable during Sleep mode - bit_offset: 29 - bit_size: 1 - - name: UART7LPEN - description: UART7 clock enable during Sleep mode - bit_offset: 30 - bit_size: 1 - - name: UART8LPEN - description: UART8 clock enable during Sleep mode - bit_offset: 31 - bit_size: 1 -fieldset/APB1RSTR: - description: APB1 peripheral reset register - fields: - - name: TIM2RST - description: TIM2 reset - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: TIM3 reset - bit_offset: 1 - bit_size: 1 - - name: TIM4RST - description: TIM4 reset - bit_offset: 2 - bit_size: 1 - - name: TIM5RST - description: TIM5 reset - bit_offset: 3 - bit_size: 1 - - name: TIM6RST - description: TIM6 reset - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: TIM7 reset - bit_offset: 5 - bit_size: 1 - - name: TIM12RST - description: TIM12 reset - bit_offset: 6 - bit_size: 1 - - name: TIM13RST - description: TIM13 reset - bit_offset: 7 - bit_size: 1 - - name: TIM14RST - description: TIM14 reset - bit_offset: 8 - bit_size: 1 - - name: WWDGRST - description: Window watchdog reset - bit_offset: 11 - bit_size: 1 - - name: SPI2RST - description: SPI 2 reset - bit_offset: 14 - bit_size: 1 - - name: SPI3RST - description: SPI 3 reset - bit_offset: 15 - bit_size: 1 - - name: UART2RST - description: USART 2 reset - bit_offset: 17 - bit_size: 1 - - name: UART3RST - description: USART 3 reset - bit_offset: 18 - bit_size: 1 - - name: UART4RST - description: USART 4 reset - bit_offset: 19 - bit_size: 1 - - name: UART5RST - description: USART 5 reset - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: I2C 1 reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C 2 reset - bit_offset: 22 - bit_size: 1 - - name: I2C3RST - description: I2C3 reset - bit_offset: 23 - bit_size: 1 - - name: CAN1RST - description: CAN1 reset - bit_offset: 25 - bit_size: 1 - - name: CAN2RST - description: CAN2 reset - bit_offset: 26 - bit_size: 1 - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - - name: DACRST - description: DAC reset - bit_offset: 29 - bit_size: 1 - - name: UART7RST - description: UART7 reset - bit_offset: 30 - bit_size: 1 - - name: UART8RST - description: UART8 reset - bit_offset: 31 - bit_size: 1 -fieldset/APB2ENR: - description: APB2 peripheral clock enable register - fields: - - name: TIM1EN - description: TIM1 clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM8EN - description: TIM8 clock enable - bit_offset: 1 - bit_size: 1 - - name: USART1EN - description: USART1 clock enable - bit_offset: 4 - bit_size: 1 - - name: USART6EN - description: USART6 clock enable - bit_offset: 5 - bit_size: 1 - - name: ADC1EN - description: ADC1 clock enable - bit_offset: 8 - bit_size: 1 - - name: ADC2EN - description: ADC2 clock enable - bit_offset: 9 - bit_size: 1 - - name: ADC3EN - description: ADC3 clock enable - bit_offset: 10 - bit_size: 1 - - name: SDIOEN - description: SDIO clock enable - bit_offset: 11 - bit_size: 1 - - name: SPI1EN - description: SPI1 clock enable - bit_offset: 12 - bit_size: 1 - - name: SPI4EN - description: SPI4 clock enable - bit_offset: 13 - bit_size: 1 - - name: SYSCFGEN - description: System configuration controller clock enable - bit_offset: 14 - bit_size: 1 - - name: TIM9EN - description: TIM9 clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM10EN - description: TIM10 clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM11EN - description: TIM11 clock enable - bit_offset: 18 - bit_size: 1 - - name: SPI5EN - description: SPI5 clock enable - bit_offset: 20 - bit_size: 1 - - name: SPI6EN - description: SPI6 clock enable - bit_offset: 21 - bit_size: 1 - - name: SAI1EN - description: SAI1 clock enable - bit_offset: 22 - bit_size: 1 - - name: LTDCEN - description: LTDC clock enable - bit_offset: 26 - bit_size: 1 -fieldset/APB2LPENR: - description: APB2 peripheral clock enabled in low power mode register - fields: - - name: TIM1LPEN - description: TIM1 clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM8LPEN - description: TIM8 clock enable during Sleep mode - bit_offset: 1 - bit_size: 1 - - name: USART1LPEN - description: USART1 clock enable during Sleep mode - bit_offset: 4 - bit_size: 1 - - name: USART6LPEN - description: USART6 clock enable during Sleep mode - bit_offset: 5 - bit_size: 1 - - name: ADC1LPEN - description: ADC1 clock enable during Sleep mode - bit_offset: 8 - bit_size: 1 - - name: ADC2LPEN - description: ADC2 clock enable during Sleep mode - bit_offset: 9 - bit_size: 1 - - name: ADC3LPEN - description: ADC 3 clock enable during Sleep mode - bit_offset: 10 - bit_size: 1 - - name: SDIOLPEN - description: SDIO clock enable during Sleep mode - bit_offset: 11 - bit_size: 1 - - name: SPI1LPEN - description: SPI 1 clock enable during Sleep mode - bit_offset: 12 - bit_size: 1 - - name: SPI4LPEN - description: SPI4 clock enable during Sleep mode - bit_offset: 13 - bit_size: 1 - - name: SYSCFGLPEN - description: System configuration controller clock enable during Sleep mode - bit_offset: 14 - bit_size: 1 - - name: TIM9LPEN - description: TIM9 clock enable during sleep mode - bit_offset: 16 - bit_size: 1 - - name: TIM10LPEN - description: TIM10 clock enable during Sleep mode - bit_offset: 17 - bit_size: 1 - - name: TIM11LPEN - description: TIM11 clock enable during Sleep mode - bit_offset: 18 - bit_size: 1 - - name: SPI5LPEN - description: SPI5 clock enable during Sleep mode - bit_offset: 20 - bit_size: 1 - - name: SPI6LPEN - description: SPI6 clock enable during Sleep mode - bit_offset: 21 - bit_size: 1 - - name: SAI1LPEN - description: SAI1 clock enable during Sleep mode - bit_offset: 22 - bit_size: 1 - - name: LTDCLPEN - description: LTDC clock enable during Sleep mode - bit_offset: 26 - bit_size: 1 -fieldset/APB2RSTR: - description: APB2 peripheral reset register - fields: - - name: TIM1RST - description: TIM1 reset - bit_offset: 0 - bit_size: 1 - - name: TIM8RST - description: TIM8 reset - bit_offset: 1 - bit_size: 1 - - name: USART1RST - description: USART1 reset - bit_offset: 4 - bit_size: 1 - - name: USART6RST - description: USART6 reset - bit_offset: 5 - bit_size: 1 - - name: ADCRST - description: ADC interface reset (common to all ADCs) - bit_offset: 8 - bit_size: 1 - - name: SDIORST - description: SDIO reset - bit_offset: 11 - bit_size: 1 - - name: SPI1RST - description: SPI 1 reset - bit_offset: 12 - bit_size: 1 - - name: SPI4RST - description: SPI4 reset - bit_offset: 13 - bit_size: 1 - - name: SYSCFGRST - description: System configuration controller reset - bit_offset: 14 - bit_size: 1 - - name: TIM9RST - description: TIM9 reset - bit_offset: 16 - bit_size: 1 - - name: TIM10RST - description: TIM10 reset - bit_offset: 17 - bit_size: 1 - - name: TIM11RST - description: TIM11 reset - bit_offset: 18 - bit_size: 1 - - name: SPI5RST - description: SPI5 reset - bit_offset: 20 - bit_size: 1 - - name: SPI6RST - description: SPI6 reset - bit_offset: 21 - bit_size: 1 - - name: SAI1RST - description: SAI1 reset - bit_offset: 22 - bit_size: 1 - - name: LTDCRST - description: LTDC reset - bit_offset: 26 - bit_size: 1 -fieldset/BDCR: - description: Backup domain control register - fields: - - name: LSEON - description: External low-speed oscillator enable - bit_offset: 0 - bit_size: 1 - enum: LSEON - - name: LSERDY - description: External low-speed oscillator ready - bit_offset: 1 - bit_size: 1 - enum_read: LSERDYR - - name: LSEBYP - description: External low-speed oscillator bypass - bit_offset: 2 - bit_size: 1 - enum: LSEBYP - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: Backup domain software reset - bit_offset: 16 - bit_size: 1 -fieldset/CFGR: - description: clock configuration register - fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 2 - enum: SW - - name: SWS - description: System clock switch status - bit_offset: 2 - bit_size: 2 - enum_read: SWSR - - name: HPRE - description: AHB prescaler - bit_offset: 4 - bit_size: 4 - enum: HPRE - - name: PPRE - description: APB Low speed prescaler (APB1) - bit_offset: 10 - bit_size: 3 - array: - len: 2 - stride: 3 - enum: PPRE - - name: RTCPRE - description: HSE division factor for RTC clock - bit_offset: 16 - bit_size: 5 - - name: MCO - description: Microcontroller clock output 1 - bit_offset: 21 - bit_size: 2 - array: - len: 2 - stride: 9 - enum: MCO1 - - name: I2SSRC - description: I2S clock selection - bit_offset: 23 - bit_size: 1 - enum: ISSRC - - name: MCO1PRE - description: MCO1 prescaler - bit_offset: 24 - bit_size: 3 - enum: MCOPRE - - name: MCO2PRE - description: MCO2 prescaler - bit_offset: 27 - bit_size: 3 - enum: MCOPRE -fieldset/CIR: - description: clock interrupt register - fields: - - name: LSIRDYF - description: LSI ready interrupt flag - bit_offset: 0 - bit_size: 1 - enum_read: PLLISRDYFR - - name: LSERDYF - description: LSE ready interrupt flag - bit_offset: 1 - bit_size: 1 - enum_read: PLLISRDYFR - - name: HSIRDYF - description: HSI ready interrupt flag - bit_offset: 2 - bit_size: 1 - enum_read: PLLISRDYFR - - name: HSERDYF - description: HSE ready interrupt flag - bit_offset: 3 - bit_size: 1 - enum_read: PLLISRDYFR - - name: PLLRDYF - description: Main PLL (PLL) ready interrupt flag - bit_offset: 4 - bit_size: 1 - enum_read: PLLISRDYFR - - name: PLLI2SRDYF - description: PLLI2S ready interrupt flag - bit_offset: 5 - bit_size: 1 - enum_read: PLLISRDYFR - - name: CSSF - description: Clock security system interrupt flag - bit_offset: 7 - bit_size: 1 - enum_read: CSSFR - - name: LSIRDYIE - description: LSI ready interrupt enable - bit_offset: 8 - bit_size: 1 - enum: PLLISRDYIE - - name: LSERDYIE - description: LSE ready interrupt enable - bit_offset: 9 - bit_size: 1 - enum: PLLISRDYIE - - name: HSIRDYIE - description: HSI ready interrupt enable - bit_offset: 10 - bit_size: 1 - enum: PLLISRDYIE - - name: HSERDYIE - description: HSE ready interrupt enable - bit_offset: 11 - bit_size: 1 - enum: PLLISRDYIE - - name: PLLRDYIE - description: Main PLL (PLL) ready interrupt enable - bit_offset: 12 - bit_size: 1 - enum: PLLISRDYIE - - name: PLLI2SRDYIE - description: PLLI2S ready interrupt enable - bit_offset: 13 - bit_size: 1 - enum: PLLISRDYIE - - name: LSIRDYC - description: LSI ready interrupt clear - bit_offset: 16 - bit_size: 1 - enum_write: PLLISRDYCW - - name: LSERDYC - description: LSE ready interrupt clear - bit_offset: 17 - bit_size: 1 - enum_write: PLLISRDYCW - - name: HSIRDYC - description: HSI ready interrupt clear - bit_offset: 18 - bit_size: 1 - enum_write: PLLISRDYCW - - name: HSERDYC - description: HSE ready interrupt clear - bit_offset: 19 - bit_size: 1 - enum_write: PLLISRDYCW - - name: PLLRDYC - description: Main PLL(PLL) ready interrupt clear - bit_offset: 20 - bit_size: 1 - enum_write: PLLISRDYCW - - name: PLLI2SRDYC - description: PLLI2S ready interrupt clear - bit_offset: 21 - bit_size: 1 - enum_write: PLLISRDYCW - - name: CSSC - description: Clock security system interrupt clear - bit_offset: 23 - bit_size: 1 - enum_write: CSSCW -fieldset/CR: - description: clock control register - fields: - - name: HSION - description: Internal high-speed clock enable - bit_offset: 0 - bit_size: 1 - enum: PLLISON - - name: HSIRDY - description: Internal high-speed clock ready flag - bit_offset: 1 - bit_size: 1 - enum_read: PLLISRDYR - - name: HSITRIM - description: Internal high-speed clock trimming - bit_offset: 3 - bit_size: 5 - - name: HSICAL - description: Internal high-speed clock calibration - bit_offset: 8 - bit_size: 8 - - name: HSEON - description: HSE clock enable - bit_offset: 16 - bit_size: 1 - enum: PLLISON - - name: HSERDY - description: HSE clock ready flag - bit_offset: 17 - bit_size: 1 - enum_read: PLLISRDYR - - name: HSEBYP - description: HSE clock bypass - bit_offset: 18 - bit_size: 1 - enum: HSEBYP - - name: CSSON - description: Clock security system enable - bit_offset: 19 - bit_size: 1 - enum: CSSON - - name: PLLON - description: Main PLL (PLL) enable - bit_offset: 24 - bit_size: 1 - enum: PLLISON - - name: PLLRDY - description: Main PLL (PLL) clock ready flag - bit_offset: 25 - bit_size: 1 - enum_read: PLLISRDYR - - name: PLLI2SON - description: PLLI2S enable - bit_offset: 26 - bit_size: 1 - enum: PLLISON - - name: PLLI2SRDY - description: PLLI2S clock ready flag - bit_offset: 27 - bit_size: 1 - enum_read: PLLISRDYR - - name: PLLSAION - description: PLLSAI enable - bit_offset: 28 - bit_size: 1 - enum: PLLISON - - name: PLLSAIRDY - description: PLLSAI clock ready flag - bit_offset: 29 - bit_size: 1 - enum_read: PLLISRDYR -fieldset/CSR: - description: clock control & status register - fields: - - name: LSION - description: Internal low-speed oscillator enable - bit_offset: 0 - bit_size: 1 - enum: LSION - - name: LSIRDY - description: Internal low-speed oscillator ready - bit_offset: 1 - bit_size: 1 - enum_read: LSIRDYR - - name: RMVF - description: Remove reset flag - bit_offset: 24 - bit_size: 1 - enum_write: RMVFW - - name: BORRSTF - description: BOR reset flag - bit_offset: 25 - bit_size: 1 - enum_read: LPWRRSTFR - - name: PADRSTF - description: PIN reset flag - bit_offset: 26 - bit_size: 1 - enum_read: LPWRRSTFR - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 27 - bit_size: 1 - enum_read: LPWRRSTFR - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - enum_read: LPWRRSTFR - - name: WDGRSTF - description: Independent watchdog reset flag - bit_offset: 29 - bit_size: 1 - enum_read: LPWRRSTFR - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - enum_read: LPWRRSTFR - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 - enum_read: LPWRRSTFR -fieldset/DCKCFGR: - description: RCC Dedicated Clock Configuration Register - fields: - - name: PLLI2SDIVQ - description: PLLI2S division factor for SAI1 clock - bit_offset: 0 - bit_size: 5 - enum: PLLISDIVQ - - name: PLLSAIDIVQ - description: PLLSAI division factor for SAI1 clock - bit_offset: 8 - bit_size: 5 - enum: PLLSAIDIVQ - - name: PLLSAIDIVR - description: division factor for LCD_CLK - bit_offset: 16 - bit_size: 2 - enum: PLLSAIDIVR - - name: SAI1ASRC - description: SAI1-A clock source selection - bit_offset: 20 - bit_size: 2 - enum: SAIASRC - - name: SAI1BSRC - description: SAI1-B clock source selection - bit_offset: 22 - bit_size: 2 - enum: SAIBSRC - - name: TIMPRE - description: Timers clocks prescalers selection - bit_offset: 24 - bit_size: 1 - enum: TIMPRE -fieldset/PLLCFGR: - description: PLL configuration register - fields: - - name: PLLM - description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock - bit_offset: 0 - bit_size: 6 - - name: PLLN - description: Main PLL (PLL) multiplication factor for VCO - bit_offset: 6 - bit_size: 9 - - name: PLLP - description: Main PLL (PLL) division factor for main system clock - bit_offset: 16 - bit_size: 2 - enum: PLLP - - name: PLLSRC - description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source - bit_offset: 22 - bit_size: 1 - enum: PLLSRC - - name: PLLQ - description: "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks" - bit_offset: 24 - bit_size: 4 -fieldset/PLLI2SCFGR: - description: PLLI2S configuration register - fields: - - name: PLLI2SN - description: PLLI2S multiplication factor for VCO - bit_offset: 6 - bit_size: 9 - - name: PLLI2SQ - description: PLLI2S division factor for SAI1 clock - bit_offset: 24 - bit_size: 4 - - name: PLLI2SR - description: PLLI2S division factor for I2S clocks - bit_offset: 28 - bit_size: 3 -fieldset/PLLSAICFGR: - description: RCC PLL configuration register - fields: - - name: PLLSAIN - description: PLLSAI division factor for VCO - bit_offset: 6 - bit_size: 9 - - name: PLLSAIQ - description: PLLSAI division factor for SAI1 clock - bit_offset: 24 - bit_size: 4 - - name: PLLSAIR - description: PLLSAI division factor for LCD clock - bit_offset: 28 - bit_size: 3 -fieldset/SSCGR: - description: spread spectrum clock generation register - fields: - - name: MODPER - description: Modulation period - bit_offset: 0 - bit_size: 13 - - name: INCSTEP - description: Incrementation step - bit_offset: 13 - bit_size: 15 - - name: SPREADSEL - description: Spread Select - bit_offset: 30 - bit_size: 1 - enum: SPREADSEL - - name: SSCGEN - description: Spread spectrum modulation enable - bit_offset: 31 - bit_size: 1 + - byte_offset: 0 + description: clock control register + fieldset: CR + name: CR + - byte_offset: 4 + description: PLL configuration register + fieldset: PLLCFGR + name: PLLCFGR + - byte_offset: 8 + description: clock configuration register + fieldset: CFGR + name: CFGR + - byte_offset: 12 + description: clock interrupt register + fieldset: CIR + name: CIR + - byte_offset: 16 + description: AHB1 peripheral reset register + fieldset: AHB1RSTR + name: AHB1RSTR + - byte_offset: 20 + description: AHB2 peripheral reset register + fieldset: AHB2RSTR + name: AHB2RSTR + - byte_offset: 32 + description: APB1 peripheral reset register + fieldset: APB1RSTR + name: APB1RSTR + - byte_offset: 36 + description: APB2 peripheral reset register + fieldset: APB2RSTR + name: APB2RSTR + - byte_offset: 48 + description: AHB1 peripheral clock register + fieldset: AHB1ENR + name: AHB1ENR + - byte_offset: 52 + description: AHB2 peripheral clock enable register + fieldset: AHB2ENR + name: AHB2ENR + - byte_offset: 64 + description: APB1 peripheral clock enable register + fieldset: APB1ENR + name: APB1ENR + - byte_offset: 68 + description: APB2 peripheral clock enable register + fieldset: APB2ENR + name: APB2ENR + - byte_offset: 80 + description: AHB1 peripheral clock enable in low power mode register + fieldset: AHB1LPENR + name: AHB1LPENR + - byte_offset: 84 + description: AHB2 peripheral clock enable in low power mode register + fieldset: AHB2LPENR + name: AHB2LPENR + - byte_offset: 96 + description: APB1 peripheral clock enable in low power mode register + fieldset: APB1LPENR + name: APB1LPENR + - byte_offset: 100 + description: APB2 peripheral clock enabled in low power mode register + fieldset: APB2LPENR + name: APB2LPENR + - byte_offset: 112 + description: Backup domain control register + fieldset: BDCR + name: BDCR + - byte_offset: 116 + description: clock control & status register + fieldset: CSR + name: CSR + - byte_offset: 128 + description: spread spectrum clock generation register + fieldset: SSCGR + name: SSCGR + - byte_offset: 132 + description: PLLI2S configuration register + fieldset: PLLI2SCFGR + name: PLLI2SCFGR + - byte_offset: 140 + description: RCC Dedicated Clock Configuration Register + fieldset: DCKCFGR + name: DCKCFGR + - byte_offset: 24 + description: AHB3 peripheral reset register + fieldset: AHB3RSTR + name: AHB3RSTR + - byte_offset: 56 + description: AHB3 peripheral clock enable register + fieldset: AHB3ENR + name: AHB3ENR + - byte_offset: 88 + description: AHB3 peripheral clock enable in low power mode register + fieldset: AHB3LPENR + name: AHB3LPENR + - byte_offset: 148 + description: DCKCFGR2 register + fieldset: DCKCFGR2 + name: DCKCFGR2 + - byte_offset: 144 + description: Clocks gated enable register + fieldset: CKGATENR + name: CKGATENR + - byte_offset: 136 + description: RCC PLL configuration register + fieldset: PLLSAICFGR + name: PLLSAICFGR +enum/CECSEL: + bit_size: 1 + variants: + - description: LSE clock is selected as HDMI-CEC clock + name: LSE + value: 0 + - description: HSI divided by 488 clock is selected as HDMI-CEC clock + name: HSI_Div488 + value: 1 +enum/CKDFSDMASEL: + bit_size: 1 + variants: + - description: CK_I2S_APB1 selected as audio clock + name: I2S1 + value: 0 + - description: CK_I2S_APB2 selected as audio clock + name: I2S2 + value: 1 +enum/CKDFSDMSEL: + bit_size: 1 + variants: + - description: APB2 clock used as Kernel clock + name: APB2 + value: 0 + - description: System clock used as Kernel clock + name: SYSCLK + value: 1 +enum/CKMSEL: + bit_size: 1 + variants: + - description: 48MHz clock from PLL is selected + name: PLL + value: 0 + - description: 48MHz clock from PLLSAI is selected + name: PLLSAI + value: 1 enum/CSSCW: bit_size: 1 variants: - - name: Clear - description: Clear CSSF flag - value: 1 + - description: Clear CSSF flag + name: Clear + value: 1 enum/CSSFR: bit_size: 1 variants: - - name: NotInterrupted - description: No clock security interrupt caused by HSE clock failure - value: 0 - - name: Interrupted - description: Clock security interrupt caused by HSE clock failure - value: 1 + - description: No clock security interrupt caused by HSE clock failure + name: NotInterrupted + value: 0 + - description: Clock security interrupt caused by HSE clock failure + name: Interrupted + value: 1 enum/CSSON: bit_size: 1 variants: - - name: "Off" - description: Clock security system disabled (clock detector OFF) - value: 0 - - name: "On" - description: "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)" - value: 1 + - description: Clock security system disabled (clock detector OFF) + name: 'Off' + value: 0 + - description: Clock security system enable (clock detector ON if the HSE is ready, + OFF if not) + name: 'On' + value: 1 +enum/DSISEL: + bit_size: 1 + variants: + - description: DSI-PHY used as DSI byte lane clock source (usual case) + name: DSI_PHY + value: 0 + - description: PLLR used as DSI byte lane clock source, used in case DSI PLL and + DSI-PHY are off (low power mode) + name: PLLR + value: 1 +enum/FMPICSEL: + bit_size: 2 + variants: + - description: APB clock selected as I2C clock + name: APB + value: 0 + - description: System clock selected as I2C clock + name: SYSCLK + value: 1 + - description: HSI clock selected as I2C clock + name: HSI + value: 2 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: SYSCLK not divided - value: 0 - - name: Div2 - description: SYSCLK divided by 2 - value: 8 - - name: Div4 - description: SYSCLK divided by 4 - value: 9 - - name: Div8 - description: SYSCLK divided by 8 - value: 10 - - name: Div16 - description: SYSCLK divided by 16 - value: 11 - - name: Div64 - description: SYSCLK divided by 64 - value: 12 - - name: Div128 - description: SYSCLK divided by 128 - value: 13 - - name: Div256 - description: SYSCLK divided by 256 - value: 14 - - name: Div512 - description: SYSCLK divided by 512 - value: 15 + - description: SYSCLK not divided + name: Div1 + value: 0 + - description: SYSCLK divided by 2 + name: Div2 + value: 8 + - description: SYSCLK divided by 4 + name: Div4 + value: 9 + - description: SYSCLK divided by 8 + name: Div8 + value: 10 + - description: SYSCLK divided by 16 + name: Div16 + value: 11 + - description: SYSCLK divided by 64 + name: Div64 + value: 12 + - description: SYSCLK divided by 128 + name: Div128 + value: 13 + - description: SYSCLK divided by 256 + name: Div256 + value: 14 + - description: SYSCLK divided by 512 + name: Div512 + value: 15 enum/HSEBYP: bit_size: 1 variants: - - name: NotBypassed - description: HSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: HSE crystal oscillator bypassed with external clock - value: 1 + - description: HSE crystal oscillator not bypassed + name: NotBypassed + value: 0 + - description: HSE crystal oscillator bypassed with external clock + name: Bypassed + value: 1 +enum/HSION: + bit_size: 1 + variants: + - description: Clock Off + name: 'Off' + value: 0 + - description: Clock On + name: 'On' + value: 1 +enum/HSIRDYR: + bit_size: 1 + variants: + - description: Clock not ready + name: NotReady + value: 0 + - description: Clock ready + name: Ready + value: 1 +enum/I2S1SRC: + bit_size: 2 + variants: + - description: I2Sx clock frequency = f(PLLI2S_R) + name: PLLI2SR + value: 0 + - description: I2Sx clock frequency = I2S_CKIN Alternate function input frequency + name: I2S_CKIN + value: 1 + - description: I2Sx clock frequency = f(PLL_R) + name: PLLR + value: 2 + - description: I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22]) + name: HSI_HSE + value: 3 +enum/I2SSRC: + bit_size: 1 + variants: + - description: PLLI2S clock used as I2S clock source + name: PLLI2S + value: 0 + - description: External clock mapped on the I2S_CKIN pin used as I2S clock source + name: CKIN + value: 1 enum/ISSRC: bit_size: 1 variants: - - name: PLLI2S - description: PLLI2S clock used as I2S clock source - value: 0 - - name: CKIN - description: External clock mapped on the I2S_CKIN pin used as I2S clock source - value: 1 + - description: PLLI2S clock used as I2S clock source + name: PLLI2S + value: 0 + - description: External clock mapped on the I2S_CKIN pin used as I2S clock source + name: CKIN + value: 1 +enum/LPTIMSEL: + bit_size: 2 + variants: + - description: APB1 clock (PCLK1) selected as LPTILM1 clock + name: APB1 + value: 0 + - description: LSI clock is selected as LPTILM1 clock + name: LSI + value: 1 + - description: HSI clock is selected as LPTILM1 clock + name: HSI + value: 2 + - description: LSE clock is selected as LPTILM1 clock + name: LSE + value: 3 enum/LPWRRSTFR: bit_size: 1 variants: - - name: NoReset - description: No reset has occured - value: 0 - - name: Reset - description: A reset has occured - value: 1 + - description: No reset has occured + name: NoReset + value: 0 + - description: A reset has occured + name: Reset + value: 1 enum/LSEBYP: bit_size: 1 variants: - - name: NotBypassed - description: LSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: LSE crystal oscillator bypassed with external clock - value: 1 + - description: LSE crystal oscillator not bypassed + name: NotBypassed + value: 0 + - description: LSE crystal oscillator bypassed with external clock + name: Bypassed + value: 1 +enum/LSEMOD: + bit_size: 1 + variants: + - description: LSE oscillator low power mode selection + name: Low + value: 0 + - description: LSE oscillator high drive mode selection + name: High + value: 1 enum/LSEON: bit_size: 1 variants: - - name: "Off" - description: LSE oscillator Off - value: 0 - - name: "On" - description: LSE oscillator On - value: 1 + - description: LSE oscillator Off + name: 'Off' + value: 0 + - description: LSE oscillator On + name: 'On' + value: 1 enum/LSERDYR: bit_size: 1 variants: - - name: NotReady - description: LSE oscillator not ready - value: 0 - - name: Ready - description: LSE oscillator ready - value: 1 + - description: LSE oscillator not ready + name: NotReady + value: 0 + - description: LSE oscillator ready + name: Ready + value: 1 enum/LSION: bit_size: 1 variants: - - name: "Off" - description: LSI oscillator Off - value: 0 - - name: "On" - description: LSI oscillator On - value: 1 + - description: LSI oscillator Off + name: 'Off' + value: 0 + - description: LSI oscillator On + name: 'On' + value: 1 enum/LSIRDYR: bit_size: 1 variants: - - name: NotReady - description: LSI oscillator not ready - value: 0 - - name: Ready - description: LSI oscillator ready - value: 1 + - description: LSI oscillator not ready + name: NotReady + value: 0 + - description: LSI oscillator ready + name: Ready + value: 1 enum/MCO1: bit_size: 2 variants: - - name: HSI - description: HSI clock selected - value: 0 - - name: LSE - description: LSE oscillator selected - value: 1 - - name: HSE - description: HSE oscillator clock selected - value: 2 - - name: PLL - description: PLL clock selected - value: 3 + - description: HSI clock selected + name: HSI + value: 0 + - description: LSE oscillator selected + name: LSE + value: 1 + - description: HSE oscillator clock selected + name: HSE + value: 2 + - description: PLL clock selected + name: PLL + value: 3 enum/MCO2: bit_size: 2 variants: - - name: SYSCLK - description: System clock (SYSCLK) selected - value: 0 - - name: PLLI2S - description: PLLI2S clock selected - value: 1 - - name: HSE - description: HSE oscillator clock selected - value: 2 - - name: PLL - description: PLL clock selected - value: 3 + - description: System clock (SYSCLK) selected + name: SYSCLK + value: 0 + - description: PLLI2S clock selected + name: PLLI2S + value: 1 + - description: HSE oscillator clock selected + name: HSE + value: 2 + - description: PLL clock selected + name: PLL + value: 3 enum/MCOPRE: bit_size: 3 variants: - - name: Div1 - description: No division - value: 0 - - name: Div2 - description: Division by 2 - value: 4 - - name: Div3 - description: Division by 3 - value: 5 - - name: Div4 - description: Division by 4 - value: 6 - - name: Div5 - description: Division by 5 - value: 7 + - description: No division + name: Div1 + value: 0 + - description: Division by 2 + name: Div2 + value: 4 + - description: Division by 3 + name: Div3 + value: 5 + - description: Division by 4 + name: Div4 + value: 6 + - description: Division by 5 + name: Div5 + value: 7 +enum/PLLDIVR: + bit_size: 5 + variants: + - description: PLLSAIDIVQ = /1 + name: Div1 + value: 0 + - description: PLLSAIDIVQ = /2 + name: Div2 + value: 1 + - description: PLLSAIDIVQ = /3 + name: Div3 + value: 2 + - description: PLLSAIDIVQ = /4 + name: Div4 + value: 3 + - description: PLLSAIDIVQ = /5 + name: Div5 + value: 4 + - description: PLLSAIDIVQ = /6 + name: Div6 + value: 5 + - description: PLLSAIDIVQ = /7 + name: Div7 + value: 6 + - description: PLLSAIDIVQ = /8 + name: Div8 + value: 7 + - description: PLLSAIDIVQ = /9 + name: Div9 + value: 8 + - description: PLLSAIDIVQ = /10 + name: Div10 + value: 9 + - description: PLLSAIDIVQ = /11 + name: Div11 + value: 10 + - description: PLLSAIDIVQ = /12 + name: Div12 + value: 11 + - description: PLLSAIDIVQ = /13 + name: Div13 + value: 12 + - description: PLLSAIDIVQ = /14 + name: Div14 + value: 13 + - description: PLLSAIDIVQ = /15 + name: Div15 + value: 14 + - description: PLLSAIDIVQ = /16 + name: Div16 + value: 15 + - description: PLLSAIDIVQ = /17 + name: Div17 + value: 16 + - description: PLLSAIDIVQ = /18 + name: Div18 + value: 17 + - description: PLLSAIDIVQ = /19 + name: Div19 + value: 18 + - description: PLLSAIDIVQ = /20 + name: Div20 + value: 19 + - description: PLLSAIDIVQ = /21 + name: Div21 + value: 20 + - description: PLLSAIDIVQ = /22 + name: Div22 + value: 21 + - description: PLLSAIDIVQ = /23 + name: Div23 + value: 22 + - description: PLLSAIDIVQ = /24 + name: Div24 + value: 23 + - description: PLLSAIDIVQ = /25 + name: Div25 + value: 24 + - description: PLLSAIDIVQ = /26 + name: Div26 + value: 25 + - description: PLLSAIDIVQ = /27 + name: Div27 + value: 26 + - description: PLLSAIDIVQ = /28 + name: Div28 + value: 27 + - description: PLLSAIDIVQ = /29 + name: Div29 + value: 28 + - description: PLLSAIDIVQ = /30 + name: Div30 + value: 29 + - description: PLLSAIDIVQ = /31 + name: Div31 + value: 30 + - description: PLLSAIDIVQ = /32 + name: Div32 + value: 31 enum/PLLISDIVQ: bit_size: 5 variants: - - name: Div1 - description: PLLI2SDIVQ = /1 - value: 0 - - name: Div2 - description: PLLI2SDIVQ = /2 - value: 1 - - name: Div3 - description: PLLI2SDIVQ = /3 - value: 2 - - name: Div4 - description: PLLI2SDIVQ = /4 - value: 3 - - name: Div5 - description: PLLI2SDIVQ = /5 - value: 4 - - name: Div6 - description: PLLI2SDIVQ = /6 - value: 5 - - name: Div7 - description: PLLI2SDIVQ = /7 - value: 6 - - name: Div8 - description: PLLI2SDIVQ = /8 - value: 7 - - name: Div9 - description: PLLI2SDIVQ = /9 - value: 8 - - name: Div10 - description: PLLI2SDIVQ = /10 - value: 9 - - name: Div11 - description: PLLI2SDIVQ = /11 - value: 10 - - name: Div12 - description: PLLI2SDIVQ = /12 - value: 11 - - name: Div13 - description: PLLI2SDIVQ = /13 - value: 12 - - name: Div14 - description: PLLI2SDIVQ = /14 - value: 13 - - name: Div15 - description: PLLI2SDIVQ = /15 - value: 14 - - name: Div16 - description: PLLI2SDIVQ = /16 - value: 15 - - name: Div17 - description: PLLI2SDIVQ = /17 - value: 16 - - name: Div18 - description: PLLI2SDIVQ = /18 - value: 17 - - name: Div19 - description: PLLI2SDIVQ = /19 - value: 18 - - name: Div20 - description: PLLI2SDIVQ = /20 - value: 19 - - name: Div21 - description: PLLI2SDIVQ = /21 - value: 20 - - name: Div22 - description: PLLI2SDIVQ = /22 - value: 21 - - name: Div23 - description: PLLI2SDIVQ = /23 - value: 22 - - name: Div24 - description: PLLI2SDIVQ = /24 - value: 23 - - name: Div25 - description: PLLI2SDIVQ = /25 - value: 24 - - name: Div26 - description: PLLI2SDIVQ = /26 - value: 25 - - name: Div27 - description: PLLI2SDIVQ = /27 - value: 26 - - name: Div28 - description: PLLI2SDIVQ = /28 - value: 27 - - name: Div29 - description: PLLI2SDIVQ = /29 - value: 28 - - name: Div30 - description: PLLI2SDIVQ = /30 - value: 29 - - name: Div31 - description: PLLI2SDIVQ = /31 - value: 30 - - name: Div32 - description: PLLI2SDIVQ = /32 - value: 31 + - description: PLLI2SDIVQ = /1 + name: Div1 + value: 0 + - description: PLLI2SDIVQ = /2 + name: Div2 + value: 1 + - description: PLLI2SDIVQ = /3 + name: Div3 + value: 2 + - description: PLLI2SDIVQ = /4 + name: Div4 + value: 3 + - description: PLLI2SDIVQ = /5 + name: Div5 + value: 4 + - description: PLLI2SDIVQ = /6 + name: Div6 + value: 5 + - description: PLLI2SDIVQ = /7 + name: Div7 + value: 6 + - description: PLLI2SDIVQ = /8 + name: Div8 + value: 7 + - description: PLLI2SDIVQ = /9 + name: Div9 + value: 8 + - description: PLLI2SDIVQ = /10 + name: Div10 + value: 9 + - description: PLLI2SDIVQ = /11 + name: Div11 + value: 10 + - description: PLLI2SDIVQ = /12 + name: Div12 + value: 11 + - description: PLLI2SDIVQ = /13 + name: Div13 + value: 12 + - description: PLLI2SDIVQ = /14 + name: Div14 + value: 13 + - description: PLLI2SDIVQ = /15 + name: Div15 + value: 14 + - description: PLLI2SDIVQ = /16 + name: Div16 + value: 15 + - description: PLLI2SDIVQ = /17 + name: Div17 + value: 16 + - description: PLLI2SDIVQ = /18 + name: Div18 + value: 17 + - description: PLLI2SDIVQ = /19 + name: Div19 + value: 18 + - description: PLLI2SDIVQ = /20 + name: Div20 + value: 19 + - description: PLLI2SDIVQ = /21 + name: Div21 + value: 20 + - description: PLLI2SDIVQ = /22 + name: Div22 + value: 21 + - description: PLLI2SDIVQ = /23 + name: Div23 + value: 22 + - description: PLLI2SDIVQ = /24 + name: Div24 + value: 23 + - description: PLLI2SDIVQ = /25 + name: Div25 + value: 24 + - description: PLLI2SDIVQ = /26 + name: Div26 + value: 25 + - description: PLLI2SDIVQ = /27 + name: Div27 + value: 26 + - description: PLLI2SDIVQ = /28 + name: Div28 + value: 27 + - description: PLLI2SDIVQ = /29 + name: Div29 + value: 28 + - description: PLLI2SDIVQ = /30 + name: Div30 + value: 29 + - description: PLLI2SDIVQ = /31 + name: Div31 + value: 30 + - description: PLLI2SDIVQ = /32 + name: Div32 + value: 31 +enum/PLLISDIVR: + bit_size: 5 + variants: + - description: PLLI2SDIVQ = /1 + name: Div1 + value: 0 + - description: PLLI2SDIVQ = /2 + name: Div2 + value: 1 + - description: PLLI2SDIVQ = /3 + name: Div3 + value: 2 + - description: PLLI2SDIVQ = /4 + name: Div4 + value: 3 + - description: PLLI2SDIVQ = /5 + name: Div5 + value: 4 + - description: PLLI2SDIVQ = /6 + name: Div6 + value: 5 + - description: PLLI2SDIVQ = /7 + name: Div7 + value: 6 + - description: PLLI2SDIVQ = /8 + name: Div8 + value: 7 + - description: PLLI2SDIVQ = /9 + name: Div9 + value: 8 + - description: PLLI2SDIVQ = /10 + name: Div10 + value: 9 + - description: PLLI2SDIVQ = /11 + name: Div11 + value: 10 + - description: PLLI2SDIVQ = /12 + name: Div12 + value: 11 + - description: PLLI2SDIVQ = /13 + name: Div13 + value: 12 + - description: PLLI2SDIVQ = /14 + name: Div14 + value: 13 + - description: PLLI2SDIVQ = /15 + name: Div15 + value: 14 + - description: PLLI2SDIVQ = /16 + name: Div16 + value: 15 + - description: PLLI2SDIVQ = /17 + name: Div17 + value: 16 + - description: PLLI2SDIVQ = /18 + name: Div18 + value: 17 + - description: PLLI2SDIVQ = /19 + name: Div19 + value: 18 + - description: PLLI2SDIVQ = /20 + name: Div20 + value: 19 + - description: PLLI2SDIVQ = /21 + name: Div21 + value: 20 + - description: PLLI2SDIVQ = /22 + name: Div22 + value: 21 + - description: PLLI2SDIVQ = /23 + name: Div23 + value: 22 + - description: PLLI2SDIVQ = /24 + name: Div24 + value: 23 + - description: PLLI2SDIVQ = /25 + name: Div25 + value: 24 + - description: PLLI2SDIVQ = /26 + name: Div26 + value: 25 + - description: PLLI2SDIVQ = /27 + name: Div27 + value: 26 + - description: PLLI2SDIVQ = /28 + name: Div28 + value: 27 + - description: PLLI2SDIVQ = /29 + name: Div29 + value: 28 + - description: PLLI2SDIVQ = /30 + name: Div30 + value: 29 + - description: PLLI2SDIVQ = /31 + name: Div31 + value: 30 + - description: PLLI2SDIVQ = /32 + name: Div32 + value: 31 enum/PLLISON: bit_size: 1 variants: - - name: "Off" - description: Clock Off - value: 0 - - name: "On" - description: Clock On - value: 1 + - description: Clock Off + name: 'Off' + value: 0 + - description: Clock On + name: 'On' + value: 1 +enum/PLLISP: + bit_size: 2 + variants: + - description: PLL*P=2 + name: Div2 + value: 0 + - description: PLL*P=4 + name: Div4 + value: 1 + - description: PLL*P=6 + name: Div6 + value: 2 + - description: PLL*P=8 + name: Div8 + value: 3 enum/PLLISRDYCW: bit_size: 1 variants: - - name: Clear - description: Clear interrupt flag - value: 1 + - description: Clear interrupt flag + name: Clear + value: 1 enum/PLLISRDYFR: bit_size: 1 variants: - - name: NotInterrupted - description: No clock ready interrupt - value: 0 - - name: Interrupted - description: Clock ready interrupt - value: 1 + - description: No clock ready interrupt + name: NotInterrupted + value: 0 + - description: Clock ready interrupt + name: Interrupted + value: 1 enum/PLLISRDYIE: bit_size: 1 variants: - - name: Disabled - description: Interrupt disabled - value: 0 - - name: Enabled - description: Interrupt enabled - value: 1 + - description: Interrupt disabled + name: Disabled + value: 0 + - description: Interrupt enabled + name: Enabled + value: 1 enum/PLLISRDYR: bit_size: 1 variants: - - name: NotReady - description: Clock not ready - value: 0 - - name: Ready - description: Clock ready - value: 1 + - description: Clock not ready + name: NotReady + value: 0 + - description: Clock ready + name: Ready + value: 1 +enum/PLLISSRC: + bit_size: 1 + variants: + - description: HSE or HSI depending on PLLSRC of PLLCFGR + name: HSE_HSI + value: 0 + - description: External AFI clock (CK_PLLI2S_EXT) selected as PLL clock entry + name: External + value: 1 +enum/PLLON: + bit_size: 1 + variants: + - description: Clock Off + name: 'Off' + value: 0 + - description: Clock On + name: 'On' + value: 1 enum/PLLP: bit_size: 2 variants: - - name: Div2 - description: PLLP=2 - value: 0 - - name: Div4 - description: PLLP=4 - value: 1 - - name: Div6 - description: PLLP=6 - value: 2 - - name: Div8 - description: PLLP=8 - value: 3 + - description: PLLP=2 + name: Div2 + value: 0 + - description: PLLP=4 + name: Div4 + value: 1 + - description: PLLP=6 + name: Div6 + value: 2 + - description: PLLP=8 + name: Div8 + value: 3 +enum/PLLRDYFR: + bit_size: 1 + variants: + - description: No clock ready interrupt + name: NotInterrupted + value: 0 + - description: Clock ready interrupt + name: Interrupted + value: 1 +enum/PLLRDYIE: + bit_size: 1 + variants: + - description: Interrupt disabled + name: Disabled + value: 0 + - description: Interrupt enabled + name: Enabled + value: 1 +enum/PLLRDYR: + bit_size: 1 + variants: + - description: Clock not ready + name: NotReady + value: 0 + - description: Clock ready + name: Ready + value: 1 enum/PLLSAIDIVQ: bit_size: 5 variants: - - name: Div1 - description: PLLSAIDIVQ = /1 - value: 0 - - name: Div2 - description: PLLSAIDIVQ = /2 - value: 1 - - name: Div3 - description: PLLSAIDIVQ = /3 - value: 2 - - name: Div4 - description: PLLSAIDIVQ = /4 - value: 3 - - name: Div5 - description: PLLSAIDIVQ = /5 - value: 4 - - name: Div6 - description: PLLSAIDIVQ = /6 - value: 5 - - name: Div7 - description: PLLSAIDIVQ = /7 - value: 6 - - name: Div8 - description: PLLSAIDIVQ = /8 - value: 7 - - name: Div9 - description: PLLSAIDIVQ = /9 - value: 8 - - name: Div10 - description: PLLSAIDIVQ = /10 - value: 9 - - name: Div11 - description: PLLSAIDIVQ = /11 - value: 10 - - name: Div12 - description: PLLSAIDIVQ = /12 - value: 11 - - name: Div13 - description: PLLSAIDIVQ = /13 - value: 12 - - name: Div14 - description: PLLSAIDIVQ = /14 - value: 13 - - name: Div15 - description: PLLSAIDIVQ = /15 - value: 14 - - name: Div16 - description: PLLSAIDIVQ = /16 - value: 15 - - name: Div17 - description: PLLSAIDIVQ = /17 - value: 16 - - name: Div18 - description: PLLSAIDIVQ = /18 - value: 17 - - name: Div19 - description: PLLSAIDIVQ = /19 - value: 18 - - name: Div20 - description: PLLSAIDIVQ = /20 - value: 19 - - name: Div21 - description: PLLSAIDIVQ = /21 - value: 20 - - name: Div22 - description: PLLSAIDIVQ = /22 - value: 21 - - name: Div23 - description: PLLSAIDIVQ = /23 - value: 22 - - name: Div24 - description: PLLSAIDIVQ = /24 - value: 23 - - name: Div25 - description: PLLSAIDIVQ = /25 - value: 24 - - name: Div26 - description: PLLSAIDIVQ = /26 - value: 25 - - name: Div27 - description: PLLSAIDIVQ = /27 - value: 26 - - name: Div28 - description: PLLSAIDIVQ = /28 - value: 27 - - name: Div29 - description: PLLSAIDIVQ = /29 - value: 28 - - name: Div30 - description: PLLSAIDIVQ = /30 - value: 29 - - name: Div31 - description: PLLSAIDIVQ = /31 - value: 30 - - name: Div32 - description: PLLSAIDIVQ = /32 - value: 31 + - description: PLLSAIDIVQ = /1 + name: Div1 + value: 0 + - description: PLLSAIDIVQ = /2 + name: Div2 + value: 1 + - description: PLLSAIDIVQ = /3 + name: Div3 + value: 2 + - description: PLLSAIDIVQ = /4 + name: Div4 + value: 3 + - description: PLLSAIDIVQ = /5 + name: Div5 + value: 4 + - description: PLLSAIDIVQ = /6 + name: Div6 + value: 5 + - description: PLLSAIDIVQ = /7 + name: Div7 + value: 6 + - description: PLLSAIDIVQ = /8 + name: Div8 + value: 7 + - description: PLLSAIDIVQ = /9 + name: Div9 + value: 8 + - description: PLLSAIDIVQ = /10 + name: Div10 + value: 9 + - description: PLLSAIDIVQ = /11 + name: Div11 + value: 10 + - description: PLLSAIDIVQ = /12 + name: Div12 + value: 11 + - description: PLLSAIDIVQ = /13 + name: Div13 + value: 12 + - description: PLLSAIDIVQ = /14 + name: Div14 + value: 13 + - description: PLLSAIDIVQ = /15 + name: Div15 + value: 14 + - description: PLLSAIDIVQ = /16 + name: Div16 + value: 15 + - description: PLLSAIDIVQ = /17 + name: Div17 + value: 16 + - description: PLLSAIDIVQ = /18 + name: Div18 + value: 17 + - description: PLLSAIDIVQ = /19 + name: Div19 + value: 18 + - description: PLLSAIDIVQ = /20 + name: Div20 + value: 19 + - description: PLLSAIDIVQ = /21 + name: Div21 + value: 20 + - description: PLLSAIDIVQ = /22 + name: Div22 + value: 21 + - description: PLLSAIDIVQ = /23 + name: Div23 + value: 22 + - description: PLLSAIDIVQ = /24 + name: Div24 + value: 23 + - description: PLLSAIDIVQ = /25 + name: Div25 + value: 24 + - description: PLLSAIDIVQ = /26 + name: Div26 + value: 25 + - description: PLLSAIDIVQ = /27 + name: Div27 + value: 26 + - description: PLLSAIDIVQ = /28 + name: Div28 + value: 27 + - description: PLLSAIDIVQ = /29 + name: Div29 + value: 28 + - description: PLLSAIDIVQ = /30 + name: Div30 + value: 29 + - description: PLLSAIDIVQ = /31 + name: Div31 + value: 30 + - description: PLLSAIDIVQ = /32 + name: Div32 + value: 31 enum/PLLSAIDIVR: bit_size: 2 variants: - - name: Div2 - description: PLLSAIDIVR = /2 - value: 0 - - name: Div4 - description: PLLSAIDIVR = /4 - value: 1 - - name: Div8 - description: PLLSAIDIVR = /8 - value: 2 - - name: Div16 - description: PLLSAIDIVR = /16 - value: 3 + - description: PLLSAIDIVR = /2 + name: Div2 + value: 0 + - description: PLLSAIDIVR = /4 + name: Div4 + value: 1 + - description: PLLSAIDIVR = /8 + name: Div8 + value: 2 + - description: PLLSAIDIVR = /16 + name: Div16 + value: 3 +enum/PLLSAIP: + bit_size: 2 + variants: + - description: PLL*P=2 + name: Div2 + value: 0 + - description: PLL*P=4 + name: Div4 + value: 1 + - description: PLL*P=6 + name: Div6 + value: 2 + - description: PLL*P=8 + name: Div8 + value: 3 +enum/PLLSAIRDYCW: + bit_size: 1 + variants: + - description: Clear interrupt flag + name: Clear + value: 1 +enum/PLLSAIRDYFR: + bit_size: 1 + variants: + - description: No clock ready interrupt + name: NotInterrupted + value: 0 + - description: Clock ready interrupt + name: Interrupted + value: 1 +enum/PLLSAIRDYIE: + bit_size: 1 + variants: + - description: Interrupt disabled + name: Disabled + value: 0 + - description: Interrupt enabled + name: Enabled + value: 1 enum/PLLSRC: bit_size: 1 variants: - - name: HSI - description: HSI clock selected as PLL and PLLI2S clock entry - value: 0 - - name: HSE - description: HSE oscillator clock selected as PLL and PLLI2S clock entry - value: 1 + - description: HSI clock selected as PLL and PLLI2S clock entry + name: HSI + value: 0 + - description: HSE oscillator clock selected as PLL and PLLI2S clock entry + name: HSE + value: 1 enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK divided by 2 - value: 4 - - name: Div4 - description: HCLK divided by 4 - value: 5 - - name: Div8 - description: HCLK divided by 8 - value: 6 - - name: Div16 - description: HCLK divided by 16 - value: 7 + - description: HCLK not divided + name: Div1 + value: 0 + - description: HCLK divided by 2 + name: Div2 + value: 4 + - description: HCLK divided by 4 + name: Div4 + value: 5 + - description: HCLK divided by 8 + name: Div8 + value: 6 + - description: HCLK divided by 16 + name: Div16 + value: 7 enum/RMVFW: bit_size: 1 variants: - - name: Clear - description: Clears the reset flag - value: 1 + - description: Clears the reset flag + name: Clear + value: 1 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: HSE oscillator clock divided by a prescaler used as RTC clock - value: 3 + - description: No clock + name: NoClock + value: 0 + - description: LSE oscillator clock used as RTC clock + name: LSE + value: 1 + - description: LSI oscillator clock used as RTC clock + name: LSI + value: 2 + - description: HSE oscillator clock divided by a prescaler used as RTC clock + name: HSE + value: 3 +enum/SAI1SRC: + bit_size: 2 + variants: + - description: SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + name: PLLSAI + value: 0 + - description: SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + name: PLLI2S + value: 1 + - description: SAI1 clock frequency = f(PLL_R) + name: PLLR + value: 2 + - description: I2S_CKIN Alternate function input frequency + name: I2S_CKIN + value: 3 +enum/SAI2SRC: + bit_size: 2 + variants: + - description: SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + name: PLLSAI + value: 0 + - description: SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + name: PLLI2S + value: 1 + - description: SAI2 clock frequency = f(PLL_R) + name: PLLR + value: 2 + - description: SAI2 clock frequency = Alternate function input frequency + name: HSI_HSE + value: 3 enum/SAIASRC: bit_size: 2 variants: - - name: PLLSAI - description: SAI1-A clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - value: 0 - - name: PLLI2S - description: SAI1-A clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - value: 1 - - name: I2S_CKIN - description: SAI1-A clock frequency = Alternate function input frequency - value: 2 + - description: SAI1-A clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + name: PLLSAI + value: 0 + - description: SAI1-A clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + name: PLLI2S + value: 1 + - description: SAI1-A clock frequency = Alternate function input frequency + name: I2S_CKIN + value: 2 enum/SAIBSRC: bit_size: 2 variants: - - name: PLLSAI - description: SAI1-B clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ - value: 0 - - name: PLLI2S - description: SAI1-B clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ - value: 1 - - name: I2S_CKIN - description: SAI1-B clock frequency = Alternate function input frequency - value: 2 + - description: SAI1-B clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + name: PLLSAI + value: 0 + - description: SAI1-B clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + name: PLLI2S + value: 1 + - description: SAI1-B clock frequency = Alternate function input frequency + name: I2S_CKIN + value: 2 +enum/SDIOSEL: + bit_size: 1 + variants: + - description: 48 MHz clock is selected as SD clock + name: CK48M + value: 0 + - description: System clock is selected as SD clock + name: SYSCLK + value: 1 +enum/SPDIFRXSEL: + bit_size: 1 + variants: + - description: SPDIF-Rx clock from PLL is selected + name: PLL + value: 0 + - description: SPDIF-Rx clock from PLLI2S is selected + name: PLLI2S + value: 1 enum/SPREADSEL: bit_size: 1 variants: - - name: Center - description: Center spread - value: 0 - - name: Down - description: Down spread - value: 1 + - description: Center spread + name: Center + value: 0 + - description: Down spread + name: Down + value: 1 enum/SW: bit_size: 2 variants: - - name: HSI - description: HSI selected as system clock - value: 0 - - name: HSE - description: HSE selected as system clock - value: 1 - - name: PLL - description: PLL selected as system clock - value: 2 + - description: HSI selected as system clock + name: HSI + value: 0 + - description: HSE selected as system clock + name: HSE + value: 1 + - description: PLL selected as system clock + name: PLL + value: 2 enum/SWSR: bit_size: 2 variants: - - name: HSI - description: HSI oscillator used as system clock - value: 0 - - name: HSE - description: HSE oscillator used as system clock - value: 1 - - name: PLL - description: PLL used as system clock - value: 2 + - description: HSI oscillator used as system clock + name: HSI + value: 0 + - description: HSE oscillator used as system clock + name: HSE + value: 1 + - description: PLL used as system clock + name: PLL + value: 2 enum/TIMPRE: bit_size: 1 variants: - - name: Mul2 - description: "If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx" - value: 0 - - name: Mul4 - description: "If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx" - value: 1 + - description: If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, + TIMxCLK = 2xPCLKx + name: Mul2 + value: 0 + - description: If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, + TIMxCLK = 4xPCLKx + name: Mul4 + value: 1 +fieldset/AHB1ENR: + description: AHB1 peripheral clock register + fields: + - bit_offset: 0 + bit_size: 1 + description: IO port A clock enable + name: GPIOAEN + - bit_offset: 1 + bit_size: 1 + description: IO port B clock enable + name: GPIOBEN + - bit_offset: 2 + bit_size: 1 + description: IO port C clock enable + name: GPIOCEN + - bit_offset: 3 + bit_size: 1 + description: IO port D clock enable + name: GPIODEN + - bit_offset: 4 + bit_size: 1 + description: IO port E clock enable + name: GPIOEEN + - bit_offset: 7 + bit_size: 1 + description: IO port H clock enable + name: GPIOHEN + - bit_offset: 12 + bit_size: 1 + description: CRC clock enable + name: CRCEN + - bit_offset: 21 + bit_size: 1 + description: DMA1 clock enable + name: DMA1EN + - bit_offset: 22 + bit_size: 1 + description: DMA2 clock enable + name: DMA2EN + - bit_offset: 5 + bit_size: 1 + description: IO port F clock enable + name: GPIOFEN + - bit_offset: 6 + bit_size: 1 + description: IO port G clock enable + name: GPIOGEN + - bit_offset: 8 + bit_size: 1 + description: IO port I clock enable + name: GPIOIEN + - bit_offset: 18 + bit_size: 1 + description: Backup SRAM interface clock enable + name: BKPSRAMEN + - bit_offset: 25 + bit_size: 1 + description: Ethernet MAC clock enable + name: ETHMACEN + - bit_offset: 26 + bit_size: 1 + description: Ethernet Transmission clock enable + name: ETHMACTXEN + - bit_offset: 27 + bit_size: 1 + description: Ethernet Reception clock enable + name: ETHMACRXEN + - bit_offset: 28 + bit_size: 1 + description: Ethernet PTP clock enable + name: ETHMACPTPEN + - bit_offset: 29 + bit_size: 1 + description: USB OTG HS clock enable + name: OTGHSEN + - bit_offset: 30 + bit_size: 1 + description: USB OTG HSULPI clock enable + name: OTGHSULPIEN + - bit_offset: 31 + bit_size: 1 + description: RNG clock enable + name: RNGEN + - bit_offset: 9 + bit_size: 1 + description: IO port J clock enable + name: GPIOJEN + - bit_offset: 10 + bit_size: 1 + description: IO port K clock enable + name: GPIOKEN + - bit_offset: 23 + bit_size: 1 + description: DMA2D clock enable + name: DMA2DEN + - bit_offset: 20 + bit_size: 1 + description: CCM data RAM clock enable + name: CCMDATARAMEN +fieldset/AHB1LPENR: + description: AHB1 peripheral clock enable in low power mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: IO port A clock enable during sleep mode + name: GPIOALPEN + - bit_offset: 1 + bit_size: 1 + description: IO port B clock enable during Sleep mode + name: GPIOBLPEN + - bit_offset: 2 + bit_size: 1 + description: IO port C clock enable during Sleep mode + name: GPIOCLPEN + - bit_offset: 3 + bit_size: 1 + description: IO port D clock enable during Sleep mode + name: GPIODLPEN + - bit_offset: 4 + bit_size: 1 + description: IO port E clock enable during Sleep mode + name: GPIOELPEN + - bit_offset: 7 + bit_size: 1 + description: IO port H clock enable during Sleep mode + name: GPIOHLPEN + - bit_offset: 12 + bit_size: 1 + description: CRC clock enable during Sleep mode + name: CRCLPEN + - bit_offset: 15 + bit_size: 1 + description: Flash interface clock enable during Sleep mode + name: FLITFLPEN + - bit_offset: 16 + bit_size: 1 + description: SRAM 1interface clock enable during Sleep mode + name: SRAM1LPEN + - bit_offset: 21 + bit_size: 1 + description: DMA1 clock enable during Sleep mode + name: DMA1LPEN + - bit_offset: 22 + bit_size: 1 + description: DMA2 clock enable during Sleep mode + name: DMA2LPEN + - bit_offset: 5 + bit_size: 1 + description: IO port F clock enable during Sleep mode + name: GPIOFLPEN + - bit_offset: 6 + bit_size: 1 + description: IO port G clock enable during Sleep mode + name: GPIOGLPEN + - bit_offset: 8 + bit_size: 1 + description: IO port I clock enable during Sleep mode + name: GPIOILPEN + - bit_offset: 17 + bit_size: 1 + description: SRAM 2 interface clock enable during Sleep mode + name: SRAM2LPEN + - bit_offset: 18 + bit_size: 1 + description: Backup SRAM interface clock enable during Sleep mode + name: BKPSRAMLPEN + - bit_offset: 25 + bit_size: 1 + description: Ethernet MAC clock enable during Sleep mode + name: ETHMACLPEN + - bit_offset: 26 + bit_size: 1 + description: Ethernet transmission clock enable during Sleep mode + name: ETHMACTXLPEN + - bit_offset: 27 + bit_size: 1 + description: Ethernet reception clock enable during Sleep mode + name: ETHMACRXLPEN + - bit_offset: 28 + bit_size: 1 + description: Ethernet PTP clock enable during Sleep mode + name: ETHMACPTPLPEN + - bit_offset: 29 + bit_size: 1 + description: USB OTG HS clock enable during Sleep mode + name: OTGHSLPEN + - bit_offset: 30 + bit_size: 1 + description: USB OTG HS ULPI clock enable during Sleep mode + name: OTGHSULPILPEN + - bit_offset: 31 + bit_size: 1 + description: RNG clock enable during sleep mode + name: RNGLPEN + - bit_offset: 9 + bit_size: 1 + description: IO port J clock enable during Sleep mode + name: GPIOJLPEN + - bit_offset: 10 + bit_size: 1 + description: IO port K clock enable during Sleep mode + name: GPIOKLPEN + - bit_offset: 19 + bit_size: 1 + description: SRAM 3 interface clock enable during Sleep mode + name: SRAM3LPEN + - bit_offset: 23 + bit_size: 1 + description: DMA2D clock enable during Sleep mode + name: DMA2DLPEN +fieldset/AHB1RSTR: + description: AHB1 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: IO port A reset + name: GPIOARST + - bit_offset: 1 + bit_size: 1 + description: IO port B reset + name: GPIOBRST + - bit_offset: 2 + bit_size: 1 + description: IO port C reset + name: GPIOCRST + - bit_offset: 3 + bit_size: 1 + description: IO port D reset + name: GPIODRST + - bit_offset: 4 + bit_size: 1 + description: IO port E reset + name: GPIOERST + - bit_offset: 7 + bit_size: 1 + description: IO port H reset + name: GPIOHRST + - bit_offset: 12 + bit_size: 1 + description: CRC reset + name: CRCRST + - bit_offset: 21 + bit_size: 1 + description: DMA2 reset + name: DMA1RST + - bit_offset: 22 + bit_size: 1 + description: DMA2 reset + name: DMA2RST + - bit_offset: 5 + bit_size: 1 + description: IO port F reset + name: GPIOFRST + - bit_offset: 6 + bit_size: 1 + description: IO port G reset + name: GPIOGRST + - bit_offset: 8 + bit_size: 1 + description: IO port I reset + name: GPIOIRST + - bit_offset: 25 + bit_size: 1 + description: Ethernet MAC reset + name: ETHMACRST + - bit_offset: 29 + bit_size: 1 + description: USB OTG HS module reset + name: OTGHSRST + - bit_offset: 31 + bit_size: 1 + description: RNGRST + name: RNGRST + - bit_offset: 9 + bit_size: 1 + description: IO port J reset + name: GPIOJRST + - bit_offset: 10 + bit_size: 1 + description: IO port K reset + name: GPIOKRST + - bit_offset: 23 + bit_size: 1 + description: DMA2D reset + name: DMA2DRST +fieldset/AHB2ENR: + description: AHB2 peripheral clock enable register + fields: + - bit_offset: 7 + bit_size: 1 + description: USB OTG FS clock enable + name: OTGFSEN + - bit_offset: 0 + bit_size: 1 + description: Camera interface enable + name: DCMIEN + - bit_offset: 6 + bit_size: 1 + description: Random number generator clock enable + name: RNGEN + - bit_offset: 4 + bit_size: 1 + description: CRYP clock enable + name: CRYPEN + - bit_offset: 5 + bit_size: 1 + description: Hash modules clock enable + name: HASHEN +fieldset/AHB2LPENR: + description: AHB2 peripheral clock enable in low power mode register + fields: + - bit_offset: 7 + bit_size: 1 + description: USB OTG FS clock enable during Sleep mode + name: OTGFSLPEN + - bit_offset: 0 + bit_size: 1 + description: Camera interface enable during Sleep mode + name: DCMILPEN + - bit_offset: 6 + bit_size: 1 + description: Random number generator clock enable during Sleep mode + name: RNGLPEN + - bit_offset: 0 + bit_size: 1 + description: Flexible memory controller module clock enable during Sleep mode + name: FSMCLPEN + - bit_offset: 1 + bit_size: 1 + description: QUADSPI memory controller module clock enable during Sleep mode + name: QSPILPEN + - bit_offset: 4 + bit_size: 1 + description: Cryptography modules clock enable during Sleep mode + name: CRYPLPEN + - bit_offset: 5 + bit_size: 1 + description: Hash modules clock enable during Sleep mode + name: HASHLPEN +fieldset/AHB2RSTR: + description: AHB2 peripheral reset register + fields: + - bit_offset: 7 + bit_size: 1 + description: USB OTG FS module reset + name: OTGFSRST + - bit_offset: 0 + bit_size: 1 + description: Camera interface reset + name: DCMIRST + - bit_offset: 6 + bit_size: 1 + description: Random number generator module reset + name: RNGRST + - bit_offset: 4 + bit_size: 1 + description: CRYP module reset + name: CRYPRST + - bit_offset: 5 + bit_size: 1 + description: Hash module reset + name: HSAHRST +fieldset/AHB3ENR: + description: AHB3 peripheral clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: Flexible static memory controller module clock enable + name: FSMCEN + - bit_offset: 1 + bit_size: 1 + description: QUADSPI memory controller module clock enable + name: QSPIEN + - bit_offset: 0 + bit_size: 1 + description: Flexible static memory controller module clock enable + name: FMCEN +fieldset/AHB3LPENR: + description: AHB3 peripheral clock enable in low power mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: Flexible static memory controller module clock enable during Sleep + mode + name: FSMCLPEN + - bit_offset: 1 + bit_size: 1 + description: QUADSPI memory controller module clock enable during Sleep mode + name: QSPILPEN + - bit_offset: 0 + bit_size: 1 + description: Flexible static memory controller module clock enable during Sleep + mode + name: FMCLPEN +fieldset/AHB3RSTR: + description: AHB3 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: Flexible static memory controller module reset + name: FSMCRST + - bit_offset: 1 + bit_size: 1 + description: QUADSPI module reset + name: QSPIRST + - bit_offset: 0 + bit_size: 1 + description: Flexible static memory controller module reset + name: FMCRST +fieldset/APB1ENR: + description: APB1 peripheral clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM2 clock enable + name: TIM2EN + - bit_offset: 1 + bit_size: 1 + description: TIM3 clock enable + name: TIM3EN + - bit_offset: 2 + bit_size: 1 + description: TIM4 clock enable + name: TIM4EN + - bit_offset: 3 + bit_size: 1 + description: TIM5 clock enable + name: TIM5EN + - bit_offset: 11 + bit_size: 1 + description: Window watchdog clock enable + name: WWDGEN + - bit_offset: 14 + bit_size: 1 + description: SPI2 clock enable + name: SPI2EN + - bit_offset: 15 + bit_size: 1 + description: SPI3 clock enable + name: SPI3EN + - bit_offset: 17 + bit_size: 1 + description: USART 2 clock enable + name: USART2EN + - bit_offset: 21 + bit_size: 1 + description: I2C1 clock enable + name: I2C1EN + - bit_offset: 22 + bit_size: 1 + description: I2C2 clock enable + name: I2C2EN + - bit_offset: 23 + bit_size: 1 + description: I2C3 clock enable + name: I2C3EN + - bit_offset: 28 + bit_size: 1 + description: Power interface clock enable + name: PWREN + - bit_offset: 4 + bit_size: 1 + description: TIM6 clock enable + name: TIM6EN + - bit_offset: 5 + bit_size: 1 + description: TIM7 clock enable + name: TIM7EN + - bit_offset: 6 + bit_size: 1 + description: TIM12 clock enable + name: TIM12EN + - bit_offset: 7 + bit_size: 1 + description: TIM13 clock enable + name: TIM13EN + - bit_offset: 8 + bit_size: 1 + description: TIM14 clock enable + name: TIM14EN + - bit_offset: 18 + bit_size: 1 + description: USART3 clock enable + name: USART3EN + - bit_offset: 19 + bit_size: 1 + description: UART4 clock enable + name: UART4EN + - bit_offset: 20 + bit_size: 1 + description: UART5 clock enable + name: UART5EN + - bit_offset: 25 + bit_size: 1 + description: CAN 1 clock enable + name: CAN1EN + - bit_offset: 26 + bit_size: 1 + description: CAN 2 clock enable + name: CAN2EN + - bit_offset: 29 + bit_size: 1 + description: DAC interface clock enable + name: DACEN + - bit_offset: 9 + bit_size: 1 + description: LPTIM1 clock enable + name: LPTIM1EN + - bit_offset: 10 + bit_size: 1 + description: RTC APB clock enable + name: RTCAPBEN + - bit_offset: 24 + bit_size: 1 + description: FMPI2C1 clock enable + name: FMPI2C1EN + - bit_offset: 9 + bit_size: 1 + description: LPTimer 1 clock enable + name: LPTIMER1EN + - bit_offset: 27 + bit_size: 1 + description: CAN 3 clock enable + name: CAN3EN + - bit_offset: 30 + bit_size: 1 + description: UART7 clock enable + name: UART7EN + - bit_offset: 31 + bit_size: 1 + description: UART8 clock enable + name: UART8EN + - bit_offset: 16 + bit_size: 1 + description: SPDIF-IN clock enable + name: SPDIFEN + - bit_offset: 27 + bit_size: 1 + description: CEC interface clock enable + name: CECEN +fieldset/APB1LPENR: + description: APB1 peripheral clock enable in low power mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM2 clock enable during Sleep mode + name: TIM2LPEN + - bit_offset: 1 + bit_size: 1 + description: TIM3 clock enable during Sleep mode + name: TIM3LPEN + - bit_offset: 2 + bit_size: 1 + description: TIM4 clock enable during Sleep mode + name: TIM4LPEN + - bit_offset: 3 + bit_size: 1 + description: TIM5 clock enable during Sleep mode + name: TIM5LPEN + - bit_offset: 11 + bit_size: 1 + description: Window watchdog clock enable during Sleep mode + name: WWDGLPEN + - bit_offset: 14 + bit_size: 1 + description: SPI2 clock enable during Sleep mode + name: SPI2LPEN + - bit_offset: 15 + bit_size: 1 + description: SPI3 clock enable during Sleep mode + name: SPI3LPEN + - bit_offset: 17 + bit_size: 1 + description: USART2 clock enable during Sleep mode + name: USART2LPEN + - bit_offset: 21 + bit_size: 1 + description: I2C1 clock enable during Sleep mode + name: I2C1LPEN + - bit_offset: 22 + bit_size: 1 + description: I2C2 clock enable during Sleep mode + name: I2C2LPEN + - bit_offset: 23 + bit_size: 1 + description: I2C3 clock enable during Sleep mode + name: I2C3LPEN + - bit_offset: 28 + bit_size: 1 + description: Power interface clock enable during Sleep mode + name: PWRLPEN + - bit_offset: 4 + bit_size: 1 + description: TIM6 clock enable during Sleep mode + name: TIM6LPEN + - bit_offset: 5 + bit_size: 1 + description: TIM7 clock enable during Sleep mode + name: TIM7LPEN + - bit_offset: 6 + bit_size: 1 + description: TIM12 clock enable during Sleep mode + name: TIM12LPEN + - bit_offset: 7 + bit_size: 1 + description: TIM13 clock enable during Sleep mode + name: TIM13LPEN + - bit_offset: 8 + bit_size: 1 + description: TIM14 clock enable during Sleep mode + name: TIM14LPEN + - bit_offset: 18 + bit_size: 1 + description: USART3 clock enable during Sleep mode + name: USART3LPEN + - bit_offset: 19 + bit_size: 1 + description: UART4 clock enable during Sleep mode + name: UART4LPEN + - bit_offset: 20 + bit_size: 1 + description: UART5 clock enable during Sleep mode + name: UART5LPEN + - bit_offset: 25 + bit_size: 1 + description: CAN 1 clock enable during Sleep mode + name: CAN1LPEN + - bit_offset: 26 + bit_size: 1 + description: CAN 2 clock enable during Sleep mode + name: CAN2LPEN + - bit_offset: 29 + bit_size: 1 + description: DAC interface clock enable during Sleep mode + name: DACLPEN + - bit_offset: 9 + bit_size: 1 + description: LPTIM1 clock enable during sleep mode + name: LPTIM1LPEN + - bit_offset: 10 + bit_size: 1 + description: RTC APB clock enable during sleep mode + name: RTCAPBLPEN + - bit_offset: 24 + bit_size: 1 + description: FMPI2C1 clock enable during Sleep + name: FMPI2C1LPEN + - bit_offset: 9 + bit_size: 1 + description: TIM14 clock enable during Sleep mode + name: LPTIMER1LPEN + - bit_offset: 19 + bit_size: 1 + description: USART4 clock enable during Sleep mode + name: USART4LPEN + - bit_offset: 20 + bit_size: 1 + description: USART5 clock enable during Sleep mode + name: USART5LPEN + - bit_offset: 27 + bit_size: 1 + description: CAN3 clock enable during Sleep mode + name: CAN3LPEN + - bit_offset: 30 + bit_size: 1 + description: UART7 clock enable during Sleep mode + name: UART7LPEN + - bit_offset: 31 + bit_size: 1 + description: UART8 clock enable during Sleep mode + name: UART8LPEN + - bit_offset: 16 + bit_size: 1 + description: SPDIF clock enable during Sleep mode + name: SPDIFLPEN + - bit_offset: 27 + bit_size: 1 + description: CEC clock enable during Sleep mode + name: CECLPEN +fieldset/APB1RSTR: + description: APB1 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM2 reset + name: TIM2RST + - bit_offset: 1 + bit_size: 1 + description: TIM3 reset + name: TIM3RST + - bit_offset: 2 + bit_size: 1 + description: TIM4 reset + name: TIM4RST + - bit_offset: 3 + bit_size: 1 + description: TIM5 reset + name: TIM5RST + - bit_offset: 11 + bit_size: 1 + description: Window watchdog reset + name: WWDGRST + - bit_offset: 14 + bit_size: 1 + description: SPI 2 reset + name: SPI2RST + - bit_offset: 15 + bit_size: 1 + description: SPI 3 reset + name: SPI3RST + - bit_offset: 17 + bit_size: 1 + description: USART 2 reset + name: UART2RST + - bit_offset: 21 + bit_size: 1 + description: I2C 1 reset + name: I2C1RST + - bit_offset: 22 + bit_size: 1 + description: I2C 2 reset + name: I2C2RST + - bit_offset: 23 + bit_size: 1 + description: I2C3 reset + name: I2C3RST + - bit_offset: 28 + bit_size: 1 + description: Power interface reset + name: PWRRST + - bit_offset: 4 + bit_size: 1 + description: TIM6 reset + name: TIM6RST + - bit_offset: 5 + bit_size: 1 + description: TIM7 reset + name: TIM7RST + - bit_offset: 6 + bit_size: 1 + description: TIM12 reset + name: TIM12RST + - bit_offset: 7 + bit_size: 1 + description: TIM13 reset + name: TIM13RST + - bit_offset: 8 + bit_size: 1 + description: TIM14 reset + name: TIM14RST + - bit_offset: 18 + bit_size: 1 + description: USART 3 reset + name: UART3RST + - bit_offset: 19 + bit_size: 1 + description: USART 4 reset + name: UART4RST + - bit_offset: 20 + bit_size: 1 + description: USART 5 reset + name: UART5RST + - bit_offset: 25 + bit_size: 1 + description: CAN1 reset + name: CAN1RST + - bit_offset: 26 + bit_size: 1 + description: CAN2 reset + name: CAN2RST + - bit_offset: 29 + bit_size: 1 + description: DAC reset + name: DACRST + - bit_offset: 9 + bit_size: 1 + description: LPTIM1 reset + name: LPTIM1RST + - bit_offset: 24 + bit_size: 1 + description: FMPI2C1 reset + name: FMPI2C1RST + - bit_offset: 18 + bit_size: 1 + description: USART3RST + name: USART3RST + - bit_offset: 9 + bit_size: 1 + description: LPTimer1 reset + name: LPTIMER1RST + - bit_offset: 19 + bit_size: 1 + description: USART4 reset + name: USART4RST + - bit_offset: 20 + bit_size: 1 + description: USART5 reset + name: USART5RST + - bit_offset: 27 + bit_size: 1 + description: CAN 3 reset + name: CAN3RST + - bit_offset: 30 + bit_size: 1 + description: UART 7 reset + name: UART7RST + - bit_offset: 31 + bit_size: 1 + description: UART 8 reset + name: UART8RST + - bit_offset: 16 + bit_size: 1 + description: SPDIF-IN reset + name: SPDIFRST +fieldset/APB2ENR: + description: APB2 peripheral clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM1 clock enable + name: TIM1EN + - bit_offset: 4 + bit_size: 1 + description: USART1 clock enable + name: USART1EN + - bit_offset: 5 + bit_size: 1 + description: USART6 clock enable + name: USART6EN + - bit_offset: 8 + bit_size: 1 + description: ADC1 clock enable + name: ADC1EN + - bit_offset: 11 + bit_size: 1 + description: SDIO clock enable + name: SDIOEN + - bit_offset: 12 + bit_size: 1 + description: SPI1 clock enable + name: SPI1EN + - bit_offset: 13 + bit_size: 1 + description: SPI4 clock enable + name: SPI4EN + - bit_offset: 14 + bit_size: 1 + description: System configuration controller clock enable + name: SYSCFGEN + - bit_offset: 16 + bit_size: 1 + description: TIM9 clock enable + name: TIM9EN + - bit_offset: 17 + bit_size: 1 + description: TIM10 clock enable + name: TIM10EN + - bit_offset: 18 + bit_size: 1 + description: TIM11 clock enable + name: TIM11EN + - bit_offset: 1 + bit_size: 1 + description: TIM8 clock enable + name: TIM8EN + - bit_offset: 9 + bit_size: 1 + description: ADC2 clock enable + name: ADC2EN + - bit_offset: 10 + bit_size: 1 + description: ADC3 clock enable + name: ADC3EN + - bit_offset: 15 + bit_size: 1 + description: EXTI ans external IT clock enable + name: EXTITEN + - bit_offset: 20 + bit_size: 1 + description: SPI5 clock enable + name: SPI5EN + - bit_offset: 24 + bit_size: 1 + description: DFSDMEN + name: DFSDMEN + - bit_offset: 6 + bit_size: 1 + description: UART9 clock enable + name: UART9EN + - bit_offset: 7 + bit_size: 1 + description: UART10 clock enable + name: UART10EN + - bit_offset: 22 + bit_size: 1 + description: SAI 1 clock enable + name: SAI1EN + - bit_offset: 25 + bit_size: 1 + description: DFSDM2 clock enable + name: DFSDM2EN + - bit_offset: 21 + bit_size: 1 + description: SPI6 clock enable + name: SPI6EN + - bit_offset: 26 + bit_size: 1 + description: LTDC clock enable + name: LTDCEN + - bit_offset: 23 + bit_size: 1 + description: SAI2 clock enable + name: SAI2EN + - bit_offset: 27 + bit_size: 1 + description: DSI clocks enable + name: DSIEN +fieldset/APB2LPENR: + description: APB2 peripheral clock enabled in low power mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM1 clock enable during Sleep mode + name: TIM1LPEN + - bit_offset: 4 + bit_size: 1 + description: USART1 clock enable during Sleep mode + name: USART1LPEN + - bit_offset: 5 + bit_size: 1 + description: USART6 clock enable during Sleep mode + name: USART6LPEN + - bit_offset: 8 + bit_size: 1 + description: ADC1 clock enable during Sleep mode + name: ADC1LPEN + - bit_offset: 11 + bit_size: 1 + description: SDIO clock enable during Sleep mode + name: SDIOLPEN + - bit_offset: 12 + bit_size: 1 + description: SPI 1 clock enable during Sleep mode + name: SPI1LPEN + - bit_offset: 13 + bit_size: 1 + description: SPI4 clock enable during Sleep mode + name: SPI4LPEN + - bit_offset: 14 + bit_size: 1 + description: System configuration controller clock enable during Sleep mode + name: SYSCFGLPEN + - bit_offset: 16 + bit_size: 1 + description: TIM9 clock enable during sleep mode + name: TIM9LPEN + - bit_offset: 17 + bit_size: 1 + description: TIM10 clock enable during Sleep mode + name: TIM10LPEN + - bit_offset: 18 + bit_size: 1 + description: TIM11 clock enable during Sleep mode + name: TIM11LPEN + - bit_offset: 1 + bit_size: 1 + description: TIM8 clock enable during Sleep mode + name: TIM8LPEN + - bit_offset: 9 + bit_size: 1 + description: ADC2 clock enable during Sleep mode + name: ADC2LPEN + - bit_offset: 10 + bit_size: 1 + description: ADC 3 clock enable during Sleep mode + name: ADC3LPEN + - bit_offset: 15 + bit_size: 1 + description: EXTI and External IT clock enable during sleep mode + name: EXTITLPEN + - bit_offset: 20 + bit_size: 1 + description: SPI5 clock enable during Sleep mode + name: SPI5LPEN + - bit_offset: 24 + bit_size: 1 + description: DFSDMLPEN + name: DFSDMLPEN + - bit_offset: 6 + bit_size: 1 + description: UART9 clock enable during Sleep mode + name: UART9LPEN + - bit_offset: 6 + bit_size: 1 + description: USART9 clock enable during Sleep mode + name: USART9LPEN + - bit_offset: 7 + bit_size: 1 + description: UART10 clock enable during Sleep mode + name: UART10LPEN + - bit_offset: 7 + bit_size: 1 + description: USART10 clock enable during Sleep mode + name: USART10LPEN + - bit_offset: 22 + bit_size: 1 + description: SAI1 clock enable during Sleep mode + name: SAI1LPEN + - bit_offset: 25 + bit_size: 1 + description: DFSDM2 clock enable during Sleep mode + name: DFSDM2LPEN + - bit_offset: 21 + bit_size: 1 + description: SPI 6 clock enable during Sleep mode + name: SPI6LPEN + - bit_offset: 26 + bit_size: 1 + description: LTDC clock enable during Sleep mode + name: LTDCLPEN + - bit_offset: 23 + bit_size: 1 + description: SAI2 clock enable + name: SAI2LPEN + - bit_offset: 27 + bit_size: 1 + description: DSI clocks enable during Sleep mode + name: DSILPEN +fieldset/APB2RSTR: + description: APB2 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM1 reset + name: TIM1RST + - bit_offset: 4 + bit_size: 1 + description: USART1 reset + name: USART1RST + - bit_offset: 5 + bit_size: 1 + description: USART6 reset + name: USART6RST + - bit_offset: 8 + bit_size: 1 + description: ADC interface reset (common to all ADCs) + name: ADCRST + - bit_offset: 11 + bit_size: 1 + description: SDIO reset + name: SDIORST + - bit_offset: 12 + bit_size: 1 + description: SPI 1 reset + name: SPI1RST + - bit_offset: 13 + bit_size: 1 + description: SPI4 reset + name: SPI4RST + - bit_offset: 14 + bit_size: 1 + description: System configuration controller reset + name: SYSCFGRST + - bit_offset: 16 + bit_size: 1 + description: TIM9 reset + name: TIM9RST + - bit_offset: 17 + bit_size: 1 + description: TIM10 reset + name: TIM10RST + - bit_offset: 18 + bit_size: 1 + description: TIM11 reset + name: TIM11RST + - bit_offset: 1 + bit_size: 1 + description: TIM8 reset + name: TIM8RST + - bit_offset: 20 + bit_size: 1 + description: SPI5 reset + name: SPI5RST + - bit_offset: 24 + bit_size: 1 + description: DFSDMRST + name: DFSDMRST + - bit_offset: 6 + bit_size: 1 + description: UART9 reset + name: UART9RST + - bit_offset: 6 + bit_size: 1 + description: USART9 reset + name: USART9RST + - bit_offset: 7 + bit_size: 1 + description: USART10 reset + name: SART10RST + - bit_offset: 7 + bit_size: 1 + description: UART10 reset + name: UART10RST + - bit_offset: 22 + bit_size: 1 + description: SAI1 reset + name: SAI1RST + - bit_offset: 25 + bit_size: 1 + description: DFSDM2 reset + name: DFSDM2RST + - bit_offset: 21 + bit_size: 1 + description: SPI6 reset + name: SPI6RST + - bit_offset: 26 + bit_size: 1 + description: LTDC reset + name: LTDCRST + - bit_offset: 23 + bit_size: 1 + description: SAI2 reset + name: SAI2RST + - bit_offset: 27 + bit_size: 1 + description: DSI host reset + name: DSIRST +fieldset/BDCR: + description: Backup domain control register + fields: + - bit_offset: 0 + bit_size: 1 + description: External low-speed oscillator enable + enum: LSEON + name: LSEON + - bit_offset: 1 + bit_size: 1 + description: External low-speed oscillator ready + enum_read: LSERDYR + name: LSERDY + - bit_offset: 2 + bit_size: 1 + description: External low-speed oscillator bypass + enum: LSEBYP + name: LSEBYP + - bit_offset: 8 + bit_size: 2 + description: RTC clock source selection + enum: RTCSEL + name: RTCSEL + - bit_offset: 15 + bit_size: 1 + description: RTC clock enable + name: RTCEN + - bit_offset: 16 + bit_size: 1 + description: Backup domain software reset + name: BDRST + - bit_offset: 3 + bit_size: 1 + description: External low-speed oscillator bypass + enum: LSEMOD + name: LSEMOD +fieldset/CFGR: + description: clock configuration register + fields: + - bit_offset: 0 + bit_size: 2 + description: System clock switch + enum: SW + name: SW + - bit_offset: 2 + bit_size: 2 + description: System clock switch status + enum_read: SWSR + name: SWS + - bit_offset: 4 + bit_size: 4 + description: AHB prescaler + enum: HPRE + name: HPRE + - array: + len: 2 + stride: 3 + bit_offset: 10 + bit_size: 3 + description: APB Low speed prescaler (APB1) + enum: PPRE + name: PPRE + - bit_offset: 16 + bit_size: 5 + description: HSE division factor for RTC clock + name: RTCPRE + - array: + len: 2 + stride: 9 + bit_offset: 21 + bit_size: 2 + description: Microcontroller clock output 1 + enum: MCO1 + name: MCO + - bit_offset: 23 + bit_size: 1 + description: I2S clock selection + enum: ISSRC + name: I2SSRC + - bit_offset: 24 + bit_size: 3 + description: MCO1 prescaler + enum: MCOPRE + name: MCO1PRE + - bit_offset: 27 + bit_size: 3 + description: MCO2 prescaler + enum: MCOPRE + name: MCO2PRE + - bit_offset: 8 + bit_size: 1 + description: MCO output enable + name: MCO1EN + - bit_offset: 9 + bit_size: 1 + description: MCO output enable + name: MCO2EN +fieldset/CIR: + description: clock interrupt register + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI ready interrupt flag + enum_read: PLLISRDYFR + name: LSIRDYF + - bit_offset: 1 + bit_size: 1 + description: LSE ready interrupt flag + enum_read: PLLISRDYFR + name: LSERDYF + - bit_offset: 2 + bit_size: 1 + description: HSI ready interrupt flag + enum_read: PLLISRDYFR + name: HSIRDYF + - bit_offset: 3 + bit_size: 1 + description: HSE ready interrupt flag + enum_read: PLLISRDYFR + name: HSERDYF + - bit_offset: 4 + bit_size: 1 + description: Main PLL (PLL) ready interrupt flag + enum_read: PLLISRDYFR + name: PLLRDYF + - bit_offset: 5 + bit_size: 1 + description: PLLI2S ready interrupt flag + enum_read: PLLISRDYFR + name: PLLI2SRDYF + - bit_offset: 7 + bit_size: 1 + description: Clock security system interrupt flag + enum_read: CSSFR + name: CSSF + - bit_offset: 8 + bit_size: 1 + description: LSI ready interrupt enable + enum: PLLISRDYIE + name: LSIRDYIE + - bit_offset: 9 + bit_size: 1 + description: LSE ready interrupt enable + enum: PLLISRDYIE + name: LSERDYIE + - bit_offset: 10 + bit_size: 1 + description: HSI ready interrupt enable + enum: PLLISRDYIE + name: HSIRDYIE + - bit_offset: 11 + bit_size: 1 + description: HSE ready interrupt enable + enum: PLLISRDYIE + name: HSERDYIE + - bit_offset: 12 + bit_size: 1 + description: Main PLL (PLL) ready interrupt enable + enum: PLLISRDYIE + name: PLLRDYIE + - bit_offset: 13 + bit_size: 1 + description: PLLI2S ready interrupt enable + enum: PLLISRDYIE + name: PLLI2SRDYIE + - bit_offset: 16 + bit_size: 1 + description: LSI ready interrupt clear + enum_write: PLLISRDYCW + name: LSIRDYC + - bit_offset: 17 + bit_size: 1 + description: LSE ready interrupt clear + enum_write: PLLISRDYCW + name: LSERDYC + - bit_offset: 18 + bit_size: 1 + description: HSI ready interrupt clear + enum_write: PLLISRDYCW + name: HSIRDYC + - bit_offset: 19 + bit_size: 1 + description: HSE ready interrupt clear + enum_write: PLLISRDYCW + name: HSERDYC + - bit_offset: 20 + bit_size: 1 + description: Main PLL(PLL) ready interrupt clear + enum_write: PLLISRDYCW + name: PLLRDYC + - bit_offset: 21 + bit_size: 1 + description: PLLI2S ready interrupt clear + enum_write: PLLISRDYCW + name: PLLI2SRDYC + - bit_offset: 23 + bit_size: 1 + description: Clock security system interrupt clear + enum_write: CSSCW + name: CSSC + - bit_offset: 6 + bit_size: 1 + description: PLLSAI ready interrupt flag + enum_read: PLLSAIRDYFR + name: PLLSAIRDYF + - bit_offset: 14 + bit_size: 1 + description: PLLSAI Ready Interrupt Enable + enum: PLLSAIRDYIE + name: PLLSAIRDYIE + - bit_offset: 22 + bit_size: 1 + description: PLLSAI Ready Interrupt Clear + enum_write: PLLSAIRDYCW + name: PLLSAIRDYC +fieldset/CKGATENR: + description: clocks gated enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: AHB to APB1 Bridge clock enable + name: AHB2APB1_CKEN + - bit_offset: 1 + bit_size: 1 + description: AHB to APB2 Bridge clock enable + name: AHB2APB2_CKEN + - bit_offset: 2 + bit_size: 1 + description: Cortex M4 ETM clock enable + name: CM4DBG_CKEN + - bit_offset: 3 + bit_size: 1 + description: Spare clock enable + name: SPARE_CKEN + - bit_offset: 4 + bit_size: 1 + description: SRAM controller clock enable + name: SRAM_CKEN + - bit_offset: 5 + bit_size: 1 + description: Flash interface clock enable + name: FLITF_CKEN + - bit_offset: 6 + bit_size: 1 + description: RCC clock enable + name: RCC_CKEN + - bit_offset: 7 + bit_size: 1 + description: EVTCL clock enable + name: EVTCL_CKEN +fieldset/CR: + description: clock control register + fields: + - bit_offset: 0 + bit_size: 1 + description: Internal high-speed clock enable + enum: PLLISON + name: HSION + - bit_offset: 1 + bit_size: 1 + description: Internal high-speed clock ready flag + enum_read: PLLISRDYR + name: HSIRDY + - bit_offset: 3 + bit_size: 5 + description: Internal high-speed clock trimming + name: HSITRIM + - bit_offset: 8 + bit_size: 8 + description: Internal high-speed clock calibration + name: HSICAL + - bit_offset: 16 + bit_size: 1 + description: HSE clock enable + enum: PLLISON + name: HSEON + - bit_offset: 17 + bit_size: 1 + description: HSE clock ready flag + enum_read: PLLISRDYR + name: HSERDY + - bit_offset: 18 + bit_size: 1 + description: HSE clock bypass + enum: HSEBYP + name: HSEBYP + - bit_offset: 19 + bit_size: 1 + description: Clock security system enable + enum: CSSON + name: CSSON + - bit_offset: 24 + bit_size: 1 + description: Main PLL (PLL) enable + enum: PLLISON + name: PLLON + - bit_offset: 25 + bit_size: 1 + description: Main PLL (PLL) clock ready flag + enum_read: PLLISRDYR + name: PLLRDY + - bit_offset: 26 + bit_size: 1 + description: PLLI2S enable + enum: PLLISON + name: PLLI2SON + - bit_offset: 27 + bit_size: 1 + description: PLLI2S clock ready flag + enum_read: PLLISRDYR + name: PLLI2SRDY + - bit_offset: 28 + bit_size: 1 + description: PLLSAI enable + enum: PLLISON + name: PLLSAION + - bit_offset: 29 + bit_size: 1 + description: PLLSAI clock ready flag + enum_read: PLLISRDYR + name: PLLSAIRDY +fieldset/CSR: + description: clock control & status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Internal low-speed oscillator enable + enum: LSION + name: LSION + - bit_offset: 1 + bit_size: 1 + description: Internal low-speed oscillator ready + enum_read: LSIRDYR + name: LSIRDY + - bit_offset: 24 + bit_size: 1 + description: Remove reset flag + enum_write: RMVFW + name: RMVF + - bit_offset: 25 + bit_size: 1 + description: BOR reset flag + enum_read: LPWRRSTFR + name: BORRSTF + - bit_offset: 26 + bit_size: 1 + description: PIN reset flag + enum_read: LPWRRSTFR + name: PADRSTF + - bit_offset: 27 + bit_size: 1 + description: POR/PDR reset flag + enum_read: LPWRRSTFR + name: PORRSTF + - bit_offset: 28 + bit_size: 1 + description: Software reset flag + enum_read: LPWRRSTFR + name: SFTRSTF + - bit_offset: 29 + bit_size: 1 + description: Independent watchdog reset flag + enum_read: LPWRRSTFR + name: WDGRSTF + - bit_offset: 30 + bit_size: 1 + description: Window watchdog reset flag + enum_read: LPWRRSTFR + name: WWDGRSTF + - bit_offset: 31 + bit_size: 1 + description: Low-power reset flag + enum_read: LPWRRSTFR + name: LPWRRSTF +fieldset/DCKCFGR: + description: Dedicated Clock Configuration Register + fields: + - bit_offset: 24 + bit_size: 1 + description: Timers clocks prescalers selection + enum: TIMPRE + name: TIMPRE + - bit_offset: 25 + bit_size: 2 + description: I2SSRC + enum: ISSRC + name: I2SSRC + - bit_offset: 15 + bit_size: 5 + description: DFSDM1 audio clock selection + enum: CKDFSDMASEL + name: CKDFSDM1ASEL + - bit_offset: 25 + bit_size: 2 + description: I2S APB1 clocks source selection (I2S2/3) + enum: I2S1SRC + name: I2S1SRC + - bit_offset: 27 + bit_size: 2 + description: I2S APB2 clocks source selection (I2S1/4/5) + enum: I2S1SRC + name: I2S2SRC + - bit_offset: 31 + bit_size: 1 + description: DFSDM1 Kernel clock selection + enum: CKDFSDMSEL + name: CKDFSDM1SEL + - bit_offset: 0 + bit_size: 5 + description: PLLI2S division factor for SAI1 A/B clock + enum: PLLISDIVR + name: PLLI2SDIVR + - bit_offset: 8 + bit_size: 5 + description: PLL division factor for SAI1 A/B clock + enum: PLLDIVR + name: PLLDIVR + - bit_offset: 14 + bit_size: 1 + description: DFSDM2 audio clock selection + enum: CKDFSDMASEL + name: CKDFSDM2ASEL + - bit_offset: 20 + bit_size: 2 + description: SAI1-A clock source selection + enum: SAIASRC + name: SAI1ASRC + - bit_offset: 22 + bit_size: 2 + description: SAI1-B clock source selection + enum: SAIBSRC + name: SAI1BSRC + - bit_offset: 0 + bit_size: 5 + description: PLLI2S division factor for SAI1 clock + enum: PLLISDIVQ + name: PLLI2SDIVQ + - bit_offset: 8 + bit_size: 5 + description: PLLSAI division factor for SAI1 clock + enum: PLLSAIDIVQ + name: PLLSAIDIVQ + - bit_offset: 16 + bit_size: 2 + description: division factor for LCD_CLK + enum: PLLSAIDIVR + name: PLLSAIDIVR + - bit_offset: 20 + bit_size: 2 + description: SAI1 clock source selection + enum: SAI1SRC + name: SAI1SRC + - bit_offset: 22 + bit_size: 2 + description: SAI2 clock source selection + enum: SAI2SRC + name: SAI2SRC + - bit_offset: 27 + bit_size: 1 + description: 48 MHz clock source selection + enum: CKMSEL + name: CK48MSEL + - bit_offset: 28 + bit_size: 1 + description: SDIO clock source selection + enum: SDIOSEL + name: SDIOSEL + - bit_offset: 29 + bit_size: 1 + description: DSI clock source selection + enum: DSISEL + name: DSISEL +fieldset/DCKCFGR2: + description: dedicated clocks configuration register 2 + fields: + - bit_offset: 22 + bit_size: 2 + description: FMPI2C1 kernel clock source selection + enum: FMPICSEL + name: FMPI2C1SEL + - bit_offset: 30 + bit_size: 2 + description: LPTIM1SEL + enum: LPTIMSEL + name: LPTIM1SEL + - bit_offset: 27 + bit_size: 1 + description: SDIO/USBFS clock selection + enum: CKMSEL + name: CK48MSEL + - bit_offset: 28 + bit_size: 1 + description: SDIO clock selection + enum: SDIOSEL + name: SDIOSEL + - bit_offset: 26 + bit_size: 1 + description: HDMI CEC clock source selection + enum: CECSEL + name: CECSEL + - bit_offset: 29 + bit_size: 1 + description: SPDIF clock selection + enum: SPDIFRXSEL + name: SPDIFRXSEL +fieldset/PLLCFGR: + description: PLL configuration register + fields: + - bit_offset: 0 + bit_size: 6 + description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input + clock + name: PLLM + - bit_offset: 6 + bit_size: 9 + description: Main PLL (PLL) multiplication factor for VCO + name: PLLN + - bit_offset: 16 + bit_size: 2 + description: Main PLL (PLL) division factor for main system clock + enum: PLLP + name: PLLP + - bit_offset: 22 + bit_size: 1 + description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + enum: PLLSRC + name: PLLSRC + - bit_offset: 24 + bit_size: 4 + description: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number + generator clocks + name: PLLQ + - bit_offset: 28 + bit_size: 3 + description: PLL division factor for I2S and System clocks + name: PLLR +fieldset/PLLI2SCFGR: + description: PLLI2S configuration register + fields: + - bit_offset: 6 + bit_size: 9 + description: PLLI2S multiplication factor for VCO + name: PLLI2SN + - bit_offset: 28 + bit_size: 3 + description: PLLI2S division factor for I2S clocks + name: PLLI2SR + - bit_offset: 0 + bit_size: 6 + description: Division factor for the audio PLL (PLLI2S) input clock + name: PLLI2SM + - bit_offset: 22 + bit_size: 1 + description: PLLI2S entry clock source + enum: PLLISSRC + name: PLLI2SSRC + - bit_offset: 24 + bit_size: 4 + description: PLLI2S division factor for USB OTG FS/SDIO/RNG clock + name: PLLI2SQ + - bit_offset: 16 + bit_size: 2 + description: PLLI2S division factor for SPDIF-IN clock + enum: PLLISP + name: PLLI2SP +fieldset/PLLSAICFGR: + description: PLL configuration register + fields: + - bit_offset: 6 + bit_size: 9 + description: PLLSAI division factor for VCO + name: PLLSAIN + - bit_offset: 24 + bit_size: 4 + description: PLLSAI division factor for SAI1 clock + name: PLLSAIQ + - bit_offset: 28 + bit_size: 3 + description: PLLSAI division factor for LCD clock + name: PLLSAIR + - bit_offset: 0 + bit_size: 6 + description: Division factor for audio PLLSAI input clock + name: PLLSAIM + - bit_offset: 16 + bit_size: 2 + description: PLLSAI division factor for 48 MHz clock + enum: PLLSAIP + name: PLLSAIP +fieldset/SSCGR: + description: spread spectrum clock generation register + fields: + - bit_offset: 0 + bit_size: 13 + description: Modulation period + name: MODPER + - bit_offset: 13 + bit_size: 15 + description: Incrementation step + name: INCSTEP + - bit_offset: 30 + bit_size: 1 + description: Spread Select + enum: SPREADSEL + name: SPREADSEL + - bit_offset: 31 + bit_size: 1 + description: Spread spectrum modulation enable + name: SSCGEN diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index e66ac16..372af9c 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -5,11 +5,23 @@ block/RCC: description: clock control register fieldset: CR name: CR + - byte_offset: 4 + description: RCC HSI configuration register + fieldset: HSICFGR + name: HSICFGR + - byte_offset: 4 + description: RCC Internal Clock Source Calibration Register + fieldset: ICSCR + name: ICSCR - access: Read byte_offset: 8 description: RCC Clock Recovery RC Register fieldset: CRRCR name: CRRCR + - byte_offset: 12 + description: RCC CSI configuration register + fieldset: CSICFGR + name: CSICFGR - byte_offset: 16 description: RCC Clock Configuration Register fieldset: CFGR @@ -58,6 +70,22 @@ block/RCC: description: RCC PLL3 Fractional Divider Register fieldset: PLL3FRACR name: PLL3FRACR + - byte_offset: 76 + description: RCC Domain 1 Kernel Clock Configuration Register + fieldset: D1CCIPR + name: D1CCIPR + - byte_offset: 80 + description: RCC Domain 2 Kernel Clock Configuration Register + fieldset: D2CCIP1R + name: D2CCIP1R + - byte_offset: 84 + description: RCC Domain 2 Kernel Clock Configuration Register + fieldset: D2CCIP2R + name: D2CCIP2R + - byte_offset: 88 + description: RCC Domain 3 Kernel Clock Configuration Register + fieldset: D3CCIPR + name: D3CCIPR - byte_offset: 96 description: RCC Clock Source Interrupt Enable Register fieldset: CIER @@ -116,117 +144,1240 @@ block/RCC: fieldset: APB4RSTR name: APB4RSTR - byte_offset: 160 - description: Global Control Register + description: RCC Global Control Register fieldset: GCR name: GCR - byte_offset: 168 description: RCC D3 Autonomous mode Register fieldset: D3AMR name: D3AMR + - byte_offset: 208 + description: RCC Reset Status Register + fieldset: RSR + name: RSR + - byte_offset: 212 + description: RCC AHB3 Clock Register + fieldset: AHB3ENR + name: AHB3ENR + - byte_offset: 216 + description: RCC AHB1 Clock Register + fieldset: AHB1ENR + name: AHB1ENR + - byte_offset: 220 + description: RCC AHB2 Clock Register + fieldset: AHB2ENR + name: AHB2ENR + - byte_offset: 224 + description: RCC AHB4 Clock Register + fieldset: AHB4ENR + name: AHB4ENR + - byte_offset: 228 + description: RCC APB3 Clock Register + fieldset: APB3ENR + name: APB3ENR + - byte_offset: 232 + description: RCC APB1 Clock Register + fieldset: APB1LENR + name: APB1LENR + - byte_offset: 236 + description: RCC APB1 Clock Register + fieldset: APB1HENR + name: APB1HENR + - byte_offset: 240 + description: RCC APB2 Clock Register + fieldset: APB2ENR + name: APB2ENR + - byte_offset: 244 + description: RCC APB4 Clock Register + fieldset: APB4ENR + name: APB4ENR + - byte_offset: 252 + description: RCC AHB3 Sleep Clock Register + fieldset: AHB3LPENR + name: AHB3LPENR + - byte_offset: 256 + description: RCC AHB1 Sleep Clock Register + fieldset: AHB1LPENR + name: AHB1LPENR + - byte_offset: 260 + description: RCC AHB2 Sleep Clock Register + fieldset: AHB2LPENR + name: AHB2LPENR + - byte_offset: 264 + description: RCC AHB4 Sleep Clock Register + fieldset: AHB4LPENR + name: AHB4LPENR + - byte_offset: 268 + description: RCC APB3 Sleep Clock Register + fieldset: APB3LPENR + name: APB3LPENR + - byte_offset: 272 + description: RCC APB1 Low Sleep Clock Register + fieldset: APB1LLPENR + name: APB1LLPENR + - byte_offset: 276 + description: RCC APB1 High Sleep Clock Register + fieldset: APB1HLPENR + name: APB1HLPENR + - byte_offset: 280 + description: RCC APB2 Sleep Clock Register + fieldset: APB2LPENR + name: APB2LPENR + - byte_offset: 284 + description: RCC APB4 Sleep Clock Register + fieldset: APB4LPENR + name: APB4LPENR - byte_offset: 304 description: RCC Reset Status Register fieldset: C1_RSR name: C1_RSR + - byte_offset: 308 + description: RCC AHB3 Clock Register + fieldset: C1_AHB3ENR + name: C1_AHB3ENR + - byte_offset: 312 + description: RCC AHB1 Clock Register + fieldset: C1_AHB1ENR + name: C1_AHB1ENR + - byte_offset: 316 + description: RCC AHB2 Clock Register + fieldset: C1_AHB2ENR + name: C1_AHB2ENR + - byte_offset: 320 + description: RCC AHB4 Clock Register + fieldset: C1_AHB4ENR + name: C1_AHB4ENR + - byte_offset: 324 + description: RCC APB3 Clock Register + fieldset: C1_APB3ENR + name: C1_APB3ENR + - byte_offset: 328 + description: RCC APB1 Clock Register + fieldset: C1_APB1LENR + name: C1_APB1LENR + - byte_offset: 332 + description: RCC APB1 Clock Register + fieldset: C1_APB1HENR + name: C1_APB1HENR + - byte_offset: 336 + description: RCC APB2 Clock Register + fieldset: C1_APB2ENR + name: C1_APB2ENR + - byte_offset: 340 + description: RCC APB4 Clock Register + fieldset: C1_APB4ENR + name: C1_APB4ENR + - byte_offset: 348 + description: RCC AHB3 Sleep Clock Register + fieldset: C1_AHB3LPENR + name: C1_AHB3LPENR + - byte_offset: 352 + description: RCC AHB1 Sleep Clock Register + fieldset: C1_AHB1LPENR + name: C1_AHB1LPENR + - byte_offset: 356 + description: RCC AHB2 Sleep Clock Register + fieldset: C1_AHB2LPENR + name: C1_AHB2LPENR + - byte_offset: 360 + description: RCC AHB4 Sleep Clock Register + fieldset: C1_AHB4LPENR + name: C1_AHB4LPENR + - byte_offset: 364 + description: RCC APB3 Sleep Clock Register + fieldset: C1_APB3LPENR + name: C1_APB3LPENR + - byte_offset: 368 + description: RCC APB1 Low Sleep Clock Register + fieldset: C1_APB1LLPENR + name: C1_APB1LLPENR + - byte_offset: 372 + description: RCC APB1 High Sleep Clock Register + fieldset: C1_APB1HLPENR + name: C1_APB1HLPENR + - byte_offset: 376 + description: RCC APB2 Sleep Clock Register + fieldset: C1_APB2LPENR + name: C1_APB2LPENR + - byte_offset: 380 + description: RCC APB4 Sleep Clock Register + fieldset: C1_APB4LPENR + name: C1_APB4LPENR + - byte_offset: 76 + description: RCC Domain 1 Kernel Clock Configuration Register + fieldset: CDCCIPR + name: CDCCIPR + - byte_offset: 80 + description: RCC Domain 2 Kernel Clock Configuration Register + fieldset: CDCCIP1R + name: CDCCIP1R + - byte_offset: 84 + description: RCC Domain 2 Kernel Clock Configuration Register + fieldset: CDCCIP2R + name: CDCCIP2R + - byte_offset: 88 + description: RCC Domain 3 Kernel Clock Configuration Register + fieldset: SRDCCIPR + name: SRDCCIPR + - byte_offset: 308 + description: RCC AHB3 Clock Register + fieldset: AHB3ENR + name: AHB3ENR + - byte_offset: 312 + description: RCC AHB1 Clock Register + fieldset: AHB1ENR + name: AHB1ENR + - byte_offset: 316 + description: RCC AHB2 Clock Register + fieldset: AHB2ENR + name: AHB2ENR + - byte_offset: 320 + description: RCC AHB4 Clock Register + fieldset: AHB4ENR + name: AHB4ENR + - byte_offset: 324 + description: RCC APB3 Clock Register + fieldset: APB3ENR + name: APB3ENR + - byte_offset: 328 + description: RCC APB1 Clock Register + fieldset: APB1LENR + name: APB1LENR + - byte_offset: 332 + description: RCC APB1 Clock Register + fieldset: APB1HENR + name: APB1HENR + - byte_offset: 336 + description: RCC APB2 Clock Register + fieldset: APB2ENR + name: APB2ENR + - byte_offset: 340 + description: RCC APB4 Clock Register + fieldset: APB4ENR + name: APB4ENR + - byte_offset: 348 + description: RCC AHB3 Sleep Clock Register + fieldset: AHB3LPENR + name: AHB3LPENR + - byte_offset: 352 + description: RCC AHB1 Sleep Clock Register + fieldset: AHB1LPENR + name: AHB1LPENR + - byte_offset: 356 + description: RCC AHB2 Sleep Clock Register + fieldset: AHB2LPENR + name: AHB2LPENR + - byte_offset: 360 + description: RCC AHB4 Sleep Clock Register + fieldset: AHB4LPENR + name: AHB4LPENR + - byte_offset: 364 + description: RCC APB3 Sleep Clock Register + fieldset: APB3LPENR + name: APB3LPENR + - byte_offset: 368 + description: RCC APB1 Low Sleep Clock Register + fieldset: APB1LLPENR + name: APB1LLPENR + - byte_offset: 372 + description: RCC APB1 High Sleep Clock Register + fieldset: APB1HLPENR + name: APB1HLPENR + - byte_offset: 376 + description: RCC APB2 Sleep Clock Register + fieldset: APB2LPENR + name: APB2LPENR + - byte_offset: 380 + description: RCC APB4 Sleep Clock Register + fieldset: APB4LPENR + name: APB4LPENR enum/ADCSEL: bit_size: 2 + variants: + - description: pll2_p selected as peripheral clock + name: PLL2_P + value: 0 + - description: pll3_r selected as peripheral clock + name: PLL3_R + value: 1 + - description: PER selected as peripheral clock + name: PER + value: 2 enum/CECSEL: bit_size: 2 + variants: + - description: LSE selected as peripheral clock + name: LSE + value: 0 + - description: LSI selected as peripheral clock + name: LSI + value: 1 + - description: csi_ker selected as peripheral clock + name: CSI_KER + value: 2 enum/CKPERSEL: bit_size: 2 + variants: + - description: HSI selected as peripheral clock + name: HSI + value: 0 + - description: CSI selected as peripheral clock + name: CSI + value: 1 + - description: HSE selected as peripheral clock + name: HSE + value: 2 +enum/CPURSTFR: + bit_size: 1 + variants: + - description: No reset occoured for block + name: NoResetOccoured + value: 0 + - description: Reset occoured for block + name: ResetOccourred + value: 1 +enum/C_RSR_CPURSTFR: + bit_size: 1 + variants: + - description: No reset occoured for block + name: NoResetOccoured + value: 0 + - description: Reset occoured for block + name: ResetOccourred + value: 1 +enum/C_RSR_RMVF: + bit_size: 1 + variants: + - description: Not clearing the the reset flags + name: NotActive + value: 0 + - description: Clear the reset flags + name: Clear + value: 1 enum/DFSDMSEL: bit_size: 1 + variants: + - description: rcc_pclk2 selected as peripheral clock + name: RCC_PCLK2 + value: 0 + - description: System clock selected as peripheral clock + name: SYS + value: 1 enum/DIVP: bit_size: 7 + variants: + - description: pll_p_ck = vco_ck + name: Div1 + value: 0 + - description: pll_p_ck = vco_ck / 2 + name: Div2 + value: 1 + - description: pll_p_ck = vco_ck / 4 + name: Div4 + value: 3 + - description: pll_p_ck = vco_ck / 6 + name: Div6 + value: 5 + - description: pll_p_ck = vco_ck / 8 + name: Div8 + value: 7 + - description: pll_p_ck = vco_ck / 10 + name: Div10 + value: 9 + - description: pll_p_ck = vco_ck / 12 + name: Div12 + value: 11 + - description: pll_p_ck = vco_ck / 14 + name: Div14 + value: 13 + - description: pll_p_ck = vco_ck / 16 + name: Div16 + value: 15 + - description: pll_p_ck = vco_ck / 18 + name: Div18 + value: 17 + - description: pll_p_ck = vco_ck / 20 + name: Div20 + value: 19 + - description: pll_p_ck = vco_ck / 22 + name: Div22 + value: 21 + - description: pll_p_ck = vco_ck / 24 + name: Div24 + value: 23 + - description: pll_p_ck = vco_ck / 26 + name: Div26 + value: 25 + - description: pll_p_ck = vco_ck / 28 + name: Div28 + value: 27 + - description: pll_p_ck = vco_ck / 30 + name: Div30 + value: 29 + - description: pll_p_ck = vco_ck / 32 + name: Div32 + value: 31 + - description: pll_p_ck = vco_ck / 34 + name: Div34 + value: 33 + - description: pll_p_ck = vco_ck / 36 + name: Div36 + value: 35 + - description: pll_p_ck = vco_ck / 38 + name: Div38 + value: 37 + - description: pll_p_ck = vco_ck / 40 + name: Div40 + value: 39 + - description: pll_p_ck = vco_ck / 42 + name: Div42 + value: 41 + - description: pll_p_ck = vco_ck / 44 + name: Div44 + value: 43 + - description: pll_p_ck = vco_ck / 46 + name: Div46 + value: 45 + - description: pll_p_ck = vco_ck / 48 + name: Div48 + value: 47 + - description: pll_p_ck = vco_ck / 50 + name: Div50 + value: 49 + - description: pll_p_ck = vco_ck / 52 + name: Div52 + value: 51 + - description: pll_p_ck = vco_ck / 54 + name: Div54 + value: 53 + - description: pll_p_ck = vco_ck / 56 + name: Div56 + value: 55 + - description: pll_p_ck = vco_ck / 58 + name: Div58 + value: 57 + - description: pll_p_ck = vco_ck / 60 + name: Div60 + value: 59 + - description: pll_p_ck = vco_ck / 62 + name: Div62 + value: 61 + - description: pll_p_ck = vco_ck / 64 + name: Div64 + value: 63 + - description: pll_p_ck = vco_ck / 66 + name: Div66 + value: 65 + - description: pll_p_ck = vco_ck / 68 + name: Div68 + value: 67 + - description: pll_p_ck = vco_ck / 70 + name: Div70 + value: 69 + - description: pll_p_ck = vco_ck / 72 + name: Div72 + value: 71 + - description: pll_p_ck = vco_ck / 74 + name: Div74 + value: 73 + - description: pll_p_ck = vco_ck / 76 + name: Div76 + value: 75 + - description: pll_p_ck = vco_ck / 78 + name: Div78 + value: 77 + - description: pll_p_ck = vco_ck / 80 + name: Div80 + value: 79 + - description: pll_p_ck = vco_ck / 82 + name: Div82 + value: 81 + - description: pll_p_ck = vco_ck / 84 + name: Div84 + value: 83 + - description: pll_p_ck = vco_ck / 86 + name: Div86 + value: 85 + - description: pll_p_ck = vco_ck / 88 + name: Div88 + value: 87 + - description: pll_p_ck = vco_ck / 90 + name: Div90 + value: 89 + - description: pll_p_ck = vco_ck / 92 + name: Div92 + value: 91 + - description: pll_p_ck = vco_ck / 94 + name: Div94 + value: 93 + - description: pll_p_ck = vco_ck / 96 + name: Div96 + value: 95 + - description: pll_p_ck = vco_ck / 98 + name: Div98 + value: 97 + - description: pll_p_ck = vco_ck / 100 + name: Div100 + value: 99 + - description: pll_p_ck = vco_ck / 102 + name: Div102 + value: 101 + - description: pll_p_ck = vco_ck / 104 + name: Div104 + value: 103 + - description: pll_p_ck = vco_ck / 106 + name: Div106 + value: 105 + - description: pll_p_ck = vco_ck / 108 + name: Div108 + value: 107 + - description: pll_p_ck = vco_ck / 110 + name: Div110 + value: 109 + - description: pll_p_ck = vco_ck / 112 + name: Div112 + value: 111 + - description: pll_p_ck = vco_ck / 114 + name: Div114 + value: 113 + - description: pll_p_ck = vco_ck / 116 + name: Div116 + value: 115 + - description: pll_p_ck = vco_ck / 118 + name: Div118 + value: 117 + - description: pll_p_ck = vco_ck / 120 + name: Div120 + value: 119 + - description: pll_p_ck = vco_ck / 122 + name: Div122 + value: 121 + - description: pll_p_ck = vco_ck / 124 + name: Div124 + value: 123 + - description: pll_p_ck = vco_ck / 126 + name: Div126 + value: 125 + - description: pll_p_ck = vco_ck / 128 + name: Div128 + value: 127 enum/DPPRE: bit_size: 3 + variants: + - description: rcc_hclk not divided + name: Div1 + value: 0 + - description: rcc_hclk divided by 2 + name: Div2 + value: 4 + - description: rcc_hclk divided by 4 + name: Div4 + value: 5 + - description: rcc_hclk divided by 8 + name: Div8 + value: 6 + - description: rcc_hclk divided by 16 + name: Div16 + value: 7 enum/FDCANSEL: bit_size: 2 + variants: + - description: HSE selected as peripheral clock + name: HSE + value: 0 + - description: pll1_q selected as peripheral clock + name: PLL1_Q + value: 1 + - description: pll2_q selected as peripheral clock + name: PLL2_Q + value: 2 enum/FMCSEL: bit_size: 2 + variants: + - description: rcc_hclk3 selected as peripheral clock + name: RCC_HCLK3 + value: 0 + - description: pll1_q selected as peripheral clock + name: PLL1_Q + value: 1 + - description: pll2_r selected as peripheral clock + name: PLL2_R + value: 2 + - description: PER selected as peripheral clock + name: PER + value: 3 enum/HPRE: bit_size: 4 + variants: + - description: sys_ck not divided + name: Div1 + value: 0 + - description: sys_ck divided by 2 + name: Div2 + value: 8 + - description: sys_ck divided by 4 + name: Div4 + value: 9 + - description: sys_ck divided by 8 + name: Div8 + value: 10 + - description: sys_ck divided by 16 + name: Div16 + value: 11 + - description: sys_ck divided by 64 + name: Div64 + value: 12 + - description: sys_ck divided by 128 + name: Div128 + value: 13 + - description: sys_ck divided by 256 + name: Div256 + value: 14 + - description: sys_ck divided by 512 + name: Div512 + value: 15 enum/HRTIMSEL: bit_size: 1 + variants: + - description: The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck) + name: TIMY_KER + value: 0 + - description: The HRTIM prescaler clock source is the CPU clock (c_ck) + name: C_CK + value: 1 enum/HSEBYP: bit_size: 1 + variants: + - description: HSE crystal oscillator not bypassed + name: NotBypassed + value: 0 + - description: HSE crystal oscillator bypassed with external clock + name: Bypassed + value: 1 enum/HSIDIV: bit_size: 2 + variants: + - description: No division + name: Div1 + value: 0 + - description: Division by 2 + name: Div2 + value: 1 + - description: Division by 4 + name: Div4 + value: 2 + - description: Division by 8 + name: Div8 + value: 3 enum/HSIDIVFR: bit_size: 1 + variants: + - description: New HSIDIV ratio has not yet propagated to hsi_ck + name: NotPropagated + value: 0 + - description: HSIDIV ratio has propagated to hsi_ck + name: Propagated + value: 1 enum/HSION: bit_size: 1 + variants: + - description: Clock Off + name: 'Off' + value: 0 + - description: Clock On + name: 'On' + value: 1 enum/HSIRDYR: bit_size: 1 + variants: + - description: Clock not ready + name: NotReady + value: 0 + - description: Clock ready + name: Ready + value: 1 enum/I2C123SEL: bit_size: 2 + variants: + - description: rcc_pclk1 selected as peripheral clock + name: RCC_PCLK1 + value: 0 + - description: pll3_r selected as peripheral clock + name: PLL3_R + value: 1 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 2 + - description: csi_ker selected as peripheral clock + name: CSI_KER + value: 3 enum/I2C4SEL: bit_size: 2 + variants: + - description: rcc_pclk4 selected as peripheral clock + name: RCC_PCLK4 + value: 0 + - description: pll3_r selected as peripheral clock + name: PLL3_R + value: 1 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 2 + - description: csi_ker selected as peripheral clock + name: CSI_KER + value: 3 enum/LPTIM1SEL: bit_size: 3 + variants: + - description: rcc_pclk1 selected as peripheral clock + name: RCC_PCLK1 + value: 0 + - description: pll2_p selected as peripheral clock + name: PLL2_P + value: 1 + - description: pll3_r selected as peripheral clock + name: PLL3_R + value: 2 + - description: LSE selected as peripheral clock + name: LSE + value: 3 + - description: LSI selected as peripheral clock + name: LSI + value: 4 + - description: PER selected as peripheral clock + name: PER + value: 5 enum/LPTIM2SEL: bit_size: 3 + variants: + - description: rcc_pclk4 selected as peripheral clock + name: RCC_PCLK4 + value: 0 + - description: pll2_p selected as peripheral clock + name: PLL2_P + value: 1 + - description: pll3_r selected as peripheral clock + name: PLL3_R + value: 2 + - description: LSE selected as peripheral clock + name: LSE + value: 3 + - description: LSI selected as peripheral clock + name: LSI + value: 4 + - description: PER selected as peripheral clock + name: PER + value: 5 enum/LPUARTSEL: bit_size: 3 + variants: + - description: rcc_pclk_d3 selected as peripheral clock + name: RCC_PCLK_D3 + value: 0 + - description: pll2_q selected as peripheral clock + name: PLL2_Q + value: 1 + - description: pll3_q selected as peripheral clock + name: PLL3_Q + value: 2 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 3 + - description: csi_ker selected as peripheral clock + name: CSI_KER + value: 4 + - description: LSE selected as peripheral clock + name: LSE + value: 5 enum/LSEBYP: bit_size: 1 + variants: + - description: LSE crystal oscillator not bypassed + name: NotBypassed + value: 0 + - description: LSE crystal oscillator bypassed with external clock + name: Bypassed + value: 1 enum/LSECSSDR: bit_size: 1 + variants: + - description: No failure detected on 32 kHz oscillator + name: NoFailure + value: 0 + - description: Failure detected on 32 kHz oscillator + name: Failure + value: 1 enum/LSECSSON: bit_size: 1 + variants: + - description: Clock security system on 32 kHz oscillator off + name: SecurityOff + value: 0 + - description: Clock security system on 32 kHz oscillator on + name: SecurityOn + value: 1 enum/LSEDRV: bit_size: 2 + variants: + - description: Lowest LSE oscillator driving capability + name: Lowest + value: 0 + - description: Medium low LSE oscillator driving capability + name: MediumLow + value: 1 + - description: Medium high LSE oscillator driving capability + name: MediumHigh + value: 2 + - description: Highest LSE oscillator driving capability + name: Highest + value: 3 enum/LSEON: bit_size: 1 + variants: + - description: LSE oscillator Off + name: 'Off' + value: 0 + - description: LSE oscillator On + name: 'On' + value: 1 enum/LSERDYR: bit_size: 1 + variants: + - description: LSE oscillator not ready + name: NotReady + value: 0 + - description: LSE oscillator ready + name: Ready + value: 1 enum/LSION: bit_size: 1 + variants: + - description: LSI oscillator Off + name: 'Off' + value: 0 + - description: LSI oscillator On + name: 'On' + value: 1 enum/LSIRDYC: bit_size: 1 + variants: + - description: Clear interrupt flag + name: Clear + value: 1 enum/LSIRDYIE: bit_size: 1 + variants: + - description: Interrupt disabled + name: Disabled + value: 0 + - description: Interrupt enabled + name: Enabled + value: 1 enum/LSIRDYR: bit_size: 1 + variants: + - description: LSI oscillator not ready + name: NotReady + value: 0 + - description: LSI oscillator ready + name: Ready + value: 1 enum/MCO1: bit_size: 3 + variants: + - description: HSI selected for micro-controller clock output + name: HSI + value: 0 + - description: LSE selected for micro-controller clock output + name: LSE + value: 1 + - description: HSE selected for micro-controller clock output + name: HSE + value: 2 + - description: pll1_q selected for micro-controller clock output + name: PLL1_Q + value: 3 + - description: HSI48 selected for micro-controller clock output + name: HSI48 + value: 4 enum/MCO2: bit_size: 3 + variants: + - description: System clock selected for micro-controller clock output + name: SYSCLK + value: 0 + - description: pll2_p selected for micro-controller clock output + name: PLL2_P + value: 1 + - description: HSE selected for micro-controller clock output + name: HSE + value: 2 + - description: pll1_p selected for micro-controller clock output + name: PLL1_P + value: 3 + - description: CSI selected for micro-controller clock output + name: CSI + value: 4 + - description: LSI selected for micro-controller clock output + name: LSI + value: 5 enum/PLLRGE: bit_size: 2 + variants: + - description: Frequency is between 1 and 2 MHz + name: Range1 + value: 0 + - description: Frequency is between 2 and 4 MHz + name: Range2 + value: 1 + - description: Frequency is between 4 and 8 MHz + name: Range4 + value: 2 + - description: Frequency is between 8 and 16 MHz + name: Range8 + value: 3 enum/PLLSRC: bit_size: 2 + variants: + - description: HSI selected as PLL clock + name: HSI + value: 0 + - description: CSI selected as PLL clock + name: CSI + value: 1 + - description: HSE selected as PLL clock + name: HSE + value: 2 + - description: No clock sent to DIVMx dividers and PLLs + name: None + value: 3 enum/PLLVCOSEL: bit_size: 1 + variants: + - description: VCO frequency range 192 to 836 MHz + name: WideVCO + value: 0 + - description: VCO frequency range 150 to 420 MHz + name: MediumVCO + value: 1 +enum/RMVF: + bit_size: 1 + variants: + - description: Not clearing the the reset flags + name: NotActive + value: 0 + - description: Clear the reset flags + name: Clear + value: 1 enum/RNGSEL: bit_size: 2 + variants: + - description: HSI48 selected as peripheral clock + name: HSI48 + value: 0 + - description: pll1_q selected as peripheral clock + name: PLL1_Q + value: 1 + - description: LSE selected as peripheral clock + name: LSE + value: 2 + - description: LSI selected as peripheral clock + name: LSI + value: 3 +enum/RSR_CPURSTFR: + bit_size: 1 + variants: + - description: No reset occoured for block + name: NoResetOccoured + value: 0 + - description: Reset occoured for block + name: ResetOccourred + value: 1 +enum/RSR_RMVF: + bit_size: 1 + variants: + - description: Not clearing the the reset flags + name: NotActive + value: 0 + - description: Clear the reset flags + name: Clear + value: 1 enum/RTCSEL: bit_size: 2 + variants: + - description: No clock + name: NoClock + value: 0 + - description: LSE oscillator clock used as RTC clock + name: LSE + value: 1 + - description: LSI oscillator clock used as RTC clock + name: LSI + value: 2 + - description: HSE oscillator clock divided by a prescaler used as RTC clock + name: HSE + value: 3 enum/SAIASEL: bit_size: 3 + variants: + - description: pll1_q selected as peripheral clock + name: PLL1_Q + value: 0 + - description: pll2_p selected as peripheral clock + name: PLL2_P + value: 1 + - description: pll3_p selected as peripheral clock + name: PLL3_P + value: 2 + - description: i2s_ckin selected as peripheral clock + name: I2S_CKIN + value: 3 + - description: PER selected as peripheral clock + name: PER + value: 4 enum/SAISEL: bit_size: 3 + variants: + - description: pll1_q selected as peripheral clock + name: PLL1_Q + value: 0 + - description: pll2_p selected as peripheral clock + name: PLL2_P + value: 1 + - description: pll3_p selected as peripheral clock + name: PLL3_P + value: 2 + - description: I2S_CKIN selected as peripheral clock + name: I2S_CKIN + value: 3 + - description: PER selected as peripheral clock + name: PER + value: 4 enum/SDMMCSEL: bit_size: 1 + variants: + - description: pll1_q selected as peripheral clock + name: PLL1_Q + value: 0 + - description: pll2_r selected as peripheral clock + name: PLL2_R + value: 1 +enum/SPDIFRXSEL: + bit_size: 2 + variants: + - description: pll1_q selected as peripheral clock + name: PLL1_Q + value: 0 + - description: pll2_r selected as peripheral clock + name: PLL2_R + value: 1 + - description: pll3_r selected as peripheral clock + name: PLL3_R + value: 2 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 3 +enum/SPDIFSEL: + bit_size: 2 + variants: + - description: pll1_q selected as peripheral clock + name: PLL1_Q + value: 0 + - description: pll2_r selected as peripheral clock + name: PLL2_R + value: 1 + - description: pll3_r selected as peripheral clock + name: PLL3_R + value: 2 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 3 enum/SPI45SEL: bit_size: 3 + variants: + - description: APB clock selected as peripheral clock + name: APB + value: 0 + - description: pll2_q selected as peripheral clock + name: PLL2_Q + value: 1 + - description: pll3_q selected as peripheral clock + name: PLL3_Q + value: 2 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 3 + - description: csi_ker selected as peripheral clock + name: CSI_KER + value: 4 + - description: HSE selected as peripheral clock + name: HSE + value: 5 enum/SPI6SEL: bit_size: 3 + variants: + - description: rcc_pclk4 selected as peripheral clock + name: RCC_PCLK4 + value: 0 + - description: pll2_q selected as peripheral clock + name: PLL2_Q + value: 1 + - description: pll3_q selected as peripheral clock + name: PLL3_Q + value: 2 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 3 + - description: csi_ker selected as peripheral clock + name: CSI_KER + value: 4 + - description: HSE selected as peripheral clock + name: HSE + value: 5 enum/STOPWUCK: bit_size: 1 + variants: + - description: HSI selected as wake up clock from system Stop + name: HSI + value: 0 + - description: CSI selected as wake up clock from system Stop + name: CSI + value: 1 enum/SW: bit_size: 3 + variants: + - description: HSI selected as system clock + name: HSI + value: 0 + - description: CSI selected as system clock + name: CSI + value: 1 + - description: HSE selected as system clock + name: HSE + value: 2 + - description: PLL1 selected as system clock + name: PLL1 + value: 3 enum/SWPSEL: bit_size: 1 + variants: + - description: pclk selected as peripheral clock + name: PCLK + value: 0 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 1 enum/SWSR: bit_size: 3 + variants: + - description: HSI oscillator used as system clock + name: HSI + value: 0 + - description: CSI oscillator used as system clock + name: CSI + value: 1 + - description: HSE oscillator used as system clock + name: HSE + value: 2 + - description: PLL1 used as system clock + name: PLL1 + value: 3 enum/TIMPRE: bit_size: 1 + variants: + - description: Timer kernel clock equal to 2x pclk by default + name: DefaultX2 + value: 0 + - description: Timer kernel clock equal to 4x pclk by default + name: DefaultX4 + value: 1 +enum/USART16910SEL: + bit_size: 3 + variants: + - description: rcc_pclk2 selected as peripheral clock + name: RCC_PCLK2 + value: 0 + - description: pll2_q selected as peripheral clock + name: PLL2_Q + value: 1 + - description: pll3_q selected as peripheral clock + name: PLL3_Q + value: 2 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 3 + - description: csi_ker selected as peripheral clock + name: CSI_KER + value: 4 + - description: LSE selected as peripheral clock + name: LSE + value: 5 +enum/USART16SEL: + bit_size: 3 + variants: + - description: rcc_pclk2 selected as peripheral clock + name: RCC_PCLK2 + value: 0 + - description: pll2_q selected as peripheral clock + name: PLL2_Q + value: 1 + - description: pll3_q selected as peripheral clock + name: PLL3_Q + value: 2 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 3 + - description: csi_ker selected as peripheral clock + name: CSI_KER + value: 4 + - description: LSE selected as peripheral clock + name: LSE + value: 5 enum/USART234578SEL: bit_size: 3 + variants: + - description: rcc_pclk1 selected as peripheral clock + name: RCC_PCLK1 + value: 0 + - description: pll2_q selected as peripheral clock + name: PLL2_Q + value: 1 + - description: pll3_q selected as peripheral clock + name: PLL3_Q + value: 2 + - description: hsi_ker selected as peripheral clock + name: HSI_KER + value: 3 + - description: csi_ker selected as peripheral clock + name: CSI_KER + value: 4 + - description: LSE selected as peripheral clock + name: LSE + value: 5 enum/USBSEL: bit_size: 2 + variants: + - description: Disable the kernel clock + name: DISABLE + value: 0 + - description: pll1_q selected as peripheral clock + name: PLL1_Q + value: 1 + - description: pll3_q selected as peripheral clock + name: PLL3_Q + value: 2 + - description: HSI48 selected as peripheral clock + name: HSI48 + value: 3 enum/WWRSC: bit_size: 1 + variants: + - description: Clear WWDG1 scope control + name: Clear + value: 0 + - description: Set WWDG1 scope control + name: Set + value: 1 fieldset/AHB1ENR: description: RCC AHB1 Clock Register fields: @@ -254,6 +1405,10 @@ fieldset/AHB1ENR: bit_size: 1 description: Ethernet Reception Clock Enable name: ETH1RXEN + - bit_offset: 18 + bit_size: 1 + description: ' Enable USB_PHY2 clocks ' + name: USB2OTGHSULPIEN - bit_offset: 25 bit_size: 1 description: USB1OTG Peripheral Clocks Enable @@ -262,6 +1417,18 @@ fieldset/AHB1ENR: bit_size: 1 description: USB_PHY1 Clocks Enable name: USB1ULPIEN + - bit_offset: 27 + bit_size: 1 + description: USB2OTG Peripheral Clocks Enable + name: USB2OTGEN + - bit_offset: 28 + bit_size: 1 + description: USB_PHY2 Clocks Enable + name: USB2ULPIEN + - bit_offset: 14 + bit_size: 1 + description: ART Clock Enable + name: ARTEN fieldset/AHB1LPENR: description: RCC AHB1 Sleep Clock Register fields: @@ -293,6 +1460,30 @@ fieldset/AHB1LPENR: bit_size: 1 description: USB1OTG peripheral clock enable during CSleep mode name: USB1OTGLPEN + - bit_offset: 26 + bit_size: 1 + description: USB_PHY1 clock enable during CSleep mode + name: USB1OTGHSULPILPEN + - bit_offset: 27 + bit_size: 1 + description: USB2OTG peripheral clock enable during CSleep mode + name: USB2OTGLPEN + - bit_offset: 28 + bit_size: 1 + description: USB_PHY2 clocks enable during CSleep mode + name: USB2OTGHSULPILPEN + - bit_offset: 14 + bit_size: 1 + description: ART Clock Enable During CSleep Mode + name: ARTLPEN + - bit_offset: 26 + bit_size: 1 + description: USB_PHY1 clock enable during CSleep mode + name: USB1ULPILPEN + - bit_offset: 28 + bit_size: 1 + description: USB_PHY2 clocks enable during CSleep mode + name: USB2ULPILPEN fieldset/AHB1RSTR: description: RCC AHB1 Peripheral Reset Register fields: @@ -320,6 +1511,10 @@ fieldset/AHB1RSTR: bit_size: 1 description: USB2OTG block reset name: USB2OTGRST + - bit_offset: 14 + bit_size: 1 + description: ART block reset + name: ARTRST fieldset/AHB2ENR: description: RCC AHB2 Clock Register fields: @@ -440,6 +1635,22 @@ fieldset/AHB3ENR: bit_size: 1 description: SDMMC1 and SDMMC1 Delay Clock Enable name: SDMMC1EN + - bit_offset: 28 + bit_size: 1 + description: D1 DTCM1 block enable + name: DTCM1EN + - bit_offset: 29 + bit_size: 1 + description: D1 DTCM2 block enable + name: DTCM2EN + - bit_offset: 30 + bit_size: 1 + description: D1 ITCM block enable + name: ITCM1EN + - bit_offset: 31 + bit_size: 1 + description: AXISRAM block enable + name: AXISRAMEN fieldset/AHB3LPENR: description: RCC AHB3 Sleep Clock Register fields: @@ -455,6 +1666,10 @@ fieldset/AHB3LPENR: bit_size: 1 description: JPGDEC Clock Enable During CSleep Mode name: JPGDECLPEN + - bit_offset: 8 + bit_size: 1 + description: FLITF Clock Enable During CSleep Mode + name: FLASHLPEN - bit_offset: 12 bit_size: 1 description: FMC Peripheral Clocks Enable During CSleep Mode @@ -483,6 +1698,14 @@ fieldset/AHB3LPENR: bit_size: 1 description: AXISRAM Block Clock Enable During CSleep mode name: AXISRAMLPEN + - bit_offset: 8 + bit_size: 1 + description: FLITF Clock Enable During CSleep Mode + name: FLITFLPEN + - bit_offset: 8 + bit_size: 1 + description: Flash interface clock enable during csleep mode + name: FLASHPREN fieldset/AHB3RSTR: description: RCC AHB3 Reset Register fields: @@ -867,6 +2090,10 @@ fieldset/APB1LENR: bit_size: 1 description: HDMI-CEC peripheral clock enable name: CECEN + - bit_offset: 29 + bit_size: 1 + description: DAC1&2 peripheral clock enable + name: DAC12EN - bit_offset: 30 bit_size: 1 description: UART7 Peripheral Clocks Enable @@ -875,6 +2102,14 @@ fieldset/APB1LENR: bit_size: 1 description: UART8 Peripheral Clocks Enable name: UART8EN + - bit_offset: 11 + bit_size: 1 + description: WWDG2 peripheral clock enable + name: WWDG2EN + - bit_offset: 29 + bit_size: 1 + description: DAC1 (containing two converters) peripheral clock enable + name: DAC1EN fieldset/APB1LLPENR: description: RCC APB1 Low Sleep Clock Register fields: @@ -962,6 +2197,10 @@ fieldset/APB1LLPENR: bit_size: 1 description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode name: CECLPEN + - bit_offset: 29 + bit_size: 1 + description: DAC1/2 peripheral clock enable during CSleep mode + name: DAC12LPEN - bit_offset: 30 bit_size: 1 description: UART7 Peripheral Clocks Enable During CSleep Mode @@ -970,6 +2209,15 @@ fieldset/APB1LLPENR: bit_size: 1 description: UART8 Peripheral Clocks Enable During CSleep Mode name: UART8LPEN + - bit_offset: 11 + bit_size: 1 + description: WWDG2 peripheral Clocks Enable During CSleep Mode + name: WWDG2LPEN + - bit_offset: 29 + bit_size: 1 + description: DAC1 (containing two converters) peripheral clock enable during CSleep + mode + name: DAC1LPEN fieldset/APB1LRSTR: description: RCC APB1 Peripheral Reset Register fields: @@ -1057,6 +2305,10 @@ fieldset/APB1LRSTR: bit_size: 1 description: HDMI-CEC block reset name: CECRST + - bit_offset: 29 + bit_size: 1 + description: DAC1 and 2 Blocks Reset + name: DAC12RST - bit_offset: 30 bit_size: 1 description: UART7 block reset @@ -1065,6 +2317,10 @@ fieldset/APB1LRSTR: bit_size: 1 description: UART8 block reset name: UART8RST + - bit_offset: 29 + bit_size: 1 + description: DAC1 (containing two converters) reset + name: DAC1RST fieldset/APB2ENR: description: RCC APB2 Clock Register fields: @@ -1265,6 +2521,10 @@ fieldset/APB3ENR: bit_size: 1 description: WWDG1 Clock Enable name: WWDG1EN + - bit_offset: 4 + bit_size: 1 + description: DSI Peripheral clocks enable + name: DSIEN fieldset/APB3LPENR: description: RCC APB3 Sleep Clock Register fields: @@ -1276,6 +2536,10 @@ fieldset/APB3LPENR: bit_size: 1 description: WWDG1 Clock Enable During CSleep Mode name: WWDG1LPEN + - bit_offset: 4 + bit_size: 1 + description: DSI Peripheral Clock Enable During CSleep Mode + name: DSILPEN fieldset/APB3RSTR: description: RCC APB3 Peripheral Reset Register fields: @@ -1283,6 +2547,10 @@ fieldset/APB3RSTR: bit_size: 1 description: LTDC block reset name: LTDCRST + - bit_offset: 4 + bit_size: 1 + description: DSI block reset + name: DSIRST fieldset/APB4ENR: description: RCC APB4 Clock Register fields: @@ -1310,6 +2578,14 @@ fieldset/APB4ENR: bit_size: 1 description: LPTIM3 Peripheral Clocks Enable name: LPTIM3EN + - bit_offset: 11 + bit_size: 1 + description: LPTIM4 Peripheral Clocks Enable + name: LPTIM4EN + - bit_offset: 12 + bit_size: 1 + description: LPTIM5 Peripheral Clocks Enable + name: LPTIM5EN - bit_offset: 14 bit_size: 1 description: COMP1/2 peripheral clock enable @@ -1326,6 +2602,10 @@ fieldset/APB4ENR: bit_size: 1 description: SAI4 Peripheral Clocks Enable name: SAI4EN + - bit_offset: 13 + bit_size: 1 + description: DAC2 (containing one converter) peripheral clock enable + name: DAC2EN fieldset/APB4LPENR: description: RCC APB4 Sleep Clock Register fields: @@ -1353,6 +2633,14 @@ fieldset/APB4LPENR: bit_size: 1 description: LPTIM3 Peripheral Clocks Enable During CSleep Mode name: LPTIM3LPEN + - bit_offset: 11 + bit_size: 1 + description: LPTIM4 Peripheral Clocks Enable During CSleep Mode + name: LPTIM4LPEN + - bit_offset: 12 + bit_size: 1 + description: LPTIM5 Peripheral Clocks Enable During CSleep Mode + name: LPTIM5LPEN - bit_offset: 14 bit_size: 1 description: COMP1/2 peripheral clock enable during CSleep mode @@ -1369,6 +2657,11 @@ fieldset/APB4LPENR: bit_size: 1 description: SAI4 Peripheral Clocks Enable During CSleep Mode name: SAI4LPEN + - bit_offset: 13 + bit_size: 1 + description: DAC2 (containing one converter) peripheral clock enable during CSleep + mode + name: DAC2LPEN fieldset/APB4RSTR: description: RCC APB4 Peripheral Reset Register fields: @@ -1396,6 +2689,14 @@ fieldset/APB4RSTR: bit_size: 1 description: LPTIM3 block reset name: LPTIM3RST + - bit_offset: 11 + bit_size: 1 + description: LPTIM4 block reset + name: LPTIM4RST + - bit_offset: 12 + bit_size: 1 + description: LPTIM5 block reset + name: LPTIM5RST - bit_offset: 14 bit_size: 1 description: COMP12 Blocks Reset @@ -1408,6 +2709,10 @@ fieldset/APB4RSTR: bit_size: 1 description: SAI4 block reset name: SAI4RST + - bit_offset: 13 + bit_size: 1 + description: DAC2 (containing one converter) reset + name: DAC2RST fieldset/BDCR: description: RCC Backup Domain Control Register fields: @@ -1454,64 +2759,1055 @@ fieldset/BDCR: bit_size: 1 description: VSwitch domain software reset name: BDRST +fieldset/C1_AHB1ENR: + description: RCC AHB1 Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: DMA1 Clock Enable + name: DMA1EN + - bit_offset: 1 + bit_size: 1 + description: DMA2 Clock Enable + name: DMA2EN + - bit_offset: 5 + bit_size: 1 + description: ADC1/2 Peripheral Clocks Enable + name: ADC12EN + - bit_offset: 15 + bit_size: 1 + description: Ethernet MAC bus interface Clock Enable + name: ETH1MACEN + - bit_offset: 16 + bit_size: 1 + description: Ethernet Transmission Clock Enable + name: ETH1TXEN + - bit_offset: 17 + bit_size: 1 + description: Ethernet Reception Clock Enable + name: ETH1RXEN + - bit_offset: 25 + bit_size: 1 + description: USB1OTG Peripheral Clocks Enable + name: USB1OTGEN + - bit_offset: 26 + bit_size: 1 + description: USB_PHY1 Clocks Enable + name: USB1ULPIEN + - bit_offset: 27 + bit_size: 1 + description: USB2OTG Peripheral Clocks Enable + name: USB2OTGEN + - bit_offset: 28 + bit_size: 1 + description: USB_PHY2 Clocks Enable + name: USB2ULPIEN + - bit_offset: 14 + bit_size: 1 + description: ART Clock Enable + name: ARTEN +fieldset/C1_AHB1LPENR: + description: RCC AHB1 Sleep Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: DMA1 Clock Enable During CSleep Mode + name: DMA1LPEN + - bit_offset: 1 + bit_size: 1 + description: DMA2 Clock Enable During CSleep Mode + name: DMA2LPEN + - bit_offset: 5 + bit_size: 1 + description: ADC1/2 Peripheral Clocks Enable During CSleep Mode + name: ADC12LPEN + - bit_offset: 15 + bit_size: 1 + description: Ethernet MAC bus interface Clock Enable During CSleep Mode + name: ETH1MACLPEN + - bit_offset: 16 + bit_size: 1 + description: Ethernet Transmission Clock Enable During CSleep Mode + name: ETH1TXLPEN + - bit_offset: 17 + bit_size: 1 + description: Ethernet Reception Clock Enable During CSleep Mode + name: ETH1RXLPEN + - bit_offset: 25 + bit_size: 1 + description: USB1OTG peripheral clock enable during CSleep mode + name: USB1OTGLPEN + - bit_offset: 26 + bit_size: 1 + description: USB_PHY1 clock enable during CSleep mode + name: USB1ULPILPEN + - bit_offset: 27 + bit_size: 1 + description: USB2OTG peripheral clock enable during CSleep mode + name: USB2OTGLPEN + - bit_offset: 28 + bit_size: 1 + description: USB_PHY2 clocks enable during CSleep mode + name: USB2ULPILPEN + - bit_offset: 14 + bit_size: 1 + description: ART Clock Enable During CSleep Mode + name: ARTLPEN +fieldset/C1_AHB2ENR: + description: RCC AHB2 Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: DCMI peripheral clock + name: DCMIEN + - bit_offset: 4 + bit_size: 1 + description: CRYPT peripheral clock enable + name: CRYPTEN + - bit_offset: 5 + bit_size: 1 + description: HASH peripheral clock enable + name: HASHEN + - bit_offset: 6 + bit_size: 1 + description: RNG peripheral clocks enable + name: RNGEN + - bit_offset: 9 + bit_size: 1 + description: SDMMC2 and SDMMC2 delay clock enable + name: SDMMC2EN + - bit_offset: 29 + bit_size: 1 + description: SRAM1 block enable + name: SRAM1EN + - bit_offset: 30 + bit_size: 1 + description: SRAM2 block enable + name: SRAM2EN + - bit_offset: 31 + bit_size: 1 + description: SRAM3 block enable + name: SRAM3EN +fieldset/C1_AHB2LPENR: + description: RCC AHB2 Sleep Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: DCMI peripheral clock enable during csleep mode + name: DCMILPEN + - bit_offset: 4 + bit_size: 1 + description: CRYPT peripheral clock enable during CSleep mode + name: CRYPTLPEN + - bit_offset: 5 + bit_size: 1 + description: HASH peripheral clock enable during CSleep mode + name: HASHLPEN + - bit_offset: 6 + bit_size: 1 + description: RNG peripheral clock enable during CSleep mode + name: RNGLPEN + - bit_offset: 9 + bit_size: 1 + description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode + name: SDMMC2LPEN + - bit_offset: 29 + bit_size: 1 + description: SRAM1 Clock Enable During CSleep Mode + name: SRAM1LPEN + - bit_offset: 30 + bit_size: 1 + description: SRAM2 Clock Enable During CSleep Mode + name: SRAM2LPEN + - bit_offset: 31 + bit_size: 1 + description: SRAM3 Clock Enable During CSleep Mode + name: SRAM3LPEN +fieldset/C1_AHB3ENR: + description: RCC AHB3 Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: MDMA Peripheral Clock Enable + name: MDMAEN + - bit_offset: 4 + bit_size: 1 + description: DMA2D Peripheral Clock Enable + name: DMA2DEN + - bit_offset: 5 + bit_size: 1 + description: JPGDEC Peripheral Clock Enable + name: JPGDECEN + - bit_offset: 12 + bit_size: 1 + description: FMC Peripheral Clocks Enable + name: FMCEN + - bit_offset: 14 + bit_size: 1 + description: QUADSPI and QUADSPI Delay Clock Enable + name: QSPIEN + - bit_offset: 16 + bit_size: 1 + description: SDMMC1 and SDMMC1 Delay Clock Enable + name: SDMMC1EN +fieldset/C1_AHB3LPENR: + description: RCC AHB3 Sleep Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: MDMA Clock Enable During CSleep Mode + name: MDMALPEN + - bit_offset: 4 + bit_size: 1 + description: DMA2D Clock Enable During CSleep Mode + name: DMA2DLPEN + - bit_offset: 5 + bit_size: 1 + description: JPGDEC Clock Enable During CSleep Mode + name: JPGDECLPEN + - bit_offset: 8 + bit_size: 1 + description: Flash interface clock enable during csleep mode + name: FLASHPREN + - bit_offset: 12 + bit_size: 1 + description: FMC Peripheral Clocks Enable During CSleep Mode + name: FMCLPEN + - bit_offset: 14 + bit_size: 1 + description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode + name: QSPILPEN + - bit_offset: 16 + bit_size: 1 + description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode + name: SDMMC1LPEN + - bit_offset: 28 + bit_size: 1 + description: D1DTCM1 Block Clock Enable During CSleep mode + name: D1DTCM1LPEN + - bit_offset: 29 + bit_size: 1 + description: D1 DTCM2 Block Clock Enable During CSleep mode + name: DTCM2LPEN + - bit_offset: 30 + bit_size: 1 + description: D1ITCM Block Clock Enable During CSleep mode + name: ITCMLPEN + - bit_offset: 31 + bit_size: 1 + description: AXISRAM Block Clock Enable During CSleep mode + name: AXISRAMLPEN +fieldset/C1_AHB4ENR: + description: RCC AHB4 Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOAEN + - bit_offset: 1 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOBEN + - bit_offset: 2 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOCEN + - bit_offset: 3 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIODEN + - bit_offset: 4 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOEEN + - bit_offset: 5 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOFEN + - bit_offset: 6 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOGEN + - bit_offset: 7 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOHEN + - bit_offset: 8 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOIEN + - bit_offset: 9 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOJEN + - bit_offset: 10 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOKEN + - bit_offset: 19 + bit_size: 1 + description: CRC peripheral clock enable + name: CRCEN + - bit_offset: 21 + bit_size: 1 + description: BDMA and DMAMUX2 Clock Enable + name: BDMAEN + - bit_offset: 24 + bit_size: 1 + description: ADC3 Peripheral Clocks Enable + name: ADC3EN + - bit_offset: 25 + bit_size: 1 + description: HSEM peripheral clock enable + name: HSEMEN + - bit_offset: 28 + bit_size: 1 + description: Backup RAM Clock Enable + name: BKPRAMEN +fieldset/C1_AHB4LPENR: + description: RCC AHB4 Sleep Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOALPEN + - bit_offset: 1 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOBLPEN + - bit_offset: 2 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOCLPEN + - bit_offset: 3 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIODLPEN + - bit_offset: 4 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOELPEN + - bit_offset: 5 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOFLPEN + - bit_offset: 6 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOGLPEN + - bit_offset: 7 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOHLPEN + - bit_offset: 8 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOILPEN + - bit_offset: 9 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOJLPEN + - bit_offset: 10 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOKLPEN + - bit_offset: 19 + bit_size: 1 + description: CRC peripheral clock enable during CSleep mode + name: CRCLPEN + - bit_offset: 21 + bit_size: 1 + description: BDMA Clock Enable During CSleep Mode + name: BDMALPEN + - bit_offset: 24 + bit_size: 1 + description: ADC3 Peripheral Clocks Enable During CSleep Mode + name: ADC3LPEN + - bit_offset: 28 + bit_size: 1 + description: Backup RAM Clock Enable During CSleep Mode + name: BKPRAMLPEN + - bit_offset: 29 + bit_size: 1 + description: SRAM4 Clock Enable During CSleep Mode + name: SRAM4LPEN +fieldset/C1_APB1HENR: + description: RCC APB1 Clock Register + fields: + - bit_offset: 1 + bit_size: 1 + description: Clock Recovery System peripheral clock enable + name: CRSEN + - bit_offset: 2 + bit_size: 1 + description: SWPMI Peripheral Clocks Enable + name: SWPEN + - bit_offset: 4 + bit_size: 1 + description: OPAMP peripheral clock enable + name: OPAMPEN + - bit_offset: 5 + bit_size: 1 + description: MDIOS peripheral clock enable + name: MDIOSEN + - bit_offset: 8 + bit_size: 1 + description: FDCAN Peripheral Clocks Enable + name: FDCANEN +fieldset/C1_APB1HLPENR: + description: RCC APB1 High Sleep Clock Register + fields: + - bit_offset: 1 + bit_size: 1 + description: Clock Recovery System peripheral clock enable during CSleep mode + name: CRSLPEN + - bit_offset: 2 + bit_size: 1 + description: SWPMI Peripheral Clocks Enable During CSleep Mode + name: SWPLPEN + - bit_offset: 4 + bit_size: 1 + description: OPAMP peripheral clock enable during CSleep mode + name: OPAMPLPEN + - bit_offset: 5 + bit_size: 1 + description: MDIOS peripheral clock enable during CSleep mode + name: MDIOSLPEN + - bit_offset: 8 + bit_size: 1 + description: FDCAN Peripheral Clocks Enable During CSleep Mode + name: FDCANLPEN +fieldset/C1_APB1LENR: + description: RCC APB1 Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM2EN + - bit_offset: 1 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM3EN + - bit_offset: 2 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM4EN + - bit_offset: 3 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM5EN + - bit_offset: 4 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM6EN + - bit_offset: 5 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM7EN + - bit_offset: 6 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM12EN + - bit_offset: 7 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM13EN + - bit_offset: 8 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM14EN + - bit_offset: 9 + bit_size: 1 + description: LPTIM1 Peripheral Clocks Enable + name: LPTIM1EN + - bit_offset: 14 + bit_size: 1 + description: SPI2 Peripheral Clocks Enable + name: SPI2EN + - bit_offset: 15 + bit_size: 1 + description: SPI3 Peripheral Clocks Enable + name: SPI3EN + - bit_offset: 16 + bit_size: 1 + description: SPDIFRX Peripheral Clocks Enable + name: SPDIFRXEN + - bit_offset: 17 + bit_size: 1 + description: USART2 Peripheral Clocks Enable + name: USART2EN + - bit_offset: 18 + bit_size: 1 + description: USART3 Peripheral Clocks Enable + name: USART3EN + - bit_offset: 19 + bit_size: 1 + description: UART4 Peripheral Clocks Enable + name: UART4EN + - bit_offset: 20 + bit_size: 1 + description: UART5 Peripheral Clocks Enable + name: UART5EN + - bit_offset: 21 + bit_size: 1 + description: I2C1 Peripheral Clocks Enable + name: I2C1EN + - bit_offset: 22 + bit_size: 1 + description: I2C2 Peripheral Clocks Enable + name: I2C2EN + - bit_offset: 23 + bit_size: 1 + description: I2C3 Peripheral Clocks Enable + name: I2C3EN + - bit_offset: 27 + bit_size: 1 + description: HDMI-CEC peripheral clock enable + name: CECEN + - bit_offset: 29 + bit_size: 1 + description: DAC1&2 peripheral clock enable + name: DAC12EN + - bit_offset: 30 + bit_size: 1 + description: UART7 Peripheral Clocks Enable + name: UART7EN + - bit_offset: 31 + bit_size: 1 + description: UART8 Peripheral Clocks Enable + name: UART8EN + - bit_offset: 11 + bit_size: 1 + description: WWDG2 peripheral clock enable + name: WWDG2EN +fieldset/C1_APB1LLPENR: + description: RCC APB1 Low Sleep Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM2 peripheral clock enable during CSleep mode + name: TIM2LPEN + - bit_offset: 1 + bit_size: 1 + description: TIM3 peripheral clock enable during CSleep mode + name: TIM3LPEN + - bit_offset: 2 + bit_size: 1 + description: TIM4 peripheral clock enable during CSleep mode + name: TIM4LPEN + - bit_offset: 3 + bit_size: 1 + description: TIM5 peripheral clock enable during CSleep mode + name: TIM5LPEN + - bit_offset: 4 + bit_size: 1 + description: TIM6 peripheral clock enable during CSleep mode + name: TIM6LPEN + - bit_offset: 5 + bit_size: 1 + description: TIM7 peripheral clock enable during CSleep mode + name: TIM7LPEN + - bit_offset: 6 + bit_size: 1 + description: TIM12 peripheral clock enable during CSleep mode + name: TIM12LPEN + - bit_offset: 7 + bit_size: 1 + description: TIM13 peripheral clock enable during CSleep mode + name: TIM13LPEN + - bit_offset: 8 + bit_size: 1 + description: TIM14 peripheral clock enable during CSleep mode + name: TIM14LPEN + - bit_offset: 9 + bit_size: 1 + description: LPTIM1 Peripheral Clocks Enable During CSleep Mode + name: LPTIM1LPEN + - bit_offset: 14 + bit_size: 1 + description: SPI2 Peripheral Clocks Enable During CSleep Mode + name: SPI2LPEN + - bit_offset: 15 + bit_size: 1 + description: SPI3 Peripheral Clocks Enable During CSleep Mode + name: SPI3LPEN + - bit_offset: 16 + bit_size: 1 + description: SPDIFRX Peripheral Clocks Enable During CSleep Mode + name: SPDIFRXLPEN + - bit_offset: 17 + bit_size: 1 + description: USART2 Peripheral Clocks Enable During CSleep Mode + name: USART2LPEN + - bit_offset: 18 + bit_size: 1 + description: USART3 Peripheral Clocks Enable During CSleep Mode + name: USART3LPEN + - bit_offset: 19 + bit_size: 1 + description: UART4 Peripheral Clocks Enable During CSleep Mode + name: UART4LPEN + - bit_offset: 20 + bit_size: 1 + description: UART5 Peripheral Clocks Enable During CSleep Mode + name: UART5LPEN + - bit_offset: 21 + bit_size: 1 + description: I2C1 Peripheral Clocks Enable During CSleep Mode + name: I2C1LPEN + - bit_offset: 22 + bit_size: 1 + description: I2C2 Peripheral Clocks Enable During CSleep Mode + name: I2C2LPEN + - bit_offset: 23 + bit_size: 1 + description: I2C3 Peripheral Clocks Enable During CSleep Mode + name: I2C3LPEN + - bit_offset: 27 + bit_size: 1 + description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode + name: CECLPEN + - bit_offset: 29 + bit_size: 1 + description: DAC1/2 peripheral clock enable during CSleep mode + name: DAC12LPEN + - bit_offset: 30 + bit_size: 1 + description: UART7 Peripheral Clocks Enable During CSleep Mode + name: UART7LPEN + - bit_offset: 31 + bit_size: 1 + description: UART8 Peripheral Clocks Enable During CSleep Mode + name: UART8LPEN + - bit_offset: 11 + bit_size: 1 + description: WWDG2 peripheral Clocks Enable During CSleep Mode + name: WWDG2LPEN +fieldset/C1_APB2ENR: + description: RCC APB2 Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM1 peripheral clock enable + name: TIM1EN + - bit_offset: 1 + bit_size: 1 + description: TIM8 peripheral clock enable + name: TIM8EN + - bit_offset: 4 + bit_size: 1 + description: USART1 Peripheral Clocks Enable + name: USART1EN + - bit_offset: 5 + bit_size: 1 + description: USART6 Peripheral Clocks Enable + name: USART6EN + - bit_offset: 12 + bit_size: 1 + description: SPI1 Peripheral Clocks Enable + name: SPI1EN + - bit_offset: 13 + bit_size: 1 + description: SPI4 Peripheral Clocks Enable + name: SPI4EN + - bit_offset: 16 + bit_size: 1 + description: TIM15 peripheral clock enable + name: TIM15EN + - bit_offset: 17 + bit_size: 1 + description: TIM16 peripheral clock enable + name: TIM16EN + - bit_offset: 18 + bit_size: 1 + description: TIM17 peripheral clock enable + name: TIM17EN + - bit_offset: 20 + bit_size: 1 + description: SPI5 Peripheral Clocks Enable + name: SPI5EN + - bit_offset: 22 + bit_size: 1 + description: SAI1 Peripheral Clocks Enable + name: SAI1EN + - bit_offset: 23 + bit_size: 1 + description: SAI2 Peripheral Clocks Enable + name: SAI2EN + - bit_offset: 24 + bit_size: 1 + description: SAI3 Peripheral Clocks Enable + name: SAI3EN + - bit_offset: 28 + bit_size: 1 + description: DFSDM1 Peripheral Clocks Enable + name: DFSDM1EN + - bit_offset: 29 + bit_size: 1 + description: HRTIM peripheral clock enable + name: HRTIMEN +fieldset/C1_APB2LPENR: + description: RCC APB2 Sleep Clock Register + fields: + - bit_offset: 0 + bit_size: 1 + description: TIM1 peripheral clock enable during CSleep mode + name: TIM1LPEN + - bit_offset: 1 + bit_size: 1 + description: TIM8 peripheral clock enable during CSleep mode + name: TIM8LPEN + - bit_offset: 4 + bit_size: 1 + description: USART1 Peripheral Clocks Enable During CSleep Mode + name: USART1LPEN + - bit_offset: 5 + bit_size: 1 + description: USART6 Peripheral Clocks Enable During CSleep Mode + name: USART6LPEN + - bit_offset: 12 + bit_size: 1 + description: SPI1 Peripheral Clocks Enable During CSleep Mode + name: SPI1LPEN + - bit_offset: 13 + bit_size: 1 + description: SPI4 Peripheral Clocks Enable During CSleep Mode + name: SPI4LPEN + - bit_offset: 16 + bit_size: 1 + description: TIM15 peripheral clock enable during CSleep mode + name: TIM15LPEN + - bit_offset: 17 + bit_size: 1 + description: TIM16 peripheral clock enable during CSleep mode + name: TIM16LPEN + - bit_offset: 18 + bit_size: 1 + description: TIM17 peripheral clock enable during CSleep mode + name: TIM17LPEN + - bit_offset: 20 + bit_size: 1 + description: SPI5 Peripheral Clocks Enable During CSleep Mode + name: SPI5LPEN + - bit_offset: 22 + bit_size: 1 + description: SAI1 Peripheral Clocks Enable During CSleep Mode + name: SAI1LPEN + - bit_offset: 23 + bit_size: 1 + description: SAI2 Peripheral Clocks Enable During CSleep Mode + name: SAI2LPEN + - bit_offset: 24 + bit_size: 1 + description: SAI3 Peripheral Clocks Enable During CSleep Mode + name: SAI3LPEN + - bit_offset: 28 + bit_size: 1 + description: DFSDM1 Peripheral Clocks Enable During CSleep Mode + name: DFSDM1LPEN + - bit_offset: 29 + bit_size: 1 + description: HRTIM peripheral clock enable during CSleep mode + name: HRTIMLPEN +fieldset/C1_APB3ENR: + description: RCC APB3 Clock Register + fields: + - bit_offset: 3 + bit_size: 1 + description: LTDC peripheral clock enable + name: LTDCEN + - bit_offset: 6 + bit_size: 1 + description: WWDG1 Clock Enable + name: WWDG1EN + - bit_offset: 4 + bit_size: 1 + description: DSI Peripheral clocks enable + name: DSIEN +fieldset/C1_APB3LPENR: + description: RCC APB3 Sleep Clock Register + fields: + - bit_offset: 3 + bit_size: 1 + description: LTDC peripheral clock enable during CSleep mode + name: LTDCLPEN + - bit_offset: 6 + bit_size: 1 + description: WWDG1 Clock Enable During CSleep Mode + name: WWDG1LPEN + - bit_offset: 4 + bit_size: 1 + description: DSI Peripheral Clock Enable During CSleep Mode + name: DSILPEN +fieldset/C1_APB4ENR: + description: RCC APB4 Clock Register + fields: + - bit_offset: 1 + bit_size: 1 + description: SYSCFG peripheral clock enable + name: SYSCFGEN + - bit_offset: 3 + bit_size: 1 + description: LPUART1 Peripheral Clocks Enable + name: LPUART1EN + - bit_offset: 5 + bit_size: 1 + description: SPI6 Peripheral Clocks Enable + name: SPI6EN + - bit_offset: 7 + bit_size: 1 + description: I2C4 Peripheral Clocks Enable + name: I2C4EN + - bit_offset: 9 + bit_size: 1 + description: LPTIM2 Peripheral Clocks Enable + name: LPTIM2EN + - bit_offset: 10 + bit_size: 1 + description: LPTIM3 Peripheral Clocks Enable + name: LPTIM3EN + - bit_offset: 11 + bit_size: 1 + description: LPTIM4 Peripheral Clocks Enable + name: LPTIM4EN + - bit_offset: 12 + bit_size: 1 + description: LPTIM5 Peripheral Clocks Enable + name: LPTIM5EN + - bit_offset: 14 + bit_size: 1 + description: COMP1/2 peripheral clock enable + name: COMP12EN + - bit_offset: 15 + bit_size: 1 + description: VREF peripheral clock enable + name: VREFEN + - bit_offset: 16 + bit_size: 1 + description: RTC APB Clock Enable + name: RTCAPBEN + - bit_offset: 21 + bit_size: 1 + description: SAI4 Peripheral Clocks Enable + name: SAI4EN +fieldset/C1_APB4LPENR: + description: RCC APB4 Sleep Clock Register + fields: + - bit_offset: 1 + bit_size: 1 + description: SYSCFG peripheral clock enable during CSleep mode + name: SYSCFGLPEN + - bit_offset: 3 + bit_size: 1 + description: LPUART1 Peripheral Clocks Enable During CSleep Mode + name: LPUART1LPEN + - bit_offset: 5 + bit_size: 1 + description: SPI6 Peripheral Clocks Enable During CSleep Mode + name: SPI6LPEN + - bit_offset: 7 + bit_size: 1 + description: I2C4 Peripheral Clocks Enable During CSleep Mode + name: I2C4LPEN + - bit_offset: 9 + bit_size: 1 + description: LPTIM2 Peripheral Clocks Enable During CSleep Mode + name: LPTIM2LPEN + - bit_offset: 10 + bit_size: 1 + description: LPTIM3 Peripheral Clocks Enable During CSleep Mode + name: LPTIM3LPEN + - bit_offset: 11 + bit_size: 1 + description: LPTIM4 Peripheral Clocks Enable During CSleep Mode + name: LPTIM4LPEN + - bit_offset: 12 + bit_size: 1 + description: LPTIM5 Peripheral Clocks Enable During CSleep Mode + name: LPTIM5LPEN + - bit_offset: 14 + bit_size: 1 + description: COMP1/2 peripheral clock enable during CSleep mode + name: COMP12LPEN + - bit_offset: 15 + bit_size: 1 + description: VREF peripheral clock enable during CSleep mode + name: VREFLPEN + - bit_offset: 16 + bit_size: 1 + description: RTC APB Clock Enable During CSleep Mode + name: RTCAPBLPEN + - bit_offset: 21 + bit_size: 1 + description: SAI4 Peripheral Clocks Enable During CSleep Mode + name: SAI4LPEN fieldset/C1_RSR: description: RCC Reset Status Register fields: - bit_offset: 16 bit_size: 1 description: Remove reset flag - enum: RMVF + enum: C_RSR_RMVF name: RMVF - bit_offset: 17 bit_size: 1 description: CPU reset flag - enum_read: CPURSTFR + enum_read: C_RSR_CPURSTFR name: CPURSTF - bit_offset: 19 bit_size: 1 description: D1 domain power switch reset flag - enum_read: CPURSTFR + enum_read: C_RSR_CPURSTFR name: D1RSTF - bit_offset: 20 bit_size: 1 description: D2 domain power switch reset flag - enum_read: CPURSTFR + enum_read: C_RSR_CPURSTFR name: D2RSTF - bit_offset: 21 bit_size: 1 description: BOR reset flag - enum_read: CPURSTFR + enum_read: C_RSR_CPURSTFR name: BORRSTF - bit_offset: 22 bit_size: 1 description: Pin reset flag (NRST) - enum_read: CPURSTFR + enum_read: C_RSR_CPURSTFR name: PINRSTF - bit_offset: 23 bit_size: 1 description: POR/PDR reset flag - enum_read: CPURSTFR + enum_read: C_RSR_CPURSTFR name: PORRSTF - bit_offset: 24 bit_size: 1 description: System reset from CPU reset flag - enum_read: CPURSTFR + enum_read: C_RSR_CPURSTFR name: SFTRSTF - bit_offset: 26 bit_size: 1 description: Independent Watchdog reset flag - enum_read: CPURSTFR + enum_read: C_RSR_CPURSTFR name: IWDG1RSTF - bit_offset: 28 bit_size: 1 description: Window Watchdog reset flag - enum_read: CPURSTFR + enum_read: C_RSR_CPURSTFR name: WWDG1RSTF - bit_offset: 30 bit_size: 1 description: Reset due to illegal D1 DStandby or CPU CStop flag - enum_read: CPURSTFR + enum_read: C_RSR_CPURSTFR name: LPWRRSTF +fieldset/CDCCIP1R: + description: RCC Domain 2 Kernel Clock Configuration Register + fields: + - bit_offset: 0 + bit_size: 3 + description: SAI1 and DFSDM1 kernel Aclk clock source selection + enum: SAISEL + name: SAI1SEL + - bit_offset: 6 + bit_size: 3 + description: SAI2 kernel clock source A source selection + enum: SAIASEL + name: SAI2ASEL + - bit_offset: 9 + bit_size: 3 + description: SAI2 kernel clock source B source selection + enum: SAIASEL + name: SAI2BSEL + - bit_offset: 12 + bit_size: 3 + description: SPI/I2S1,2 and 3 kernel clock source selection + enum: SAISEL + name: SPI123SEL + - bit_offset: 16 + bit_size: 3 + description: SPI4 and 5 kernel clock source selection + enum: SPI45SEL + name: SPI45SEL + - bit_offset: 20 + bit_size: 2 + description: SPDIFRX kernel clock source selection + enum: SPDIFRXSEL + name: SPDIFRXSEL + - bit_offset: 24 + bit_size: 1 + description: DFSDM1 kernel Clk clock source selection + enum: DFSDMSEL + name: DFSDM1SEL + - bit_offset: 28 + bit_size: 2 + description: FDCAN kernel clock source selection + enum: FDCANSEL + name: FDCANSEL + - bit_offset: 31 + bit_size: 1 + description: SWPMI kernel clock source selection + enum: SWPSEL + name: SWPSEL +fieldset/CDCCIP2R: + description: RCC Domain 2 Kernel Clock Configuration Register + fields: + - bit_offset: 0 + bit_size: 3 + description: USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection + enum: USART234578SEL + name: USART234578SEL + - bit_offset: 3 + bit_size: 3 + description: USART1, 6, 9 and 10 kernel clock source selection + enum: USART16910SEL + name: USART16910SEL + - bit_offset: 8 + bit_size: 2 + description: RNG kernel clock source selection + enum: RNGSEL + name: RNGSEL + - bit_offset: 12 + bit_size: 2 + description: I2C1,2,3 kernel clock source selection + enum: I2C123SEL + name: I2C123SEL + - bit_offset: 20 + bit_size: 2 + description: USBOTG 1 and 2 kernel clock source selection + enum: USBSEL + name: USBSEL + - bit_offset: 22 + bit_size: 2 + description: HDMI-CEC kernel clock source selection + enum: CECSEL + name: CECSEL + - bit_offset: 28 + bit_size: 3 + description: LPTIM1 kernel clock source selection + enum: LPTIM1SEL + name: LPTIM1SEL +fieldset/CDCCIPR: + description: RCC Domain 1 Kernel Clock Configuration Register + fields: + - bit_offset: 0 + bit_size: 2 + description: FMC kernel clock source selection + enum: FMCSEL + name: FMCSEL + - bit_offset: 4 + bit_size: 2 + description: OCTOSPI kernel clock source selection + enum: FMCSEL + name: OCTOSPISEL + - bit_offset: 16 + bit_size: 1 + description: SDMMC kernel clock source selection + enum: SDMMCSEL + name: SDMMCSEL + - bit_offset: 28 + bit_size: 2 + description: per_ck clock source selection + enum: CKPERSEL + name: CKPERSEL fieldset/CFGR: description: RCC Clock Configuration Register fields: @@ -1842,6 +4138,17 @@ fieldset/CRRCR: bit_size: 10 description: Internal RC 48 MHz clock calibration name: HSI48CAL +fieldset/CSICFGR: + description: RCC CSI configuration register + fields: + - bit_offset: 0 + bit_size: 9 + description: CSI clock calibration + name: CSICAL + - bit_offset: 24 + bit_size: 6 + description: CSI clock trimming + name: CSITRIM fieldset/CSR: description: RCC Clock Control and Status Register fields: @@ -1855,6 +4162,33 @@ fieldset/CSR: description: LSI oscillator ready enum_read: LSIRDYR name: LSIRDY +fieldset/D1CCIPR: + description: RCC Domain 1 Kernel Clock Configuration Register + fields: + - bit_offset: 0 + bit_size: 2 + description: FMC kernel clock source selection + enum: FMCSEL + name: FMCSEL + - bit_offset: 4 + bit_size: 2 + description: QUADSPI kernel clock source selection + enum: FMCSEL + name: QSPISEL + - bit_offset: 16 + bit_size: 1 + description: SDMMC kernel clock source selection + enum: SDMMCSEL + name: SDMMCSEL + - bit_offset: 28 + bit_size: 2 + description: per_ck clock source selection + enum: CKPERSEL + name: CKPERSEL + - bit_offset: 8 + bit_size: 1 + description: kernel clock source selection + name: DSISEL fieldset/D1CFGR: description: RCC Domain 1 Clock Configuration Register fields: @@ -1873,6 +4207,87 @@ fieldset/D1CFGR: description: D1 domain Core prescaler enum: HPRE name: D1CPRE +fieldset/D2CCIP1R: + description: RCC Domain 2 Kernel Clock Configuration Register + fields: + - bit_offset: 0 + bit_size: 3 + description: SAI1 and DFSDM1 kernel Aclk clock source selection + enum: SAISEL + name: SAI1SEL + - bit_offset: 6 + bit_size: 3 + description: SAI2 and SAI3 kernel clock source selection + enum: SAISEL + name: SAI23SEL + - bit_offset: 12 + bit_size: 3 + description: SPI/I2S1,2 and 3 kernel clock source selection + enum: SAISEL + name: SPI123SEL + - bit_offset: 16 + bit_size: 3 + description: SPI4 and 5 kernel clock source selection + enum: SPI45SEL + name: SPI45SEL + - bit_offset: 20 + bit_size: 2 + description: SPDIFRX kernel clock source selection + enum: SPDIFSEL + name: SPDIFSEL + - bit_offset: 24 + bit_size: 1 + description: DFSDM1 kernel Clk clock source selection + enum: DFSDMSEL + name: DFSDM1SEL + - bit_offset: 28 + bit_size: 2 + description: FDCAN kernel clock source selection + enum: FDCANSEL + name: FDCANSEL + - bit_offset: 31 + bit_size: 1 + description: SWPMI kernel clock source selection + enum: SWPSEL + name: SWPSEL +fieldset/D2CCIP2R: + description: RCC Domain 2 Kernel Clock Configuration Register + fields: + - bit_offset: 0 + bit_size: 3 + description: USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection + enum: USART234578SEL + name: USART234578SEL + - bit_offset: 3 + bit_size: 3 + description: USART1 and 6 kernel clock source selection + enum: USART16SEL + name: USART16SEL + - bit_offset: 8 + bit_size: 2 + description: RNG kernel clock source selection + enum: RNGSEL + name: RNGSEL + - bit_offset: 12 + bit_size: 2 + description: I2C1,2,3 kernel clock source selection + enum: I2C123SEL + name: I2C123SEL + - bit_offset: 20 + bit_size: 2 + description: USBOTG 1 and 2 kernel clock source selection + enum: USBSEL + name: USBSEL + - bit_offset: 22 + bit_size: 2 + description: HDMI-CEC kernel clock source selection + enum: CECSEL + name: CECSEL + - bit_offset: 28 + bit_size: 3 + description: LPTIM1 kernel clock source selection + enum: LPTIM1SEL + name: LPTIM1SEL fieldset/D2CFGR: description: RCC Domain 2 Clock Configuration Register fields: @@ -1913,6 +4328,14 @@ fieldset/D3AMR: bit_size: 1 description: LPTIM3 Autonomous mode enable name: LPTIM3AMEN + - bit_offset: 11 + bit_size: 1 + description: LPTIM4 Autonomous mode enable + name: LPTIM4AMEN + - bit_offset: 12 + bit_size: 1 + description: LPTIM5 Autonomous mode enable + name: LPTIM5AMEN - bit_offset: 14 bit_size: 1 description: COMP12 Autonomous mode enable @@ -1937,10 +4360,65 @@ fieldset/D3AMR: bit_size: 1 description: ADC3 Autonomous mode enable name: ADC3AMEN + - bit_offset: 28 + bit_size: 1 + description: Backup RAM Autonomous mode enable + name: BKPRAMAMEN - bit_offset: 29 bit_size: 1 description: SRAM4 Autonomous mode enable name: SRAM4AMEN + - bit_offset: 28 + bit_size: 1 + description: Backup RAM Autonomous mode enable + name: BKPSRAMAMEN + - bit_offset: 13 + bit_size: 1 + description: DAC2 (containing one converter) Autonomous mode enable + name: DAC2AMEN +fieldset/D3CCIPR: + description: RCC Domain 3 Kernel Clock Configuration Register + fields: + - bit_offset: 0 + bit_size: 3 + description: LPUART1 kernel clock source selection + enum: LPUARTSEL + name: LPUART1SEL + - bit_offset: 8 + bit_size: 2 + description: I2C4 kernel clock source selection + enum: I2C4SEL + name: I2C4SEL + - bit_offset: 10 + bit_size: 3 + description: LPTIM2 kernel clock source selection + enum: LPTIM2SEL + name: LPTIM2SEL + - bit_offset: 13 + bit_size: 3 + description: LPTIM3,4,5 kernel clock source selection + enum: LPTIM2SEL + name: LPTIM345SEL + - bit_offset: 16 + bit_size: 2 + description: SAR ADC kernel clock source selection + enum: ADCSEL + name: ADCSEL + - bit_offset: 21 + bit_size: 3 + description: Sub-Block A of SAI4 kernel clock source selection + enum: SAIASEL + name: SAI4ASEL + - bit_offset: 24 + bit_size: 3 + description: Sub-Block B of SAI4 kernel clock source selection + enum: SAIASEL + name: SAI4BSEL + - bit_offset: 28 + bit_size: 3 + description: SPI6 kernel clock source selection + enum: SPI6SEL + name: SPI6SEL fieldset/D3CFGR: description: RCC Domain 3 Clock Configuration Register fields: @@ -1950,13 +4428,55 @@ fieldset/D3CFGR: enum: DPPRE name: D3PPRE fieldset/GCR: - description: RCC Global Control Register + description: Global Control Register fields: - bit_offset: 0 bit_size: 1 description: WWDG1 reset scope control enum: WWRSC name: WW1RSC + - bit_offset: 1 + bit_size: 1 + description: WWDG2 reset scope control + name: WW2RSC + - bit_offset: 2 + bit_size: 1 + description: Force allow CPU1 to boot + name: BOOT_C1 + - bit_offset: 3 + bit_size: 1 + description: Force allow CPU2 to boot + name: BOOT_C2 +fieldset/HSICFGR: + description: RCC HSI configuration register + fields: + - bit_offset: 0 + bit_size: 12 + description: HSI clock calibration + name: HSICAL + - bit_offset: 24 + bit_size: 7 + description: HSI clock trimming + name: HSITRIM +fieldset/ICSCR: + description: RCC Internal Clock Source Calibration Register + fields: + - bit_offset: 0 + bit_size: 12 + description: HSI clock calibration + name: HSICAL + - bit_offset: 12 + bit_size: 6 + description: HSI clock trimming + name: HSITRIM + - bit_offset: 18 + bit_size: 8 + description: CSI clock calibration + name: CSICAL + - bit_offset: 26 + bit_size: 5 + description: CSI clock trimming + name: CSITRIM fieldset/PLL1DIVR: description: RCC PLL1 Dividers Configuration Register fields: @@ -2177,3 +4697,97 @@ fieldset/PLLCKSELR: bit_size: 6 description: Prescaler for PLL1 name: DIVM +fieldset/RSR: + description: RCC Reset Status Register + fields: + - bit_offset: 16 + bit_size: 1 + description: Remove reset flag + enum: RSR_RMVF + name: RMVF + - bit_offset: 17 + bit_size: 1 + description: CPU reset flag + enum_read: RSR_CPURSTFR + name: CPURSTF + - bit_offset: 19 + bit_size: 1 + description: D1 domain power switch reset flag + enum_read: RSR_CPURSTFR + name: D1RSTF + - bit_offset: 20 + bit_size: 1 + description: D2 domain power switch reset flag + enum_read: RSR_CPURSTFR + name: D2RSTF + - bit_offset: 21 + bit_size: 1 + description: BOR reset flag + enum_read: RSR_CPURSTFR + name: BORRSTF + - bit_offset: 22 + bit_size: 1 + description: Pin reset flag (NRST) + enum_read: RSR_CPURSTFR + name: PINRSTF + - bit_offset: 23 + bit_size: 1 + description: POR/PDR reset flag + enum_read: RSR_CPURSTFR + name: PORRSTF + - bit_offset: 24 + bit_size: 1 + description: System reset from CPU reset flag + enum_read: RSR_CPURSTFR + name: SFTRSTF + - bit_offset: 26 + bit_size: 1 + description: Independent Watchdog reset flag + enum_read: RSR_CPURSTFR + name: IWDG1RSTF + - bit_offset: 28 + bit_size: 1 + description: Window Watchdog reset flag + enum_read: RSR_CPURSTFR + name: WWDG1RSTF + - bit_offset: 30 + bit_size: 1 + description: Reset due to illegal D1 DStandby or CPU CStop flag + enum_read: RSR_CPURSTFR + name: LPWRRSTF +fieldset/SRDCCIPR: + description: RCC Domain 3 Kernel Clock Configuration Register + fields: + - bit_offset: 0 + bit_size: 3 + description: LPUART1 kernel clock source selection + enum: LPUARTSEL + name: LPUART1SEL + - bit_offset: 8 + bit_size: 2 + description: I2C4 kernel clock source selection + enum: I2C4SEL + name: I2C4SEL + - bit_offset: 10 + bit_size: 3 + description: LPTIM2 kernel clock source selection + enum: LPTIM2SEL + name: LPTIM2SEL + - bit_offset: 13 + bit_size: 3 + description: LPTIM3,4,5 kernel clock source selection + name: LPTIM3SEL + - bit_offset: 16 + bit_size: 2 + description: SAR ADC kernel clock source selection + enum: ADCSEL + name: ADCSEL + - bit_offset: 27 + bit_size: 1 + description: DFSDM2 kernel clock source selection + name: DFSDM2SEL + - bit_offset: 28 + bit_size: 3 + description: SPI6 kernel clock source selection + enum: SPI6SEL + name: SPI6SEL diff --git a/data/registers/rcc_l0.yaml b/data/registers/rcc_l0.yaml index d1cf396..8161f27 100644 --- a/data/registers/rcc_l0.yaml +++ b/data/registers/rcc_l0.yaml @@ -1,1535 +1,1598 @@ ---- block/RCC: description: Reset and clock control items: - - name: CR - description: Clock control register - byte_offset: 0 - fieldset: CR - - name: ICSCR - description: Internal clock sources calibration register - byte_offset: 4 - fieldset: ICSCR - - name: CRRCR - description: Clock recovery RC register - byte_offset: 8 - fieldset: CRRCR - - name: CFGR - description: Clock configuration register - byte_offset: 12 - fieldset: CFGR - - name: CIER - description: Clock interrupt enable register - byte_offset: 16 - access: Read - fieldset: CIER - - name: CIFR - description: Clock interrupt flag register - byte_offset: 20 - access: Read - fieldset: CIFR - - name: CICR - description: Clock interrupt clear register - byte_offset: 24 - access: Read - fieldset: CICR - - name: IOPRSTR - description: GPIO reset register - byte_offset: 28 - fieldset: IOPRSTR - - name: AHBRSTR - description: AHB peripheral reset register - byte_offset: 32 - fieldset: AHBRSTR - - name: APB2RSTR - description: APB2 peripheral reset register - byte_offset: 36 - fieldset: APB2RSTR - - name: APB1RSTR - description: APB1 peripheral reset register - byte_offset: 40 - fieldset: APB1RSTR - - name: IOPENR - description: GPIO clock enable register - byte_offset: 44 - fieldset: IOPENR - - name: AHBENR - description: AHB peripheral clock enable register - byte_offset: 48 - fieldset: AHBENR - - name: APB2ENR - description: APB2 peripheral clock enable register - byte_offset: 52 - fieldset: APB2ENR - - name: APB1ENR - description: APB1 peripheral clock enable register - byte_offset: 56 - fieldset: APB1ENR - - name: IOPSMEN - description: GPIO clock enable in sleep mode register - byte_offset: 60 - fieldset: IOPSMEN - - name: AHBSMENR - description: AHB peripheral clock enable in sleep mode register - byte_offset: 64 - fieldset: AHBSMENR - - name: APB2SMENR - description: APB2 peripheral clock enable in sleep mode register - byte_offset: 68 - fieldset: APB2SMENR - - name: APB1SMENR - description: APB1 peripheral clock enable in sleep mode register - byte_offset: 72 - fieldset: APB1SMENR - - name: CCIPR - description: Clock configuration register - byte_offset: 76 - fieldset: CCIPR - - name: CSR - description: Control and status register - byte_offset: 80 - fieldset: CSR -fieldset/AHBENR: - description: AHB peripheral clock enable register - fields: - - name: DMAEN - description: DMA clock enable bit - bit_offset: 0 - bit_size: 1 - - name: MIFEN - description: NVM interface clock enable bit - bit_offset: 8 - bit_size: 1 - - name: CRCEN - description: CRC clock enable bit - bit_offset: 12 - bit_size: 1 - - name: TOUCHEN - description: Touch Sensing clock enable bit - bit_offset: 16 - bit_size: 1 - - name: RNGEN - description: Random Number Generator clock enable bit - bit_offset: 20 - bit_size: 1 - - name: CRYPEN - description: Crypto clock enable bit - bit_offset: 24 - bit_size: 1 -fieldset/AHBRSTR: - description: AHB peripheral reset register - fields: - - name: DMARST - description: DMA reset - bit_offset: 0 - bit_size: 1 - enum_write: CRYPRSTW - - name: MIFRST - description: Memory interface reset - bit_offset: 8 - bit_size: 1 - enum_write: CRYPRSTW - - name: CRCRST - description: Test integration module reset - bit_offset: 12 - bit_size: 1 - enum_write: CRYPRSTW - - name: TOUCHRST - description: Touch Sensing reset - bit_offset: 16 - bit_size: 1 - enum_write: CRYPRSTW - - name: RNGRST - description: Random Number Generator module reset - bit_offset: 20 - bit_size: 1 - enum_write: CRYPRSTW - - name: CRYPRST - description: Crypto module reset - bit_offset: 24 - bit_size: 1 - enum_write: CRYPRSTW -fieldset/AHBSMENR: - description: AHB peripheral clock enable in sleep mode register - fields: - - name: DMASMEN - description: DMA clock enable during sleep mode bit - bit_offset: 0 - bit_size: 1 - - name: MIFSMEN - description: NVM interface clock enable during sleep mode bit - bit_offset: 8 - bit_size: 1 - - name: SRAMSMEN - description: SRAM interface clock enable during sleep mode bit - bit_offset: 9 - bit_size: 1 - - name: CRCSMEN - description: CRC clock enable during sleep mode bit - bit_offset: 12 - bit_size: 1 - - name: TOUCHSMEN - description: Touch Sensing clock enable during sleep mode bit - bit_offset: 16 - bit_size: 1 - - name: RNGSMEN - description: Random Number Generator clock enable during sleep mode bit - bit_offset: 20 - bit_size: 1 - - name: CRYPSMEN - description: Crypto clock enable during sleep mode bit - bit_offset: 24 - bit_size: 1 -fieldset/APB1ENR: - description: APB1 peripheral clock enable register - fields: - - name: TIM2EN - description: Timer2 clock enable bit - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: Timer3 clock enable bit - bit_offset: 1 - bit_size: 1 - - name: TIM6EN - description: Timer 6 clock enable bit - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: Timer 7 clock enable bit - bit_offset: 5 - bit_size: 1 - - name: WWDGEN - description: Window watchdog clock enable bit - bit_offset: 11 - bit_size: 1 - - name: SPI2EN - description: SPI2 clock enable bit - bit_offset: 14 - bit_size: 1 - - name: USART2EN - description: UART2 clock enable bit - bit_offset: 17 - bit_size: 1 - - name: LPUART1EN - description: LPUART1 clock enable bit - bit_offset: 18 - bit_size: 1 - - name: USART4EN - description: USART4 clock enable bit - bit_offset: 19 - bit_size: 1 - - name: USART5EN - description: USART5 clock enable bit - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C1 clock enable bit - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C2 clock enable bit - bit_offset: 22 - bit_size: 1 - - name: USBEN - description: USB clock enable bit - bit_offset: 23 - bit_size: 1 - - name: CRSEN - description: Clock recovery system clock enable bit - bit_offset: 27 - bit_size: 1 - - name: PWREN - description: Power interface clock enable bit - bit_offset: 28 - bit_size: 1 - - name: DACEN - description: DAC interface clock enable bit - bit_offset: 29 - bit_size: 1 - - name: I2C3EN - description: I2C3 clock enable bit - bit_offset: 30 - bit_size: 1 - - name: LPTIM1EN - description: Low power timer clock enable bit - bit_offset: 31 - bit_size: 1 -fieldset/APB1RSTR: - description: APB1 peripheral reset register - fields: - - name: TIM2RST - description: Timer2 reset - bit_offset: 0 - bit_size: 1 - enum_write: LPTIMRSTW - - name: TIM3RST - description: Timer3 reset - bit_offset: 1 - bit_size: 1 - enum_write: LPTIMRSTW - - name: TIM6RST - description: Timer 6 reset - bit_offset: 4 - bit_size: 1 - enum_write: LPTIMRSTW - - name: TIM7RST - description: Timer 7 reset - bit_offset: 5 - bit_size: 1 - enum_write: LPTIMRSTW - - name: WWDRST - description: Window watchdog reset - bit_offset: 11 - bit_size: 1 - enum_write: LPTIMRSTW - - name: SPI2RST - description: SPI2 reset - bit_offset: 14 - bit_size: 1 - enum_write: LPTIMRSTW - - name: LPUART12RST - description: UART2 reset - bit_offset: 17 - bit_size: 1 - enum_write: LPTIMRSTW - - name: LPUART1RST - description: LPUART1 reset - bit_offset: 18 - bit_size: 1 - enum_write: LPTIMRSTW - - name: USART4RST - description: USART4 reset - bit_offset: 19 - bit_size: 1 - enum_write: LPTIMRSTW - - name: USART5RST - description: USART5 reset - bit_offset: 20 - bit_size: 1 - enum_write: LPTIMRSTW - - name: I2C1RST - description: I2C1 reset - bit_offset: 21 - bit_size: 1 - enum_write: LPTIMRSTW - - name: I2C2RST - description: I2C2 reset - bit_offset: 22 - bit_size: 1 - enum_write: LPTIMRSTW - - name: USBRST - description: USB reset - bit_offset: 23 - bit_size: 1 - enum_write: LPTIMRSTW - - name: CRSRST - description: Clock recovery system reset - bit_offset: 27 - bit_size: 1 - enum_write: LPTIMRSTW - - name: PWRRST - description: Power interface reset - bit_offset: 28 - bit_size: 1 - enum_write: LPTIMRSTW - - name: DACRST - description: DAC interface reset - bit_offset: 29 - bit_size: 1 - enum_write: LPTIMRSTW - - name: I2C3RST - description: I2C3 reset - bit_offset: 30 - bit_size: 1 - enum_write: LPTIMRSTW - - name: LPTIM1RST - description: Low power timer reset - bit_offset: 31 - bit_size: 1 - enum_write: LPTIMRSTW -fieldset/APB1SMENR: - description: APB1 peripheral clock enable in sleep mode register - fields: - - name: TIM2SMEN - description: Timer2 clock enable during sleep mode bit - bit_offset: 0 - bit_size: 1 - - name: TIM3SMEN - description: Timer3 clock enable during Sleep mode bit - bit_offset: 1 - bit_size: 1 - - name: TIM6SMEN - description: Timer 6 clock enable during sleep mode bit - bit_offset: 4 - bit_size: 1 - - name: TIM7SMEN - description: Timer 7 clock enable during Sleep mode bit - bit_offset: 5 - bit_size: 1 - - name: WWDGSMEN - description: Window watchdog clock enable during sleep mode bit - bit_offset: 11 - bit_size: 1 - - name: SPI2SMEN - description: SPI2 clock enable during sleep mode bit - bit_offset: 14 - bit_size: 1 - - name: USART2SMEN - description: UART2 clock enable during sleep mode bit - bit_offset: 17 - bit_size: 1 - - name: LPUART1SMEN - description: LPUART1 clock enable during sleep mode bit - bit_offset: 18 - bit_size: 1 - - name: USART4SMEN - description: USART4 clock enable during Sleep mode bit - bit_offset: 19 - bit_size: 1 - - name: USART5SMEN - description: USART5 clock enable during Sleep mode bit - bit_offset: 20 - bit_size: 1 - - name: I2C1SMEN - description: I2C1 clock enable during sleep mode bit - bit_offset: 21 - bit_size: 1 - - name: I2C2SMEN - description: I2C2 clock enable during sleep mode bit - bit_offset: 22 - bit_size: 1 - - name: USBSMEN - description: USB clock enable during sleep mode bit - bit_offset: 23 - bit_size: 1 - - name: CRSSMEN - description: Clock recovery system clock enable during sleep mode bit - bit_offset: 27 - bit_size: 1 - - name: PWRSMEN - description: Power interface clock enable during sleep mode bit - bit_offset: 28 - bit_size: 1 - - name: DACSMEN - description: DAC interface clock enable during sleep mode bit - bit_offset: 29 - bit_size: 1 - - name: I2C3SMEN - description: 2C3 clock enable during Sleep mode bit - bit_offset: 30 - bit_size: 1 - - name: LPTIM1SMEN - description: Low power timer clock enable during sleep mode bit - bit_offset: 31 - bit_size: 1 -fieldset/APB2ENR: - description: APB2 peripheral clock enable register - fields: - - name: SYSCFGEN - description: System configuration controller clock enable bit - bit_offset: 0 - bit_size: 1 - - name: TIM21EN - description: TIM21 timer clock enable bit - bit_offset: 2 - bit_size: 1 - - name: TIM22EN - description: TIM22 timer clock enable bit - bit_offset: 5 - bit_size: 1 - - name: MIFIEN - description: MiFaRe Firewall clock enable bit - bit_offset: 7 - bit_size: 1 - - name: ADCEN - description: ADC clock enable bit - bit_offset: 9 - bit_size: 1 - - name: SPI1EN - description: SPI1 clock enable bit - bit_offset: 12 - bit_size: 1 - - name: USART1EN - description: USART1 clock enable bit - bit_offset: 14 - bit_size: 1 - - name: DBGEN - description: DBG clock enable bit - bit_offset: 22 - bit_size: 1 -fieldset/APB2RSTR: - description: APB2 peripheral reset register - fields: - - name: SYSCFGRST - description: System configuration controller reset - bit_offset: 0 - bit_size: 1 - enum_write: DBGRSTW - - name: TIM21RST - description: TIM21 timer reset - bit_offset: 2 - bit_size: 1 - enum_write: DBGRSTW - - name: TIM22RST - description: TIM22 timer reset - bit_offset: 5 - bit_size: 1 - enum_write: DBGRSTW - - name: ADCRST - description: ADC interface reset - bit_offset: 9 - bit_size: 1 - enum_write: DBGRSTW - - name: SPI1RST - description: SPI 1 reset - bit_offset: 12 - bit_size: 1 - enum_write: DBGRSTW - - name: USART1RST - description: USART1 reset - bit_offset: 14 - bit_size: 1 - enum_write: DBGRSTW - - name: DBGRST - description: DBG reset - bit_offset: 22 - bit_size: 1 - enum_write: DBGRSTW -fieldset/APB2SMENR: - description: APB2 peripheral clock enable in sleep mode register - fields: - - name: SYSCFGSMEN - description: System configuration controller clock enable during sleep mode bit - bit_offset: 0 - bit_size: 1 - - name: TIM21SMEN - description: TIM21 timer clock enable during sleep mode bit - bit_offset: 2 - bit_size: 1 - - name: TIM22SMEN - description: TIM22 timer clock enable during sleep mode bit - bit_offset: 5 - bit_size: 1 - - name: ADCSMEN - description: ADC clock enable during sleep mode bit - bit_offset: 9 - bit_size: 1 - - name: SPI1SMEN - description: SPI1 clock enable during sleep mode bit - bit_offset: 12 - bit_size: 1 - - name: USART1SMEN - description: USART1 clock enable during sleep mode bit - bit_offset: 14 - bit_size: 1 - - name: DBGSMEN - description: DBG clock enable during sleep mode bit - bit_offset: 22 - bit_size: 1 -fieldset/CCIPR: - description: Clock configuration register - fields: - - name: USART1SEL - description: USART1 clock source selection bits - bit_offset: 0 - bit_size: 2 - enum: LPUARTSEL - - name: USART2SEL - description: USART2 clock source selection bits - bit_offset: 2 - bit_size: 2 - enum: LPUARTSEL - - name: LPUART1SEL - description: LPUART1 clock source selection bits - bit_offset: 10 - bit_size: 2 - enum: LPUARTSEL - - name: I2C1SEL - description: I2C1 clock source selection bits - bit_offset: 12 - bit_size: 2 - enum: ICSEL - - name: I2C3SEL - description: I2C3 clock source selection bits - bit_offset: 16 - bit_size: 2 - enum: ICSEL - - name: LPTIM1SEL - description: Low Power Timer clock source selection bits - bit_offset: 18 - bit_size: 2 - enum: LPTIMSEL - - name: HSI48MSEL - description: 48 MHz HSI48 clock source selection bit - bit_offset: 26 - bit_size: 1 -fieldset/CFGR: - description: Clock configuration register - fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 2 - enum: SW - - name: SWS - description: System clock switch status - bit_offset: 2 - bit_size: 2 - enum: SWS - - name: HPRE - description: AHB prescaler - bit_offset: 4 - bit_size: 4 - enum: HPRE - - name: PPRE - description: APB low-speed prescaler (APB1) - bit_offset: 8 - bit_size: 3 - array: - len: 2 - stride: 3 - enum: PPRE - - name: STOPWUCK - description: Wake-up from stop clock selection - bit_offset: 15 - bit_size: 1 - enum: STOPWUCK - - name: PLLSRC - description: PLL entry clock source - bit_offset: 16 - bit_size: 1 - enum: PLLSRC - - name: PLLMUL - description: PLL multiplication factor - bit_offset: 18 - bit_size: 4 - enum: PLLMUL - - name: PLLDIV - description: PLL output division - bit_offset: 22 - bit_size: 2 - enum: PLLDIV - - name: MCOSEL - description: Microcontroller clock output selection - bit_offset: 24 - bit_size: 4 - enum: MCOSEL - - name: MCOPRE - description: Microcontroller clock output prescaler - bit_offset: 28 - bit_size: 3 - enum: MCOPRE -fieldset/CICR: - description: Clock interrupt clear register - fields: - - name: LSIRDYC - description: LSI ready Interrupt clear - bit_offset: 0 - bit_size: 1 - enum_write: CSSHSECW - - name: LSERDYC - description: LSE ready Interrupt clear - bit_offset: 1 - bit_size: 1 - enum_write: CSSHSECW - - name: HSI16RDYC - description: HSI16 ready Interrupt clear - bit_offset: 2 - bit_size: 1 - enum_write: CSSHSECW - - name: HSERDYC - description: HSE ready Interrupt clear - bit_offset: 3 - bit_size: 1 - enum_write: CSSHSECW - - name: PLLRDYC - description: PLL ready Interrupt clear - bit_offset: 4 - bit_size: 1 - enum_write: CSSHSECW - - name: MSIRDYC - description: MSI ready Interrupt clear - bit_offset: 5 - bit_size: 1 - enum_write: CSSHSECW - - name: HSI48RDYC - description: HSI48 ready Interrupt clear - bit_offset: 6 - bit_size: 1 - enum_write: CSSHSECW - - name: CSSLSEC - description: LSE Clock Security System Interrupt clear - bit_offset: 7 - bit_size: 1 - enum_write: CSSHSECW - - name: CSSHSEC - description: Clock Security System Interrupt clear - bit_offset: 8 - bit_size: 1 - enum_write: CSSHSECW -fieldset/CIER: - description: Clock interrupt enable register - fields: - - name: LSIRDYIE - description: LSI ready interrupt flag - bit_offset: 0 - bit_size: 1 - enum: HSIRDYIE - - name: LSERDYIE - description: LSE ready interrupt flag - bit_offset: 1 - bit_size: 1 - enum: HSIRDYIE - - name: HSI16RDYIE - description: HSI16 ready interrupt flag - bit_offset: 2 - bit_size: 1 - enum: HSIRDYIE - - name: HSERDYIE - description: HSE ready interrupt flag - bit_offset: 3 - bit_size: 1 - enum: HSIRDYIE - - name: PLLRDYIE - description: PLL ready interrupt flag - bit_offset: 4 - bit_size: 1 - enum: HSIRDYIE - - name: MSIRDYIE - description: MSI ready interrupt flag - bit_offset: 5 - bit_size: 1 - enum: HSIRDYIE - - name: HSI48RDYIE - description: HSI48 ready interrupt flag - bit_offset: 6 - bit_size: 1 - enum: HSIRDYIE - - name: CSSLSE - description: LSE CSS interrupt flag - bit_offset: 7 - bit_size: 1 - enum: CSSLSE -fieldset/CIFR: - description: Clock interrupt flag register - fields: - - name: LSIRDYF - description: LSI ready interrupt flag - bit_offset: 0 - bit_size: 1 - enum_read: HSI48RDYFR - - name: LSERDYF - description: LSE ready interrupt flag - bit_offset: 1 - bit_size: 1 - enum_read: HSI48RDYFR - - name: HSI16RDYF - description: HSI16 ready interrupt flag - bit_offset: 2 - bit_size: 1 - enum_read: HSI48RDYFR - - name: HSERDYF - description: HSE ready interrupt flag - bit_offset: 3 - bit_size: 1 - enum_read: HSI48RDYFR - - name: PLLRDYF - description: PLL ready interrupt flag - bit_offset: 4 - bit_size: 1 - enum_read: HSI48RDYFR - - name: MSIRDYF - description: MSI ready interrupt flag - bit_offset: 5 - bit_size: 1 - enum_read: HSI48RDYFR - - name: HSI48RDYF - description: HSI48 ready interrupt flag - bit_offset: 6 - bit_size: 1 - enum_read: HSI48RDYFR - - name: CSSLSEF - description: LSE Clock Security System Interrupt flag - bit_offset: 7 - bit_size: 1 - enum: CSSLSEF - - name: CSSHSEF - description: Clock Security System Interrupt flag - bit_offset: 8 - bit_size: 1 - enum: CSSHSEF -fieldset/CR: - description: Clock control register - fields: - - name: HSI16ON - description: 16 MHz high-speed internal clock enable - bit_offset: 0 - bit_size: 1 - enum: PLLON - - name: HSI16KERON - description: High-speed internal clock enable bit for some IP kernels - bit_offset: 1 - bit_size: 1 - enum: PLLON - - name: HSI16RDYF - description: Internal high-speed clock ready flag - bit_offset: 2 - bit_size: 1 - enum_read: HSI16RDYFR - - name: HSI16DIVEN - description: HSI16DIVEN - bit_offset: 3 - bit_size: 1 - - name: HSI16DIVF - description: HSI16DIVF - bit_offset: 4 - bit_size: 1 - enum_read: HSIDIVFR - - name: HSI16OUTEN - description: 16 MHz high-speed internal clock output enable - bit_offset: 5 - bit_size: 1 - - name: MSION - description: MSI clock enable bit - bit_offset: 8 - bit_size: 1 - enum: PLLON - - name: MSIRDY - description: MSI clock ready flag - bit_offset: 9 - bit_size: 1 - enum_read: HSERDYR - - name: HSEON - description: HSE clock enable bit - bit_offset: 16 - bit_size: 1 - enum: PLLON - - name: HSERDY - description: HSE clock ready flag - bit_offset: 17 - bit_size: 1 - enum_read: HSERDYR - - name: HSEBYP - description: HSE clock bypass bit - bit_offset: 18 - bit_size: 1 - enum: HSEBYP - - name: CSSHSEON - description: Clock security system on HSE enable bit - bit_offset: 19 - bit_size: 1 - enum: PLLON - - name: RTCPRE - description: TC/LCD prescaler - bit_offset: 20 - bit_size: 2 - enum: RTCPRE - - name: PLLON - description: PLL enable bit - bit_offset: 24 - bit_size: 1 - enum: PLLON - - name: PLLRDY - description: PLL clock ready flag - bit_offset: 25 - bit_size: 1 - enum_read: PLLRDYR -fieldset/CRRCR: - description: Clock recovery RC register - fields: - - name: HSI48ON - description: 48MHz HSI clock enable bit - bit_offset: 0 - bit_size: 1 - - name: HSI48RDY - description: 48MHz HSI clock ready flag - bit_offset: 1 - bit_size: 1 - - name: HSI48DIV6EN - description: 48 MHz HSI clock divided by 6 output enable - bit_offset: 2 - bit_size: 1 - - name: HSI48CAL - description: 48 MHz HSI clock calibration - bit_offset: 8 - bit_size: 8 -fieldset/CSR: - description: Control and status register - fields: - - name: LSION - description: Internal low-speed oscillator enable - bit_offset: 0 - bit_size: 1 - enum: CSSLSEON - - name: LSIRDY - description: Internal low-speed oscillator ready bit - bit_offset: 1 - bit_size: 1 - enum: LSERDY - - name: LSEON - description: External low-speed oscillator enable bit - bit_offset: 8 - bit_size: 1 - enum: CSSLSEON - - name: LSERDY - description: External low-speed oscillator ready bit - bit_offset: 9 - bit_size: 1 - enum: LSERDY - - name: LSEBYP - description: External low-speed oscillator bypass bit - bit_offset: 10 - bit_size: 1 - enum: LSEBYP - - name: LSEDRV - description: LSEDRV - bit_offset: 11 - bit_size: 2 - enum: LSEDRV - - name: CSSLSEON - description: CSSLSEON - bit_offset: 13 - bit_size: 1 - enum: CSSLSEON - - name: CSSLSED - description: CSS on LSE failure detection flag - bit_offset: 14 - bit_size: 1 - enum: CSSLSED - - name: RTCSEL - description: RTC and LCD clock source selection bits - bit_offset: 16 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable bit - bit_offset: 18 - bit_size: 1 - - name: RTCRST - description: RTC software reset bit - bit_offset: 19 - bit_size: 1 - enum_write: RTCRSTW - - name: RMVF - description: Remove reset flag - bit_offset: 24 - bit_size: 1 - enum_write: RMVFW - - name: OBLRSTF - description: OBLRSTF - bit_offset: 25 - bit_size: 1 - enum_read: LPWRRSTFR - - name: PINRSTF - description: PIN reset flag - bit_offset: 26 - bit_size: 1 - enum_read: LPWRRSTFR - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 27 - bit_size: 1 - enum_read: LPWRRSTFR - - name: SFTRSTF - description: Software reset flag - bit_offset: 28 - bit_size: 1 - enum_read: LPWRRSTFR - - name: IWDGRSTF - description: Independent watchdog reset flag - bit_offset: 29 - bit_size: 1 - enum_read: LPWRRSTFR - - name: WWDGRSTF - description: Window watchdog reset flag - bit_offset: 30 - bit_size: 1 - enum_read: LPWRRSTFR - - name: LPWRRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 - enum_read: LPWRRSTFR -fieldset/ICSCR: - description: Internal clock sources calibration register - fields: - - name: HSI16CAL - description: nternal high speed clock calibration - bit_offset: 0 - bit_size: 8 - - name: HSI16TRIM - description: High speed internal clock trimming - bit_offset: 8 - bit_size: 5 - - name: MSIRANGE - description: MSI clock ranges - bit_offset: 13 - bit_size: 3 - enum: MSIRANGE - - name: MSICAL - description: MSI clock calibration - bit_offset: 16 - bit_size: 8 - - name: MSITRIM - description: MSI clock trimming - bit_offset: 24 - bit_size: 8 -fieldset/IOPENR: - description: GPIO clock enable register - fields: - - name: IOPAEN - description: IO port A clock enable bit - bit_offset: 0 - bit_size: 1 - - name: IOPBEN - description: IO port B clock enable bit - bit_offset: 1 - bit_size: 1 - - name: IOPCEN - description: IO port A clock enable bit - bit_offset: 2 - bit_size: 1 - - name: IOPDEN - description: I/O port D clock enable bit - bit_offset: 3 - bit_size: 1 - - name: IOPEEN - description: I/O port E clock enable bit - bit_offset: 4 - bit_size: 1 - - name: IOPHEN - description: I/O port H clock enable bit - bit_offset: 7 - bit_size: 1 -fieldset/IOPRSTR: - description: GPIO reset register - fields: - - name: IOPARST - description: I/O port A reset - bit_offset: 0 - bit_size: 1 - - name: IOPBRST - description: I/O port B reset - bit_offset: 1 - bit_size: 1 - - name: IOPCRST - description: I/O port A reset - bit_offset: 2 - bit_size: 1 - - name: IOPDRST - description: I/O port D reset - bit_offset: 3 - bit_size: 1 - - name: IOPERST - description: I/O port E reset - bit_offset: 4 - bit_size: 1 - - name: IOPHRST - description: I/O port H reset - bit_offset: 7 - bit_size: 1 -fieldset/IOPSMEN: - description: GPIO clock enable in sleep mode register - fields: - - name: IOPASMEN - description: IOPASMEN - bit_offset: 0 - bit_size: 1 - - name: IOPBSMEN - description: IOPBSMEN - bit_offset: 1 - bit_size: 1 - - name: IOPCSMEN - description: IOPCSMEN - bit_offset: 2 - bit_size: 1 - - name: IOPDSMEN - description: IOPDSMEN - bit_offset: 3 - bit_size: 1 - - name: IOPESMEN - description: Port E clock enable during Sleep mode bit - bit_offset: 4 - bit_size: 1 - - name: IOPHSMEN - description: IOPHSMEN - bit_offset: 7 - bit_size: 1 + - byte_offset: 0 + description: Clock control register + fieldset: CR + name: CR + - byte_offset: 4 + description: Internal clock sources calibration register + fieldset: ICSCR + name: ICSCR + - byte_offset: 12 + description: Clock configuration register + fieldset: CFGR + name: CFGR + - access: Read + byte_offset: 16 + description: Clock interrupt enable register + fieldset: CIER + name: CIER + - access: Read + byte_offset: 20 + description: Clock interrupt flag register + fieldset: CIFR + name: CIFR + - access: Read + byte_offset: 24 + description: Clock interrupt clear register + fieldset: CICR + name: CICR + - byte_offset: 28 + description: GPIO reset register + fieldset: IOPRSTR + name: IOPRSTR + - byte_offset: 32 + description: AHB peripheral reset register + fieldset: AHBRSTR + name: AHBRSTR + - byte_offset: 36 + description: APB2 peripheral reset register + fieldset: APB2RSTR + name: APB2RSTR + - byte_offset: 40 + description: APB1 peripheral reset register + fieldset: APB1RSTR + name: APB1RSTR + - byte_offset: 44 + description: GPIO clock enable register + fieldset: IOPENR + name: IOPENR + - byte_offset: 48 + description: AHB peripheral clock enable register + fieldset: AHBENR + name: AHBENR + - byte_offset: 52 + description: APB2 peripheral clock enable register + fieldset: APB2ENR + name: APB2ENR + - byte_offset: 56 + description: APB1 peripheral clock enable register + fieldset: APB1ENR + name: APB1ENR + - byte_offset: 60 + description: GPIO clock enable in sleep mode register + fieldset: IOPSMEN + name: IOPSMEN + - byte_offset: 64 + description: AHB peripheral clock enable in sleep mode register + fieldset: AHBSMENR + name: AHBSMENR + - byte_offset: 68 + description: APB2 peripheral clock enable in sleep mode register + fieldset: APB2SMENR + name: APB2SMENR + - byte_offset: 72 + description: APB1 peripheral clock enable in sleep mode register + fieldset: APB1SMENR + name: APB1SMENR + - byte_offset: 76 + description: Clock configuration register + fieldset: CCIPR + name: CCIPR + - byte_offset: 80 + description: Control and status register + fieldset: CSR + name: CSR + - byte_offset: 8 + description: Clock recovery RC register + fieldset: CRRCR + name: CRRCR enum/CRYPRSTW: bit_size: 1 variants: - - name: Reset - description: Reset the module - value: 1 + - description: Reset the module + name: Reset + value: 1 enum/CSSHSECW: bit_size: 1 variants: - - name: Clear - description: Clear interrupt flag - value: 1 + - description: Clear interrupt flag + name: Clear + value: 1 enum/CSSHSEF: bit_size: 1 variants: - - name: NoClock - description: No clock security interrupt caused by HSE clock failure - value: 0 - - name: Clock - description: Clock security interrupt caused by HSE clock failure - value: 1 + - description: No clock security interrupt caused by HSE clock failure + name: NoClock + value: 0 + - description: Clock security interrupt caused by HSE clock failure + name: Clock + value: 1 enum/CSSLSE: bit_size: 1 variants: - - name: Disabled - description: LSE CSS interrupt disabled - value: 0 - - name: Enabled - description: LSE CSS interrupt enabled - value: 1 + - description: LSE CSS interrupt disabled + name: Disabled + value: 0 + - description: LSE CSS interrupt enabled + name: Enabled + value: 1 enum/CSSLSED: bit_size: 1 variants: - - name: NoFailure - description: No failure detected on LSE (32 kHz oscillator) - value: 0 - - name: Failure - description: Failure detected on LSE (32 kHz oscillator) - value: 1 + - description: No failure detected on LSE (32 kHz oscillator) + name: NoFailure + value: 0 + - description: Failure detected on LSE (32 kHz oscillator) + name: Failure + value: 1 enum/CSSLSEF: bit_size: 1 variants: - - name: NoFailure - description: No failure detected on LSE clock failure - value: 0 - - name: Failure - description: Failure detected on LSE clock failure - value: 1 + - description: No failure detected on LSE clock failure + name: NoFailure + value: 0 + - description: Failure detected on LSE clock failure + name: Failure + value: 1 enum/CSSLSEON: bit_size: 1 variants: - - name: "Off" - description: Oscillator OFF - value: 0 - - name: "On" - description: Oscillator ON - value: 1 + - description: Oscillator OFF + name: 'Off' + value: 0 + - description: Oscillator ON + name: 'On' + value: 1 enum/DBGRSTW: bit_size: 1 variants: - - name: Reset - description: Reset the module - value: 1 + - description: Reset the module + name: Reset + value: 1 enum/HPRE: bit_size: 4 variants: - - name: Div1 - description: system clock not divided - value: 0 - - name: Div2 - description: system clock divided by 2 - value: 8 - - name: Div4 - description: system clock divided by 4 - value: 9 - - name: Div8 - description: system clock divided by 8 - value: 10 - - name: Div16 - description: system clock divided by 16 - value: 11 - - name: Div64 - description: system clock divided by 64 - value: 12 - - name: Div128 - description: system clock divided by 128 - value: 13 - - name: Div256 - description: system clock divided by 256 - value: 14 - - name: Div512 - description: system clock divided by 512 - value: 15 + - description: system clock not divided + name: Div1 + value: 0 + - description: system clock divided by 2 + name: Div2 + value: 8 + - description: system clock divided by 4 + name: Div4 + value: 9 + - description: system clock divided by 8 + name: Div8 + value: 10 + - description: system clock divided by 16 + name: Div16 + value: 11 + - description: system clock divided by 64 + name: Div64 + value: 12 + - description: system clock divided by 128 + name: Div128 + value: 13 + - description: system clock divided by 256 + name: Div256 + value: 14 + - description: system clock divided by 512 + name: Div512 + value: 15 enum/HSEBYP: bit_size: 1 variants: - - name: NotBypassed - description: HSE oscillator not bypassed - value: 0 - - name: Bypassed - description: HSE oscillator bypassed - value: 1 + - description: HSE oscillator not bypassed + name: NotBypassed + value: 0 + - description: HSE oscillator bypassed + name: Bypassed + value: 1 enum/HSERDYR: bit_size: 1 variants: - - name: NotReady - description: Oscillator is not stable - value: 0 - - name: Ready - description: Oscillator is stable - value: 1 + - description: Oscillator is not stable + name: NotReady + value: 0 + - description: Oscillator is stable + name: Ready + value: 1 enum/HSI16RDYFR: bit_size: 1 variants: - - name: NotReady - description: HSI 16 MHz oscillator not ready - value: 0 - - name: Ready - description: HSI 16 MHz oscillator ready - value: 1 + - description: HSI 16 MHz oscillator not ready + name: NotReady + value: 0 + - description: HSI 16 MHz oscillator ready + name: Ready + value: 1 enum/HSI48RDYFR: bit_size: 1 variants: - - name: NotInterrupted - description: No clock ready interrupt - value: 0 - - name: Interrupted - description: Clock ready interrupt - value: 1 + - description: No clock ready interrupt + name: NotInterrupted + value: 0 + - description: Clock ready interrupt + name: Interrupted + value: 1 enum/HSIDIVFR: bit_size: 1 variants: - - name: NotDivided - description: 16 MHz HSI clock not divided - value: 0 - - name: Div4 - description: 16 MHz HSI clock divided by 4 - value: 1 + - description: 16 MHz HSI clock not divided + name: NotDivided + value: 0 + - description: 16 MHz HSI clock divided by 4 + name: Div4 + value: 1 +enum/HSIRDYFR: + bit_size: 1 + variants: + - description: HSI 16 MHz oscillator not ready + name: NotReady + value: 0 + - description: HSI 16 MHz oscillator ready + name: Ready + value: 1 enum/HSIRDYIE: bit_size: 1 variants: - - name: Disabled - description: Ready interrupt disabled - value: 0 - - name: Enabled - description: Ready interrupt enabled - value: 1 + - description: Ready interrupt disabled + name: Disabled + value: 0 + - description: Ready interrupt enabled + name: Enabled + value: 1 enum/ICSEL: bit_size: 2 variants: - - name: APB - description: APB clock selected as peripheral clock - value: 0 - - name: SYSTEM - description: System clock selected as peripheral clock - value: 1 - - name: HSI16 - description: HSI16 clock selected as peripheral clock - value: 2 + - description: APB clock selected as peripheral clock + name: APB + value: 0 + - description: System clock selected as peripheral clock + name: SYSTEM + value: 1 + - description: HSI16 clock selected as peripheral clock + name: HSI16 + value: 2 enum/LPTIMRSTW: bit_size: 1 variants: - - name: Reset - description: Reset the module - value: 1 + - description: Reset the module + name: Reset + value: 1 enum/LPTIMSEL: bit_size: 2 variants: - - name: APB - description: APB clock selected as Timer clock - value: 0 - - name: LSI - description: LSI clock selected as Timer clock - value: 1 - - name: HSI16 - description: HSI16 clock selected as Timer clock - value: 2 - - name: LSE - description: LSE clock selected as Timer clock - value: 3 + - description: APB clock selected as Timer clock + name: APB + value: 0 + - description: LSI clock selected as Timer clock + name: LSI + value: 1 + - description: HSI16 clock selected as Timer clock + name: HSI16 + value: 2 + - description: LSE clock selected as Timer clock + name: LSE + value: 3 enum/LPUARTSEL: bit_size: 2 variants: - - name: APB - description: APB clock selected as peripheral clock - value: 0 - - name: SYSTEM - description: System clock selected as peripheral clock - value: 1 - - name: HSI16 - description: HSI16 clock selected as peripheral clock - value: 2 - - name: LSE - description: LSE clock selected as peripheral clock - value: 3 + - description: APB clock selected as peripheral clock + name: APB + value: 0 + - description: System clock selected as peripheral clock + name: SYSTEM + value: 1 + - description: HSI16 clock selected as peripheral clock + name: HSI16 + value: 2 + - description: LSE clock selected as peripheral clock + name: LSE + value: 3 enum/LPWRRSTFR: bit_size: 1 variants: - - name: NoReset - description: No reset has occured - value: 0 - - name: Reset - description: A reset has occured - value: 1 + - description: No reset has occured + name: NoReset + value: 0 + - description: A reset has occured + name: Reset + value: 1 enum/LSEBYP: bit_size: 1 variants: - - name: NotBypassed - description: LSE oscillator not bypassed - value: 0 - - name: Bypassed - description: LSE oscillator bypassed - value: 1 + - description: LSE oscillator not bypassed + name: NotBypassed + value: 0 + - description: LSE oscillator bypassed + name: Bypassed + value: 1 enum/LSEDRV: bit_size: 2 variants: - - name: Low - description: Lowest drive - value: 0 - - name: MediumLow - description: Medium low drive - value: 1 - - name: MediumHigh - description: Medium high drive - value: 2 - - name: High - description: Highest drive - value: 3 + - description: Lowest drive + name: Low + value: 0 + - description: Medium low drive + name: MediumLow + value: 1 + - description: Medium high drive + name: MediumHigh + value: 2 + - description: Highest drive + name: High + value: 3 enum/LSERDY: bit_size: 1 variants: - - name: NotReady - description: Oscillator not ready - value: 0 - - name: Ready - description: Oscillator ready - value: 1 + - description: Oscillator not ready + name: NotReady + value: 0 + - description: Oscillator ready + name: Ready + value: 1 enum/MCOPRE: bit_size: 3 variants: - - name: Div1 - description: No division - value: 0 - - name: Div2 - description: Division by 2 - value: 1 - - name: Div4 - description: Division by 4 - value: 2 - - name: Div8 - description: Division by 8 - value: 3 - - name: Div16 - description: Division by 16 - value: 4 + - description: No division + name: Div1 + value: 0 + - description: Division by 2 + name: Div2 + value: 1 + - description: Division by 4 + name: Div4 + value: 2 + - description: Division by 8 + name: Div8 + value: 3 + - description: Division by 16 + name: Div16 + value: 4 enum/MCOSEL: bit_size: 4 variants: - - name: NoClock - description: No clock - value: 0 - - name: SYSCLK - description: SYSCLK clock selected - value: 1 - - name: HSI16 - description: HSI oscillator clock selected - value: 2 - - name: MSI - description: MSI oscillator clock selected - value: 3 - - name: HSE - description: HSE oscillator clock selected - value: 4 - - name: PLL - description: PLL clock selected - value: 5 - - name: LSI - description: LSI oscillator clock selected - value: 6 - - name: LSE - description: LSE oscillator clock selected - value: 7 + - description: No clock + name: NoClock + value: 0 + - description: SYSCLK clock selected + name: SYSCLK + value: 1 + - description: HSI oscillator clock selected + name: HSI16 + value: 2 + - description: MSI oscillator clock selected + name: MSI + value: 3 + - description: HSE oscillator clock selected + name: HSE + value: 4 + - description: PLL clock selected + name: PLL + value: 5 + - description: LSI oscillator clock selected + name: LSI + value: 6 + - description: LSE oscillator clock selected + name: LSE + value: 7 enum/MSIRANGE: bit_size: 3 variants: - - name: Range0 - description: range 0 around 65.536 kHz - value: 0 - - name: Range1 - description: range 1 around 131.072 kHz - value: 1 - - name: Range2 - description: range 2 around 262.144 kHz - value: 2 - - name: Range3 - description: range 3 around 524.288 kHz - value: 3 - - name: Range4 - description: range 4 around 1.048 MHz - value: 4 - - name: Range5 - description: range 5 around 2.097 MHz (reset value) - value: 5 - - name: Range6 - description: range 6 around 4.194 MHz - value: 6 - - name: Range7 - description: not allowed - value: 7 + - description: range 0 around 65.536 kHz + name: Range0 + value: 0 + - description: range 1 around 131.072 kHz + name: Range1 + value: 1 + - description: range 2 around 262.144 kHz + name: Range2 + value: 2 + - description: range 3 around 524.288 kHz + name: Range3 + value: 3 + - description: range 4 around 1.048 MHz + name: Range4 + value: 4 + - description: range 5 around 2.097 MHz (reset value) + name: Range5 + value: 5 + - description: range 6 around 4.194 MHz + name: Range6 + value: 6 + - description: not allowed + name: Range7 + value: 7 +enum/MSIRDYFR: + bit_size: 1 + variants: + - description: No clock ready interrupt + name: NotInterrupted + value: 0 + - description: Clock ready interrupt + name: Interrupted + value: 1 +enum/MSIRDYIE: + bit_size: 1 + variants: + - description: Ready interrupt disabled + name: Disabled + value: 0 + - description: Ready interrupt enabled + name: Enabled + value: 1 enum/PLLDIV: bit_size: 2 variants: - - name: Div2 - description: PLLVCO / 2 - value: 1 - - name: Div3 - description: PLLVCO / 3 - value: 2 - - name: Div4 - description: PLLVCO / 4 - value: 3 + - description: PLLVCO / 2 + name: Div2 + value: 1 + - description: PLLVCO / 3 + name: Div3 + value: 2 + - description: PLLVCO / 4 + name: Div4 + value: 3 enum/PLLMUL: bit_size: 4 variants: - - name: Mul3 - description: PLL clock entry x 3 - value: 0 - - name: Mul4 - description: PLL clock entry x 4 - value: 1 - - name: Mul6 - description: PLL clock entry x 6 - value: 2 - - name: Mul8 - description: PLL clock entry x 8 - value: 3 - - name: Mul12 - description: PLL clock entry x 12 - value: 4 - - name: Mul16 - description: PLL clock entry x 16 - value: 5 - - name: Mul24 - description: PLL clock entry x 24 - value: 6 - - name: Mul32 - description: PLL clock entry x 32 - value: 7 - - name: Mul48 - description: PLL clock entry x 48 - value: 8 + - description: PLL clock entry x 3 + name: Mul3 + value: 0 + - description: PLL clock entry x 4 + name: Mul4 + value: 1 + - description: PLL clock entry x 6 + name: Mul6 + value: 2 + - description: PLL clock entry x 8 + name: Mul8 + value: 3 + - description: PLL clock entry x 12 + name: Mul12 + value: 4 + - description: PLL clock entry x 16 + name: Mul16 + value: 5 + - description: PLL clock entry x 24 + name: Mul24 + value: 6 + - description: PLL clock entry x 32 + name: Mul32 + value: 7 + - description: PLL clock entry x 48 + name: Mul48 + value: 8 enum/PLLON: bit_size: 1 variants: - - name: Disabled - description: Clock disabled - value: 0 - - name: Enabled - description: Clock enabled - value: 1 + - description: Clock disabled + name: Disabled + value: 0 + - description: Clock enabled + name: Enabled + value: 1 enum/PLLRDYR: bit_size: 1 variants: - - name: Unlocked - description: PLL unlocked - value: 0 - - name: Locked - description: PLL locked - value: 1 + - description: PLL unlocked + name: Unlocked + value: 0 + - description: PLL locked + name: Locked + value: 1 enum/PLLSRC: bit_size: 1 variants: - - name: HSI16 - description: HSI selected as PLL input clock - value: 0 - - name: HSE - description: HSE selected as PLL input clock - value: 1 + - description: HSI selected as PLL input clock + name: HSI16 + value: 0 + - description: HSE selected as PLL input clock + name: HSE + value: 1 enum/PPRE: bit_size: 3 variants: - - name: Div1 - description: HCLK not divided - value: 0 - - name: Div2 - description: HCLK divided by 2 - value: 4 - - name: Div4 - description: HCLK divided by 4 - value: 5 - - name: Div8 - description: HCLK divided by 8 - value: 6 - - name: Div16 - description: HCLK divided by 16 - value: 7 + - description: HCLK not divided + name: Div1 + value: 0 + - description: HCLK divided by 2 + name: Div2 + value: 4 + - description: HCLK divided by 4 + name: Div4 + value: 5 + - description: HCLK divided by 8 + name: Div8 + value: 6 + - description: HCLK divided by 16 + name: Div16 + value: 7 enum/RMVFW: bit_size: 1 variants: - - name: Clear - description: Clears the reset flag - value: 1 + - description: Clears the reset flag + name: Clear + value: 1 enum/RTCPRE: bit_size: 2 variants: - - name: Div2 - description: HSE divided by 2 - value: 0 - - name: Div4 - description: HSE divided by 4 - value: 1 - - name: Div8 - description: HSE divided by 8 - value: 2 - - name: Div16 - description: HSE divided by 16 - value: 3 + - description: HSE divided by 2 + name: Div2 + value: 0 + - description: HSE divided by 4 + name: Div4 + value: 1 + - description: HSE divided by 8 + name: Div8 + value: 2 + - description: HSE divided by 16 + name: Div16 + value: 3 enum/RTCRSTW: bit_size: 1 variants: - - name: Reset - description: Resets the RTC peripheral - value: 1 + - description: Resets the RTC peripheral + name: Reset + value: 1 enum/RTCSEL: bit_size: 2 variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: "HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock" - value: 3 + - description: No clock + name: NoClock + value: 0 + - description: LSE oscillator clock used as RTC clock + name: LSE + value: 1 + - description: LSI oscillator clock used as RTC clock + name: LSI + value: 2 + - description: HSE oscillator clock divided by a programmable prescaler (selection + through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used + as the RTC clock + name: HSE + value: 3 enum/STOPWUCK: bit_size: 1 variants: - - name: MSI - description: Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock - value: 0 - - name: HSI16 - description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI16/4 if HSI16DIVEN=1) - value: 1 + - description: Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from + Stop clock + name: MSI + value: 0 + - description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock + (or HSI16/4 if HSI16DIVEN=1) + name: HSI16 + value: 1 enum/SW: bit_size: 2 variants: - - name: MSI - description: MSI oscillator used as system clock - value: 0 - - name: HSI16 - description: HSI oscillator used as system clock - value: 1 - - name: HSE - description: HSE oscillator used as system clock - value: 2 - - name: PLL - description: PLL used as system clock - value: 3 + - description: MSI oscillator used as system clock + name: MSI + value: 0 + - description: HSI oscillator used as system clock + name: HSI16 + value: 1 + - description: HSE oscillator used as system clock + name: HSE + value: 2 + - description: PLL used as system clock + name: PLL + value: 3 enum/SWS: bit_size: 2 variants: - - name: MSI - description: MSI oscillator used as system clock - value: 0 - - name: HSI16 - description: HSI oscillator used as system clock - value: 1 - - name: HSE - description: HSE oscillator used as system clock - value: 2 - - name: PLL - description: PLL used as system clock - value: 3 + - description: MSI oscillator used as system clock + name: MSI + value: 0 + - description: HSI oscillator used as system clock + name: HSI16 + value: 1 + - description: HSE oscillator used as system clock + name: HSE + value: 2 + - description: PLL used as system clock + name: PLL + value: 3 +fieldset/AHBENR: + description: AHB peripheral clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: DMA clock enable bit + name: DMAEN + - bit_offset: 8 + bit_size: 1 + description: NVM interface clock enable bit + name: MIFEN + - bit_offset: 12 + bit_size: 1 + description: CRC clock enable bit + name: CRCEN + - bit_offset: 24 + bit_size: 1 + description: Crypto clock enable bit + name: CRYPEN + - bit_offset: 16 + bit_size: 1 + description: Touch Sensing clock enable bit + name: TOUCHEN + - bit_offset: 20 + bit_size: 1 + description: Random Number Generator clock enable bit + name: RNGEN +fieldset/AHBRSTR: + description: AHB peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: DMA reset + enum_write: CRYPRSTW + name: DMARST + - bit_offset: 8 + bit_size: 1 + description: Memory interface reset + enum_write: CRYPRSTW + name: MIFRST + - bit_offset: 12 + bit_size: 1 + description: Test integration module reset + enum_write: CRYPRSTW + name: CRCRST + - bit_offset: 24 + bit_size: 1 + description: Crypto module reset + enum_write: CRYPRSTW + name: CRYPRST + - bit_offset: 16 + bit_size: 1 + description: Touch Sensing reset + enum_write: CRYPRSTW + name: TOUCHRST + - bit_offset: 20 + bit_size: 1 + description: Random Number Generator module reset + enum_write: CRYPRSTW + name: RNGRST +fieldset/AHBSMENR: + description: AHB peripheral clock enable in sleep mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: DMA clock enable during sleep mode bit + name: DMASMEN + - bit_offset: 8 + bit_size: 1 + description: NVM interface clock enable during sleep mode bit + name: MIFSMEN + - bit_offset: 9 + bit_size: 1 + description: SRAM interface clock enable during sleep mode bit + name: SRAMSMEN + - bit_offset: 12 + bit_size: 1 + description: CRC clock enable during sleep mode bit + name: CRCSMEN + - bit_offset: 24 + bit_size: 1 + description: Crypto clock enable during sleep mode bit + name: CRYPSMEN + - bit_offset: 16 + bit_size: 1 + description: Touch Sensing clock enable during sleep mode bit + name: TOUCHSMEN + - bit_offset: 20 + bit_size: 1 + description: Random Number Generator clock enable during sleep mode bit + name: RNGSMEN +fieldset/APB1ENR: + description: APB1 peripheral clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: Timer2 clock enable bit + name: TIM2EN + - bit_offset: 4 + bit_size: 1 + description: Timer 6 clock enable bit + name: TIM6EN + - bit_offset: 5 + bit_size: 1 + description: Timer 7 clock enable bit + name: TIM7EN + - bit_offset: 11 + bit_size: 1 + description: Window watchdog clock enable bit + name: WWDGEN + - bit_offset: 14 + bit_size: 1 + description: SPI2 clock enable bit + name: SPI2EN + - bit_offset: 17 + bit_size: 1 + description: UART2 clock enable bit + name: USART2EN + - bit_offset: 18 + bit_size: 1 + description: LPUART1 clock enable bit + name: LPUART1EN + - bit_offset: 19 + bit_size: 1 + description: USART4 clock enable bit + name: USART4EN + - bit_offset: 20 + bit_size: 1 + description: USART5 clock enable bit + name: USART5EN + - bit_offset: 21 + bit_size: 1 + description: I2C1 clock enable bit + name: I2C1EN + - bit_offset: 22 + bit_size: 1 + description: I2C2 clock enable bit + name: I2C2EN + - bit_offset: 28 + bit_size: 1 + description: Power interface clock enable bit + name: PWREN + - bit_offset: 30 + bit_size: 1 + description: I2C3 clock enable bit + name: I2C3EN + - bit_offset: 31 + bit_size: 1 + description: Low power timer clock enable bit + name: LPTIM1EN + - bit_offset: 1 + bit_size: 1 + description: Timer 3 clock enbale bit + name: TIM3EN + - bit_offset: 23 + bit_size: 1 + description: USB clock enable bit + name: USBEN + - bit_offset: 27 + bit_size: 1 + description: Clock recovery system clock enable bit + name: CRSEN + - bit_offset: 29 + bit_size: 1 + description: DAC interface clock enable bit + name: DACEN +fieldset/APB1RSTR: + description: APB1 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: Timer 2 reset + enum_write: LPTIMRSTW + name: TIM2RST + - bit_offset: 1 + bit_size: 1 + description: Timer 3 reset + enum_write: LPTIMRSTW + name: TIM3RST + - bit_offset: 4 + bit_size: 1 + description: Timer 6 reset + enum_write: LPTIMRSTW + name: TIM6RST + - bit_offset: 5 + bit_size: 1 + description: Timer 7 reset + enum_write: LPTIMRSTW + name: TIM7RST + - bit_offset: 11 + bit_size: 1 + description: Window watchdog reset + enum_write: LPTIMRSTW + name: WWDGRST + - bit_offset: 14 + bit_size: 1 + description: SPI2 reset + enum_write: LPTIMRSTW + name: SPI2RST + - bit_offset: 17 + bit_size: 1 + description: USART2 reset + enum_write: LPTIMRSTW + name: USART2RST + - bit_offset: 18 + bit_size: 1 + description: LPUART1 reset + enum_write: LPTIMRSTW + name: LPUART1RST + - bit_offset: 19 + bit_size: 1 + description: USART4 reset + enum_write: LPTIMRSTW + name: USART4RST + - bit_offset: 20 + bit_size: 1 + description: USART5 reset + enum_write: LPTIMRSTW + name: USART5RST + - bit_offset: 21 + bit_size: 1 + description: I2C1 reset + enum_write: LPTIMRSTW + name: I2C1RST + - bit_offset: 22 + bit_size: 1 + description: I2C2 reset + enum_write: LPTIMRSTW + name: I2C2RST + - bit_offset: 27 + bit_size: 1 + description: CRC reset + enum_write: LPTIMRSTW + name: CRCRST + - bit_offset: 28 + bit_size: 1 + description: Power interface reset + enum_write: LPTIMRSTW + name: PWRRST + - bit_offset: 30 + bit_size: 1 + description: I2C3 reset + name: I2C3 + - bit_offset: 31 + bit_size: 1 + description: Low power timer reset + enum_write: LPTIMRSTW + name: LPTIM1RST + - bit_offset: 30 + bit_size: 1 + description: I2C3 reset + enum_write: LPTIMRSTW + name: I2C3RST + - bit_offset: 11 + bit_size: 1 + description: Window watchdog reset + enum_write: LPTIMRSTW + name: WWDRST + - bit_offset: 17 + bit_size: 1 + description: UART2 reset + enum_write: LPTIMRSTW + name: LPUART12RST + - bit_offset: 23 + bit_size: 1 + description: USB reset + enum_write: LPTIMRSTW + name: USBRST + - bit_offset: 27 + bit_size: 1 + description: Clock recovery system reset + enum_write: LPTIMRSTW + name: CRSRST + - bit_offset: 29 + bit_size: 1 + description: DAC interface reset + enum_write: LPTIMRSTW + name: DACRST +fieldset/APB1SMENR: + description: APB1 peripheral clock enable in sleep mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: Timer2 clock enable during sleep mode bit + name: TIM2SMEN + - bit_offset: 1 + bit_size: 1 + description: Timer 3 clock enable during sleep mode bit + name: TIM3SMEN + - bit_offset: 4 + bit_size: 1 + description: Timer 6 clock enable during sleep mode bit + name: TIM6SMEN + - bit_offset: 5 + bit_size: 1 + description: Timer 7 clock enable during sleep mode bit + name: TIM7SMEN + - bit_offset: 11 + bit_size: 1 + description: Window watchdog clock enable during sleep mode bit + name: WWDGSMEN + - bit_offset: 14 + bit_size: 1 + description: SPI2 clock enable during sleep mode bit + name: SPI2SMEN + - bit_offset: 17 + bit_size: 1 + description: UART2 clock enable during sleep mode bit + name: USART2SMEN + - bit_offset: 18 + bit_size: 1 + description: LPUART1 clock enable during sleep mode bit + name: LPUART1SMEN + - bit_offset: 19 + bit_size: 1 + description: USART4 clock enabe during sleep mode bit + name: USART4SMEN + - bit_offset: 20 + bit_size: 1 + description: USART5 clock enable during sleep mode bit + name: USART5SMEN + - bit_offset: 21 + bit_size: 1 + description: I2C1 clock enable during sleep mode bit + name: I2C1SMEN + - bit_offset: 22 + bit_size: 1 + description: I2C2 clock enable during sleep mode bit + name: I2C2SMEN + - bit_offset: 27 + bit_size: 1 + description: Clock recovery system clock enable during sleep mode bit + name: CRSSMEN + - bit_offset: 28 + bit_size: 1 + description: Power interface clock enable during sleep mode bit + name: PWRSMEN + - bit_offset: 30 + bit_size: 1 + description: I2C3 clock enable during sleep mode bit + name: I2C3SMEN + - bit_offset: 31 + bit_size: 1 + description: Low power timer clock enable during sleep mode bit + name: LPTIM1SMEN + - bit_offset: 23 + bit_size: 1 + description: USB clock enable during sleep mode bit + name: USBSMEN + - bit_offset: 29 + bit_size: 1 + description: DAC interface clock enable during sleep mode bit + name: DACSMEN +fieldset/APB2ENR: + description: APB2 peripheral clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: System configuration controller clock enable bit + name: SYSCFGEN + - bit_offset: 2 + bit_size: 1 + description: TIM21 timer clock enable bit + name: TIM21EN + - bit_offset: 5 + bit_size: 1 + description: TIM22 timer clock enable bit + name: TIM22EN + - bit_offset: 7 + bit_size: 1 + description: Firewall clock enable bit + name: FWEN + - bit_offset: 9 + bit_size: 1 + description: ADC clock enable bit + name: ADCEN + - bit_offset: 12 + bit_size: 1 + description: SPI1 clock enable bit + name: SPI1EN + - bit_offset: 14 + bit_size: 1 + description: USART1 clock enable bit + name: USART1EN + - bit_offset: 22 + bit_size: 1 + description: DBG clock enable bit + name: DBGEN + - bit_offset: 7 + bit_size: 1 + description: MiFaRe Firewall clock enable bit + name: MIFIEN +fieldset/APB2RSTR: + description: APB2 peripheral reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: System configuration controller reset + enum_write: DBGRSTW + name: SYSCFGRST + - bit_offset: 2 + bit_size: 1 + description: TIM21 timer reset + enum_write: DBGRSTW + name: TIM21RST + - bit_offset: 5 + bit_size: 1 + description: TIM22 timer reset + enum_write: DBGRSTW + name: TIM22RST + - bit_offset: 9 + bit_size: 1 + description: ADC interface reset + enum_write: DBGRSTW + name: ADCRST + - bit_offset: 12 + bit_size: 1 + description: SPI 1 reset + enum_write: DBGRSTW + name: SPI1RST + - bit_offset: 14 + bit_size: 1 + description: USART1 reset + enum_write: DBGRSTW + name: USART1RST + - bit_offset: 22 + bit_size: 1 + description: DBG reset + enum_write: DBGRSTW + name: DBGRST +fieldset/APB2SMENR: + description: APB2 peripheral clock enable in sleep mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: System configuration controller clock enable during sleep mode bit + name: SYSCFGSMEN + - bit_offset: 2 + bit_size: 1 + description: TIM21 timer clock enable during sleep mode bit + name: TIM21SMEN + - bit_offset: 5 + bit_size: 1 + description: TIM22 timer clock enable during sleep mode bit + name: TIM22SMEN + - bit_offset: 9 + bit_size: 1 + description: ADC clock enable during sleep mode bit + name: ADCSMEN + - bit_offset: 12 + bit_size: 1 + description: SPI1 clock enable during sleep mode bit + name: SPI1SMEN + - bit_offset: 14 + bit_size: 1 + description: USART1 clock enable during sleep mode bit + name: USART1SMEN + - bit_offset: 22 + bit_size: 1 + description: DBG clock enable during sleep mode bit + name: DBGSMEN +fieldset/CCIPR: + description: Clock configuration register + fields: + - bit_offset: 0 + bit_size: 2 + description: USART1 clock source selection bits + enum: LPUARTSEL + name: USART1SEL + - bit_offset: 2 + bit_size: 2 + description: USART2 clock source selection bits + enum: LPUARTSEL + name: USART2SEL + - bit_offset: 10 + bit_size: 2 + description: LPUART1 clock source selection bits + enum: LPUARTSEL + name: LPUART1SEL + - bit_offset: 12 + bit_size: 2 + description: I2C1 clock source selection bits + enum: ICSEL + name: I2C1SEL + - bit_offset: 16 + bit_size: 2 + description: I2C3 clock source selection bits + enum: ICSEL + name: I2C3SEL + - bit_offset: 18 + bit_size: 2 + description: Low Power Timer clock source selection bits + enum: LPTIMSEL + name: LPTIM1SEL + - bit_offset: 26 + bit_size: 1 + description: 48 MHz HSI48 clock source selection bit + name: HSI48MSEL +fieldset/CFGR: + description: Clock configuration register + fields: + - bit_offset: 0 + bit_size: 2 + description: System clock switch + enum: SW + name: SW + - bit_offset: 2 + bit_size: 2 + description: System clock switch status + enum: SWS + name: SWS + - bit_offset: 4 + bit_size: 4 + description: AHB prescaler + enum: HPRE + name: HPRE + - array: + len: 2 + stride: 3 + bit_offset: 8 + bit_size: 3 + description: APB low-speed prescaler (APB1) + enum: PPRE + name: PPRE + - bit_offset: 15 + bit_size: 1 + description: Wake-up from stop clock selection + enum: STOPWUCK + name: STOPWUCK + - bit_offset: 16 + bit_size: 1 + description: PLL entry clock source + enum: PLLSRC + name: PLLSRC + - bit_offset: 18 + bit_size: 4 + description: PLL multiplication factor + enum: PLLMUL + name: PLLMUL + - bit_offset: 22 + bit_size: 2 + description: PLL output division + enum: PLLDIV + name: PLLDIV + - bit_offset: 24 + bit_size: 3 + description: Microcontroller clock output selection + enum: MCOSEL + name: MCOSEL + - bit_offset: 28 + bit_size: 3 + description: Microcontroller clock output prescaler + enum: MCOPRE + name: MCOPRE +fieldset/CICR: + description: Clock interrupt clear register + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI ready Interrupt clear + enum_write: CSSHSECW + name: LSIRDYC + - bit_offset: 1 + bit_size: 1 + description: LSE ready Interrupt clear + enum_write: CSSHSECW + name: LSERDYC + - bit_offset: 2 + bit_size: 1 + description: HSI16 ready Interrupt clear + enum_write: CSSHSECW + name: HSI16RDYC + - bit_offset: 3 + bit_size: 1 + description: HSE ready Interrupt clear + enum_write: CSSHSECW + name: HSERDYC + - bit_offset: 4 + bit_size: 1 + description: PLL ready Interrupt clear + enum_write: CSSHSECW + name: PLLRDYC + - bit_offset: 5 + bit_size: 1 + description: MSI ready Interrupt clear + enum_write: CSSHSECW + name: MSIRDYC + - bit_offset: 7 + bit_size: 1 + description: LSE Clock Security System Interrupt clear + enum_write: CSSHSECW + name: CSSLSEC + - bit_offset: 8 + bit_size: 1 + description: Clock Security System Interrupt clear + enum_write: CSSHSECW + name: CSSHSEC + - bit_offset: 6 + bit_size: 1 + description: HSI48 ready Interrupt clear + enum_write: CSSHSECW + name: HSI48RDYC +fieldset/CIER: + description: Clock interrupt enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI ready interrupt flag + enum: MSIRDYIE + name: LSIRDYIE + - bit_offset: 1 + bit_size: 1 + description: LSE ready interrupt flag + enum: MSIRDYIE + name: LSERDYIE + - bit_offset: 2 + bit_size: 1 + description: HSI16 ready interrupt flag + enum: MSIRDYIE + name: HSI16RDYIE + - bit_offset: 3 + bit_size: 1 + description: HSE ready interrupt flag + enum: MSIRDYIE + name: HSERDYIE + - bit_offset: 4 + bit_size: 1 + description: PLL ready interrupt flag + enum: MSIRDYIE + name: PLLRDYIE + - bit_offset: 5 + bit_size: 1 + description: MSI ready interrupt flag + enum: MSIRDYIE + name: MSIRDYIE + - bit_offset: 7 + bit_size: 1 + description: LSE CSS interrupt flag + enum: CSSLSE + name: CSSLSE + - bit_offset: 6 + bit_size: 1 + description: HSI48 ready interrupt flag + enum: HSIRDYIE + name: HSI48RDYIE +fieldset/CIFR: + description: Clock interrupt flag register + fields: + - bit_offset: 0 + bit_size: 1 + description: LSI ready interrupt flag + enum_read: MSIRDYFR + name: LSIRDYF + - bit_offset: 1 + bit_size: 1 + description: LSE ready interrupt flag + enum_read: MSIRDYFR + name: LSERDYF + - bit_offset: 2 + bit_size: 1 + description: HSI16 ready interrupt flag + enum_read: MSIRDYFR + name: HSI16RDYF + - bit_offset: 3 + bit_size: 1 + description: HSE ready interrupt flag + enum_read: MSIRDYFR + name: HSERDYF + - bit_offset: 4 + bit_size: 1 + description: PLL ready interrupt flag + enum_read: MSIRDYFR + name: PLLRDYF + - bit_offset: 5 + bit_size: 1 + description: MSI ready interrupt flag + enum_read: MSIRDYFR + name: MSIRDYF + - bit_offset: 7 + bit_size: 1 + description: LSE Clock Security System Interrupt flag + enum: CSSLSEF + name: CSSLSEF + - bit_offset: 8 + bit_size: 1 + description: Clock Security System Interrupt flag + enum: CSSHSEF + name: CSSHSEF + - bit_offset: 6 + bit_size: 1 + description: HSI48 ready interrupt flag + enum_read: HSI48RDYFR + name: HSI48RDYF +fieldset/CR: + description: Clock control register + fields: + - bit_offset: 0 + bit_size: 1 + description: 16 MHz high-speed internal clock enable + enum: PLLON + name: HSI16ON + - bit_offset: 1 + bit_size: 1 + description: High-speed internal clock enable bit for some IP kernels + enum: PLLON + name: HSI16KERON + - bit_offset: 2 + bit_size: 1 + description: Internal high-speed clock ready flag + enum_read: HSIRDYFR + name: HSI16RDYF + - bit_offset: 3 + bit_size: 1 + description: HSI16DIVEN + name: HSI16DIVEN + - bit_offset: 4 + bit_size: 1 + description: HSI16DIVF + enum_read: HSIDIVFR + name: HSI16DIVF + - bit_offset: 5 + bit_size: 1 + description: 16 MHz high-speed internal clock output enable + name: HSI16OUTEN + - bit_offset: 8 + bit_size: 1 + description: MSI clock enable bit + enum: PLLON + name: MSION + - bit_offset: 9 + bit_size: 1 + description: MSI clock ready flag + enum_read: HSERDYR + name: MSIRDY + - bit_offset: 16 + bit_size: 1 + description: HSE clock enable bit + enum: PLLON + name: HSEON + - bit_offset: 17 + bit_size: 1 + description: HSE clock ready flag + enum_read: HSERDYR + name: HSERDY + - bit_offset: 18 + bit_size: 1 + description: HSE clock bypass bit + enum: HSEBYP + name: HSEBYP + - bit_offset: 19 + bit_size: 1 + description: Clock security system on HSE enable bit + enum: PLLON + name: CSSHSEON + - bit_offset: 20 + bit_size: 2 + description: TC/LCD prescaler + enum: RTCPRE + name: RTCPRE + - bit_offset: 24 + bit_size: 1 + description: PLL enable bit + enum: PLLON + name: PLLON + - bit_offset: 25 + bit_size: 1 + description: PLL clock ready flag + enum_read: PLLRDYR + name: PLLRDY +fieldset/CRRCR: + description: Clock recovery RC register + fields: + - bit_offset: 0 + bit_size: 1 + description: 48MHz HSI clock enable bit + name: HSI48ON + - bit_offset: 1 + bit_size: 1 + description: 48MHz HSI clock ready flag + name: HSI48RDY + - bit_offset: 2 + bit_size: 1 + description: 48 MHz HSI clock divided by 6 output enable + name: HSI48DIV6EN + - bit_offset: 8 + bit_size: 8 + description: 48 MHz HSI clock calibration + name: HSI48CAL +fieldset/CSR: + description: Control and status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Internal low-speed oscillator enable + enum: CSSLSEON + name: LSION + - bit_offset: 1 + bit_size: 1 + description: Internal low-speed oscillator ready bit + enum: LSERDY + name: LSIRDY + - bit_offset: 8 + bit_size: 1 + description: External low-speed oscillator enable bit + enum: CSSLSEON + name: LSEON + - bit_offset: 9 + bit_size: 1 + description: External low-speed oscillator ready bit + enum: LSERDY + name: LSERDY + - bit_offset: 10 + bit_size: 1 + description: External low-speed oscillator bypass bit + enum: LSEBYP + name: LSEBYP + - bit_offset: 11 + bit_size: 2 + description: LSEDRV + enum: LSEDRV + name: LSEDRV + - bit_offset: 13 + bit_size: 1 + description: CSSLSEON + enum: CSSLSEON + name: CSSLSEON + - bit_offset: 14 + bit_size: 1 + description: CSS on LSE failure detection flag + enum: CSSLSED + name: CSSLSED + - bit_offset: 16 + bit_size: 2 + description: RTC and LCD clock source selection bits + enum: RTCSEL + name: RTCSEL + - bit_offset: 18 + bit_size: 1 + description: RTC clock enable bit + name: RTCEN + - bit_offset: 19 + bit_size: 1 + description: RTC software reset bit + enum_write: RTCRSTW + name: RTCRST + - bit_offset: 23 + bit_size: 1 + description: Remove reset flag + enum_write: RMVFW + name: RMVF + - bit_offset: 24 + bit_size: 1 + description: Firewall reset flag + enum_read: LPWRRSTFR + name: FWRSTF + - bit_offset: 25 + bit_size: 1 + description: OBLRSTF + enum_read: LPWRRSTFR + name: OBLRSTF + - bit_offset: 26 + bit_size: 1 + description: PIN reset flag + enum_read: LPWRRSTFR + name: PINRSTF + - bit_offset: 27 + bit_size: 1 + description: POR/PDR reset flag + enum_read: LPWRRSTFR + name: PORRSTF + - bit_offset: 28 + bit_size: 1 + description: Software reset flag + enum_read: LPWRRSTFR + name: SFTRSTF + - bit_offset: 29 + bit_size: 1 + description: Independent watchdog reset flag + enum_read: LPWRRSTFR + name: IWDGRSTF + - bit_offset: 30 + bit_size: 1 + description: Window watchdog reset flag + enum_read: LPWRRSTFR + name: WWDGRSTF + - bit_offset: 31 + bit_size: 1 + description: Low-power reset flag + enum_read: LPWRRSTFR + name: LPWRRSTF + - bit_offset: 24 + bit_size: 1 + description: Remove reset flag + enum_write: RMVFW + name: RMVF +fieldset/ICSCR: + description: Internal clock sources calibration register + fields: + - bit_offset: 0 + bit_size: 8 + description: nternal high speed clock calibration + name: HSI16CAL + - bit_offset: 8 + bit_size: 5 + description: High speed internal clock trimming + name: HSI16TRIM + - bit_offset: 13 + bit_size: 3 + description: MSI clock ranges + enum: MSIRANGE + name: MSIRANGE + - bit_offset: 16 + bit_size: 8 + description: MSI clock calibration + name: MSICAL + - bit_offset: 24 + bit_size: 8 + description: MSI clock trimming + name: MSITRIM +fieldset/IOPENR: + description: GPIO clock enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: IO port A clock enable bit + name: IOPAEN + - bit_offset: 1 + bit_size: 1 + description: IO port B clock enable bit + name: IOPBEN + - bit_offset: 2 + bit_size: 1 + description: IO port A clock enable bit + name: IOPCEN + - bit_offset: 3 + bit_size: 1 + description: I/O port D clock enable bit + name: IOPDEN + - bit_offset: 4 + bit_size: 1 + description: IO port E clock enable bit + name: IOPEEN + - bit_offset: 7 + bit_size: 1 + description: I/O port H clock enable bit + name: IOPHEN +fieldset/IOPRSTR: + description: GPIO reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: I/O port A reset + name: IOPARST + - bit_offset: 1 + bit_size: 1 + description: I/O port B reset + name: IOPBRST + - bit_offset: 2 + bit_size: 1 + description: I/O port A reset + name: IOPCRST + - bit_offset: 3 + bit_size: 1 + description: I/O port D reset + name: IOPDRST + - bit_offset: 4 + bit_size: 1 + description: I/O port E reset + name: IOPERST + - bit_offset: 7 + bit_size: 1 + description: I/O port H reset + name: IOPHRST +fieldset/IOPSMEN: + description: GPIO clock enable in sleep mode register + fields: + - bit_offset: 0 + bit_size: 1 + description: Port A clock enable during Sleep mode bit + name: IOPASMEN + - bit_offset: 1 + bit_size: 1 + description: Port B clock enable during Sleep mode bit + name: IOPBSMEN + - bit_offset: 2 + bit_size: 1 + description: Port C clock enable during Sleep mode bit + name: IOPCSMEN + - bit_offset: 3 + bit_size: 1 + description: Port D clock enable during Sleep mode bit + name: IOPDSMEN + - bit_offset: 4 + bit_size: 1 + description: Port E clock enable during Sleep mode bit + name: IOPESMEN + - bit_offset: 7 + bit_size: 1 + description: Port H clock enable during Sleep mode bit + name: IOPHSMEN diff --git a/merge_regs.py b/merge_regs.py index fc9381a..bdb2f59 100644 --- a/merge_regs.py +++ b/merge_regs.py @@ -13,43 +13,38 @@ def item_key(a): def field_key(a): return int(a["bit_offset"]) -def block_items(origin, new): - newarr=[] - sorted(origin, key=item_key) - sorted(new, key=item_key) +def merge_block(origin, new): + for newval in new: + found = False + for val in origin: + if val["name"] == newval["name"] and val["byte_offset"] == newval["byte_offset"]: + found = True + if not found: + origin.append(newval) - for val in origin: - for newval in new: - if val["name"] == newval["name"] and val["byte_offset"] == newval["byte_offset"] and val["fieldset"] == newval["fieldset"]: - newarr.append(newval) - - return newarr - -def reg_fields(origin, new): - newarr=[] - sorted(origin, key=field_key) - sorted(new, key=field_key) - for val in origin: - for newval in new: +def merge_fields(origin, new): + for newval in new: + found = False + for val in origin: if val["name"] == newval["name"] and val["bit_offset"] == newval["bit_offset"]: - newarr.append(newval) - return newarr + found = True + if not found: + origin.append(newval) def merge_dicts(origin, new): - merged={} - for k, v in origin.items(): - if k in new: + for k, v in new.items(): + if k in origin: if type(v) is dict: - merged[k] = merge_dicts(v, new[k]) + merge_dicts(origin[k], v) elif type(v) is list: if k == "items": - merged[k] = block_items(v, new[k]) + merge_block(origin[k], v) if k == "fields": - merged[k] = reg_fields(v, new[k]) + merge_fields(origin[k], v) else: - merged[k] = v - return merged - + origin[k] = v + else: + origin[k] = v first=True reg_map={} @@ -57,10 +52,7 @@ for regfile in sys.argv[1:]: print("Loading", regfile) with open(regfile, 'r') as f: y = yaml.load(f, Loader=yaml.SafeLoader) - if not reg_map: - reg_map = y - else: - reg_map = merge_dicts(reg_map, y) + merge_dicts(reg_map, y) with open('regs_merged.yaml', 'w') as f: