Add fmc register files

data/registers/fmc_v1x3.yaml

@@ -0,0 +1,801 @@
+# stm32f429
+---
+block/FMC:
+  description: Flexible memory controller
+  items:
+    - name: BCR1
+      description: SRAM/NOR-Flash chip-select control register 1
+      byte_offset: 0
+      fieldset: BCR1
+    - name: BCR
+      description: SRAM/NOR-Flash chip-select control register 2-4
+      array:
+        len: 3
+        stride: 8
+      byte_offset: 8
+      fieldset: BCR
+    - name: BTR
+      description: SRAM/NOR-Flash chip-select timing register 1-4
+      array:
+        len: 4
+        stride: 8
+      byte_offset: 4
+      fieldset: BTR
+    - name: BWTR
+      description: SRAM/NOR-Flash write timing registers 1-4
+      array:
+        len: 4
+        stride: 8
+      byte_offset: 260
+      fieldset: BWTR
+    - name: PCR
+      description: PC Card/NAND Flash control register 2-4
+      array:
+        len: 3
+        stride: 32
+      byte_offset: 96
+      fieldset: PCR
+    - name: SR
+      description: FIFO status and interrupt register 2-4
+      array:
+        len: 3
+        stride: 32
+      byte_offset: 100
+      fieldset: SR
+    - name: PMEM
+      description: Common memory space timing register 2-4
+      array:
+        len: 3
+        stride: 32
+      byte_offset: 104
+      fieldset: PMEM
+    - name: PATT
+      description: Attribute memory space timing register 2-4
+      array:
+        len: 3
+        stride: 32
+      byte_offset: 108
+      fieldset: PATT
+    - name: PIO4
+      description: I/O space timing register 4
+      byte_offset: 176
+      fieldset: PIO4
+    - name: ECCR
+      description: ECC result register 2-3
+      array:
+        len: 2
+        stride: 32
+      byte_offset: 116
+      access: Read
+      fieldset: ECCR
+    - name: SDCR
+      description: SDRAM Control Register 1-2
+      array:
+        len: 2
+        stride: 4
+      byte_offset: 320
+      fieldset: SDCR
+    - name: SDTR
+      description: SDRAM Timing register 1-2
+      array:
+        len: 2
+        stride: 4
+      byte_offset: 328
+      fieldset: SDTR
+    - name: SDCMR
+      description: SDRAM Command Mode register
+      byte_offset: 336
+      fieldset: SDCMR
+    - name: SDRTR
+      description: SDRAM Refresh Timer register
+      byte_offset: 340
+      fieldset: SDRTR
+    - name: SDSR
+      description: SDRAM Status register
+      byte_offset: 344
+      access: Read
+      fieldset: SDSR
+fieldset/BCR1:
+  description: SRAM/NOR-Flash chip-select control register 1
+  fields:
+    - name: MBKEN
+      description: Memory bank enable bit
+      bit_offset: 0
+      bit_size: 1
+    - name: MUXEN
+      description: Address/data multiplexing enable bit
+      bit_offset: 1
+      bit_size: 1
+    - name: MTYP
+      description: Memory type
+      bit_offset: 2
+      bit_size: 2
+      enum: MTYP
+    - name: MWID
+      description: Memory data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: MWID
+    - name: FACCEN
+      description: Flash access enable
+      bit_offset: 6
+      bit_size: 1
+    - name: BURSTEN
+      description: Burst enable bit
+      bit_offset: 8
+      bit_size: 1
+    - name: WAITPOL
+      description: Wait signal polarity bit
+      bit_offset: 9
+      bit_size: 1
+      enum: WAITPOL
+    - name: WRAPMOD
+      description: WRAPMOD
+      bit_offset: 10
+      bit_size: 1
+    - name: WAITCFG
+      description: Wait timing configuration
+      bit_offset: 11
+      bit_size: 1
+      enum: WAITCFG
+    - name: WREN
+      description: Write enable bit
+      bit_offset: 12
+      bit_size: 1
+    - name: WAITEN
+      description: Wait enable bit
+      bit_offset: 13
+      bit_size: 1
+    - name: EXTMOD
+      description: Extended mode enable
+      bit_offset: 14
+      bit_size: 1
+    - name: ASYNCWAIT
+      description: Wait signal during asynchronous transfers
+      bit_offset: 15
+      bit_size: 1
+    - name: CPSIZE
+      description: CRAM page size
+      bit_offset: 16
+      bit_size: 3
+      enum: CPSIZE
+    - name: CBURSTRW
+      description: Write burst enable
+      bit_offset: 19
+      bit_size: 1
+    - name: CCLKEN
+      description: Continuous clock enable
+      bit_offset: 20
+      bit_size: 1
+fieldset/BCR:
+  description: SRAM/NOR-Flash chip-select control register 2-4
+  fields:
+    - name: MBKEN
+      description: Memory bank enable bit
+      bit_offset: 0
+      bit_size: 1
+    - name: MUXEN
+      description: Address/data multiplexing enable bit
+      bit_offset: 1
+      bit_size: 1
+    - name: MTYP
+      description: Memory type
+      bit_offset: 2
+      bit_size: 2
+      enum: MTYP
+    - name: MWID
+      description: Memory data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: MWID
+    - name: FACCEN
+      description: Flash access enable
+      bit_offset: 6
+      bit_size: 1
+    - name: BURSTEN
+      description: Burst enable bit
+      bit_offset: 8
+      bit_size: 1
+    - name: WAITPOL
+      description: Wait signal polarity bit
+      bit_offset: 9
+      bit_size: 1
+      enum: WAITPOL
+    - name: WRAPMOD
+      description: WRAPMOD
+      bit_offset: 10
+      bit_size: 1
+    - name: WAITCFG
+      description: Wait timing configuration
+      bit_offset: 11
+      bit_size: 1
+      enum: WAITCFG
+    - name: WREN
+      description: Write enable bit
+      bit_offset: 12
+      bit_size: 1
+    - name: WAITEN
+      description: Wait enable bit
+      bit_offset: 13
+      bit_size: 1
+    - name: EXTMOD
+      description: Extended mode enable
+      bit_offset: 14
+      bit_size: 1
+    - name: ASYNCWAIT
+      description: Wait signal during asynchronous transfers
+      bit_offset: 15
+      bit_size: 1
+    - name: CPSIZE
+      description: CRAM page size
+      bit_offset: 16
+      bit_size: 3
+      enum: CPSIZE
+    - name: CBURSTRW
+      description: Write burst enable
+      bit_offset: 19
+      bit_size: 1
+fieldset/BTR:
+  description: SRAM/NOR-Flash chip-select timing register
+  fields:
+    - name: ADDSET
+      description: Address setup phase duration
+      bit_offset: 0
+      bit_size: 4
+    - name: ADDHLD
+      description: Address-hold phase duration
+      bit_offset: 4
+      bit_size: 4
+    - name: DATAST
+      description: Data-phase duration
+      bit_offset: 8
+      bit_size: 8
+    - name: BUSTURN
+      description: Bus turnaround phase duration
+      bit_offset: 16
+      bit_size: 4
+    - name: CLKDIV
+      description: Clock divide ratio (for FMC_CLK signal)
+      bit_offset: 20
+      bit_size: 4
+    - name: DATLAT
+      description: Data latency for synchronous memory
+      bit_offset: 24
+      bit_size: 4
+    - name: ACCMOD
+      description: Access mode
+      bit_offset: 28
+      bit_size: 2
+      enum: ACCMOD
+fieldset/BWTR:
+  description: SRAM/NOR-Flash write timing registers
+  fields:
+    - name: ADDSET
+      description: Address setup phase duration
+      bit_offset: 0
+      bit_size: 4
+    - name: ADDHLD
+      description: Address-hold phase duration
+      bit_offset: 4
+      bit_size: 4
+    - name: DATAST
+      description: Data-phase duration
+      bit_offset: 8
+      bit_size: 8
+    - name: BUSTURN
+      description: Bus turnaround phase duration
+      bit_offset: 16
+      bit_size: 4
+    - name: ACCMOD
+      description: Access mode
+      bit_offset: 28
+      bit_size: 2
+      enum: ACCMOD
+fieldset/PCR:
+  description: PC Card/NAND Flash control register
+  fields:
+    - name: PWAITEN
+      description: Wait feature enable bit
+      bit_offset: 1
+      bit_size: 1
+    - name: PBKEN
+      description: NAND Flash memory bank enable bit
+      bit_offset: 2
+      bit_size: 1
+    - name: PTYP
+      description: Memory type
+      bit_offset: 3
+      bit_size: 1
+      enum: PTYP
+    - name: PWID
+      description: Data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: PWID
+    - name: ECCEN
+      description: ECC computation logic enable bit
+      bit_offset: 6
+      bit_size: 1
+    - name: TCLR
+      description: CLE to RE delay
+      bit_offset: 9
+      bit_size: 4
+    - name: TAR
+      description: ALE to RE delay
+      bit_offset: 13
+      bit_size: 4
+    - name: ECCPS
+      description: ECC page size
+      bit_offset: 17
+      bit_size: 3
+      enum: ECCPS
+fieldset/SR:
+  description: FIFO status and interrupt register
+  fields:
+    - name: IRS
+      description: Interrupt rising edge status
+      bit_offset: 0
+      bit_size: 1
+    - name: ILS
+      description: Interrupt high-level status
+      bit_offset: 1
+      bit_size: 1
+    - name: IFS
+      description: Interrupt falling edge status
+      bit_offset: 2
+      bit_size: 1
+    - name: IREN
+      description: Interrupt rising edge detection enable bit
+      bit_offset: 3
+      bit_size: 1
+    - name: ILEN
+      description: Interrupt high-level detection enable bit
+      bit_offset: 4
+      bit_size: 1
+    - name: IFEN
+      description: Interrupt falling edge detection enable bit
+      bit_offset: 5
+      bit_size: 1
+    - name: FEMPT
+      description: FIFO empty status
+      bit_offset: 6
+      bit_size: 1
+fieldset/PMEM:
+  description: Common memory space timing register
+  fields:
+    - name: MEMSET
+      description: Common memory x setup time
+      bit_offset: 0
+      bit_size: 8
+    - name: MEMWAIT
+      description: Common memory wait time
+      bit_offset: 8
+      bit_size: 8
+    - name: MEMHOLD
+      description: Common memory hold time
+      bit_offset: 16
+      bit_size: 8
+    - name: MEMHIZ
+      description: Common memory x data bus Hi-Z time
+      bit_offset: 24
+      bit_size: 8
+fieldset/PATT:
+  description: Attribute memory space timing register
+  fields:
+    - name: ATTSET
+      description: Attribute memory setup time
+      bit_offset: 0
+      bit_size: 8
+    - name: ATTWAIT
+      description: Attribute memory wait time
+      bit_offset: 8
+      bit_size: 8
+    - name: ATTHOLD
+      description: Attribute memory hold time
+      bit_offset: 16
+      bit_size: 8
+    - name: ATTHIZ
+      description: Attribute memory data bus Hi-Z time
+      bit_offset: 24
+      bit_size: 8
+fieldset/PIO4:
+  description: I/O space timing register 4
+  fields:
+    - name: IOSETx
+      description: IOSETx
+      bit_offset: 0
+      bit_size: 8
+    - name: IOWAITx
+      description: IOWAITx
+      bit_offset: 8
+      bit_size: 8
+    - name: IOHOLDx
+      description: IOHOLDx
+      bit_offset: 16
+      bit_size: 8
+    - name: IOHIZx
+      description: IOHIZx
+      bit_offset: 24
+      bit_size: 8
+fieldset/ECCR:
+  description: ECC result register
+  fields:
+    - name: ECC
+      description: ECC computation result value
+      bit_offset: 0
+      bit_size: 32
+fieldset/SDCR:
+  description: SDRAM Control Register
+  fields:
+    - name: NC
+      description: Number of column address bits
+      bit_offset: 0
+      bit_size: 2
+      enum: NC
+    - name: NR
+      description: Number of row address bits
+      bit_offset: 2
+      bit_size: 2
+      enum: NR
+    - name: MWID
+      description: Memory data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: SDCR_MWID
+    - name: NB
+      description: Number of internal banks
+      bit_offset: 6
+      bit_size: 1
+      enum: NB
+    - name: CAS
+      description: CAS latency
+      bit_offset: 7
+      bit_size: 2
+      enum: CAS
+    - name: WP
+      description: Write protection
+      bit_offset: 9
+      bit_size: 1
+    - name: SDCLK
+      description: SDRAM clock configuration
+      bit_offset: 10
+      bit_size: 2
+      enum: SDCLK
+    - name: RBURST
+      description: Burst read
+      bit_offset: 12
+      bit_size: 1
+    - name: RPIPE
+      description: Read pipe
+      bit_offset: 13
+      bit_size: 2
+      enum: RPIPE
+fieldset/SDTR:
+  description: SDRAM Timing register
+  fields:
+    - name: TMRD
+      description: Load Mode Register to Active
+      bit_offset: 0
+      bit_size: 4
+    - name: TXSR
+      description: Exit self-refresh delay
+      bit_offset: 4
+      bit_size: 4
+    - name: TRAS
+      description: Self refresh time
+      bit_offset: 8
+      bit_size: 4
+    - name: TRC
+      description: Row cycle delay
+      bit_offset: 12
+      bit_size: 4
+    - name: TWR
+      description: Recovery delay
+      bit_offset: 16
+      bit_size: 4
+    - name: TRP
+      description: Row precharge delay
+      bit_offset: 20
+      bit_size: 4
+    - name: TRCD
+      description: Row to column delay
+      bit_offset: 24
+      bit_size: 4
+fieldset/SDCMR:
+  description: SDRAM Command Mode register
+  fields:
+    - name: MODE
+      description: Command mode
+      bit_offset: 0
+      bit_size: 3
+      enum_write: MODE
+    - name: CTB2
+      description: Command target bank 2
+      bit_offset: 3
+      bit_size: 1
+    - name: CTB1
+      description: Command target bank 1
+      bit_offset: 4
+      bit_size: 1
+    - name: NRFS
+      description: Number of Auto-refresh
+      bit_offset: 5
+      bit_size: 4
+    - name: MRD
+      description: Mode Register definition
+      bit_offset: 9
+      bit_size: 13
+fieldset/SDRTR:
+  description: SDRAM Refresh Timer register
+  fields:
+    - name: CRE
+      description: Clear Refresh error flag
+      bit_offset: 0
+      bit_size: 1
+      enum_write: CRE
+    - name: COUNT
+      description: Refresh Timer Count
+      bit_offset: 1
+      bit_size: 13
+    - name: REIE
+      description: RES Interrupt Enable
+      bit_offset: 14
+      bit_size: 1
+fieldset/SDSR:
+  description: SDRAM Status register
+  fields:
+    - name: RE
+      description: Refresh error flag
+      bit_offset: 0
+      bit_size: 1
+    - name: MODES1
+      description: Status Mode for Bank 1
+      bit_offset: 1
+      bit_size: 2
+      enum_read: MODES1
+    - name: MODES2
+      description: Status Mode for Bank 2
+      bit_offset: 3
+      bit_size: 2
+      enum_read: MODES1
+    - name: BUSY
+      description: Busy status
+      bit_offset: 5
+      bit_size: 1
+enum/ACCMOD:
+  bit_size: 2
+  variants:
+    - name: A
+      description: Access mode A
+      value: 0
+    - name: B
+      description: Access mode B
+      value: 1
+    - name: C
+      description: Access mode C
+      value: 2
+    - name: D
+      description: Access mode D
+      value: 3
+enum/CAS:
+  bit_size: 2
+  variants:
+    - name: Clocks1
+      description: 1 cycle
+      value: 1
+    - name: Clocks2
+      description: 2 cycles
+      value: 2
+    - name: Clocks3
+      description: 3 cycles
+      value: 3
+enum/CPSIZE:
+  bit_size: 3
+  variants:
+    - name: NoBurstSplit
+      description: No burst split when crossing page boundary
+      value: 0
+    - name: Bytes128
+      description: 128 bytes CRAM page size
+      value: 1
+    - name: Bytes256
+      description: 256 bytes CRAM page size
+      value: 2
+    - name: Bytes512
+      description: 512 bytes CRAM page size
+      value: 3
+    - name: Bytes1024
+      description: 1024 bytes CRAM page size
+      value: 4
+enum/CRE:
+  bit_size: 1
+  variants:
+    - name: Clear
+      description: Refresh Error Flag is cleared
+      value: 1
+enum/ECCPS:
+  bit_size: 3
+  variants:
+    - name: Bytes256
+      description: ECC page size 256 bytes
+      value: 0
+    - name: Bytes512
+      description: ECC page size 512 bytes
+      value: 1
+    - name: Bytes1024
+      description: ECC page size 1024 bytes
+      value: 2
+    - name: Bytes2048
+      description: ECC page size 2048 bytes
+      value: 3
+    - name: Bytes4096
+      description: ECC page size 4096 bytes
+      value: 4
+    - name: Bytes8192
+      description: ECC page size 8192 bytes
+      value: 5
+enum/MODE:
+  bit_size: 3
+  variants:
+    - name: Normal
+      description: Normal Mode
+      value: 0
+    - name: ClockConfigurationEnable
+      description: Clock Configuration Enable
+      value: 1
+    - name: PALL
+      description: PALL (All Bank Precharge) command
+      value: 2
+    - name: AutoRefreshCommand
+      description: Auto-refresh command
+      value: 3
+    - name: LoadModeRegister
+      description: Load Mode Resgier
+      value: 4
+    - name: SelfRefreshCommand
+      description: Self-refresh command
+      value: 5
+    - name: PowerDownCommand
+      description: Power-down command
+      value: 6
+enum/MODES1:
+  bit_size: 2
+  variants:
+    - name: Normal
+      description: Normal Mode
+      value: 0
+    - name: SelfRefresh
+      description: Self-refresh mode
+      value: 1
+    - name: PowerDown
+      description: Power-down mode
+      value: 2
+enum/MTYP:
+  bit_size: 2
+  variants:
+    - name: SRAM
+      description: SRAM memory type
+      value: 0
+    - name: PSRAM
+      description: PSRAM (CRAM) memory type
+      value: 1
+    - name: Flash
+      description: NOR Flash/OneNAND Flash
+      value: 2
+enum/MWID:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: Memory data bus width 8 bits
+      value: 0
+    - name: Bits16
+      description: Memory data bus width 16 bits
+      value: 1
+    - name: Bits32
+      description: Memory data bus width 32 bits
+      value: 2
+enum/NB:
+  bit_size: 1
+  variants:
+    - name: NB2
+      description: Two internal Banks
+      value: 0
+    - name: NB4
+      description: Four internal Banks
+      value: 1
+enum/NC:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: 8 bits
+      value: 0
+    - name: Bits9
+      description: 9 bits
+      value: 1
+    - name: Bits10
+      description: 10 bits
+      value: 2
+    - name: Bits11
+      description: 11 bits
+      value: 3
+enum/NR:
+  bit_size: 2
+  variants:
+    - name: Bits11
+      description: 11 bits
+      value: 0
+    - name: Bits12
+      description: 12 bits
+      value: 1
+    - name: Bits13
+      description: 13 bits
+      value: 2
+enum/PTYP:
+  bit_size: 1
+  variants:
+    - name: NANDFlash
+      description: NAND Flash
+      value: 1
+enum/PWID:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: External memory device width 8 bits
+      value: 0
+    - name: Bits16
+      description: External memory device width 16 bits
+      value: 1
+enum/RPIPE:
+  bit_size: 2
+  variants:
+    - name: NoDelay
+      description: No clock cycle delay
+      value: 0
+    - name: Clocks1
+      description: One clock cycle delay
+      value: 1
+    - name: Clocks2
+      description: Two clock cycles delay
+      value: 2
+enum/SDCLK:
+  bit_size: 2
+  variants:
+    - name: Disabled
+      description: SDCLK clock disabled
+      value: 0
+    - name: Div2
+      description: SDCLK period = 2 x HCLK period
+      value: 2
+    - name: Div3
+      description: SDCLK period = 3 x HCLK period
+      value: 3
+enum/SDCR_MWID:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: Memory data bus width 8 bits
+      value: 0
+    - name: Bits16
+      description: Memory data bus width 16 bits
+      value: 1
+    - name: Bits32
+      description: Memory data bus width 32 bits
+      value: 2
+enum/WAITCFG:
+  bit_size: 1
+  variants:
+    - name: BeforeWaitState
+      description: NWAIT signal is active one data cycle before wait state
+      value: 0
+    - name: DuringWaitState
+      description: NWAIT signal is active during wait state
+      value: 1
+enum/WAITPOL:
+  bit_size: 1
+  variants:
+    - name: ActiveLow
+      description: NWAIT active low
+      value: 0
+    - name: ActiveHigh
+      description: NWAIT active high
+      value: 1

data/registers/fmc_v2x1.yaml

@@ -0,0 +1,760 @@
+# stm32f446
+# stm32f469
+---
+block/FMC:
+  description: Flexible memory controller
+  items:
+    - name: BCR1
+      description: SRAM/NOR-Flash chip-select control register 1
+      byte_offset: 0
+      fieldset: BCR1
+    - name: BCR
+      description: SRAM/NOR-Flash chip-select control register 2-4
+      array:
+        len: 3
+        stride: 8
+      byte_offset: 8
+      fieldset: BCR
+    - name: BTR
+      description: SRAM/NOR-Flash chip-select timing register 1-4
+      array:
+        len: 4
+        stride: 8
+      byte_offset: 4
+      fieldset: BTR
+    - name: BWTR
+      description: SRAM/NOR-Flash write timing registers 1-4
+      array:
+        len: 4
+        stride: 8
+      byte_offset: 260
+      fieldset: BWTR
+    - name: PCR
+      description: PC Card/NAND Flash control register
+      byte_offset: 128
+      fieldset: PCR
+    - name: SR
+      description: FIFO status and interrupt register
+      byte_offset: 132
+      fieldset: SR
+    - name: PMEM
+      description: Common memory space timing register
+      byte_offset: 136
+      fieldset: PMEM
+    - name: PATT
+      description: Attribute memory space timing register
+      byte_offset: 140
+      fieldset: PATT
+    - name: ECCR
+      description: ECC result register
+      byte_offset: 148
+      access: Read
+      fieldset: ECCR
+    - name: SDCR
+      description: SDRAM Control Register 1-2
+      array:
+        len: 2
+        stride: 4
+      byte_offset: 320
+      fieldset: SDCR
+    - name: SDTR
+      description: SDRAM Timing register 1-2
+      array:
+        len: 2
+        stride: 4
+      byte_offset: 328
+      fieldset: SDTR
+    - name: SDCMR
+      description: SDRAM Command Mode register
+      byte_offset: 336
+      fieldset: SDCMR
+    - name: SDRTR
+      description: SDRAM Refresh Timer register
+      byte_offset: 340
+      fieldset: SDRTR
+    - name: SDSR
+      description: SDRAM Status register
+      byte_offset: 344
+      access: Read
+      fieldset: SDSR
+fieldset/BCR1:
+  description: SRAM/NOR-Flash chip-select control register 1
+  fields:
+    - name: MBKEN
+      description: Memory bank enable bit
+      bit_offset: 0
+      bit_size: 1
+    - name: MUXEN
+      description: Address/data multiplexing enable bit
+      bit_offset: 1
+      bit_size: 1
+    - name: MTYP
+      description: Memory type
+      bit_offset: 2
+      bit_size: 2
+      enum: MTYP
+    - name: MWID
+      description: Memory data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: MWID
+    - name: FACCEN
+      description: Flash access enable
+      bit_offset: 6
+      bit_size: 1
+    - name: BURSTEN
+      description: Burst enable bit
+      bit_offset: 8
+      bit_size: 1
+    - name: WAITPOL
+      description: Wait signal polarity bit
+      bit_offset: 9
+      bit_size: 1
+      enum: WAITPOL
+    - name: WAITCFG
+      description: Wait timing configuration
+      bit_offset: 11
+      bit_size: 1
+      enum: WAITCFG
+    - name: WREN
+      description: Write enable bit
+      bit_offset: 12
+      bit_size: 1
+    - name: WAITEN
+      description: Wait enable bit
+      bit_offset: 13
+      bit_size: 1
+    - name: EXTMOD
+      description: Extended mode enable
+      bit_offset: 14
+      bit_size: 1
+    - name: ASYNCWAIT
+      description: Wait signal during asynchronous transfers
+      bit_offset: 15
+      bit_size: 1
+    - name: CPSIZE
+      description: CRAM page size
+      bit_offset: 16
+      bit_size: 3
+      enum: CPSIZE
+    - name: CBURSTRW
+      description: Write burst enable
+      bit_offset: 19
+      bit_size: 1
+    - name: CCLKEN
+      description: Continuous clock enable
+      bit_offset: 20
+      bit_size: 1
+    - name: WFDIS
+      description: Write FIFO disable
+      bit_offset: 21
+      bit_size: 1
+fieldset/BCR:
+  description: SRAM/NOR-Flash chip-select control register 2-4
+  fields:
+    - name: MBKEN
+      description: Memory bank enable bit
+      bit_offset: 0
+      bit_size: 1
+    - name: MUXEN
+      description: Address/data multiplexing enable bit
+      bit_offset: 1
+      bit_size: 1
+    - name: MTYP
+      description: Memory type
+      bit_offset: 2
+      bit_size: 2
+      enum: MTYP
+    - name: MWID
+      description: Memory data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: MWID
+    - name: FACCEN
+      description: Flash access enable
+      bit_offset: 6
+      bit_size: 1
+    - name: BURSTEN
+      description: Burst enable bit
+      bit_offset: 8
+      bit_size: 1
+    - name: WAITPOL
+      description: Wait signal polarity bit
+      bit_offset: 9
+      bit_size: 1
+      enum: WAITPOL
+    - name: WAITCFG
+      description: Wait timing configuration
+      bit_offset: 11
+      bit_size: 1
+      enum: WAITCFG
+    - name: WREN
+      description: Write enable bit
+      bit_offset: 12
+      bit_size: 1
+    - name: WAITEN
+      description: Wait enable bit
+      bit_offset: 13
+      bit_size: 1
+    - name: EXTMOD
+      description: Extended mode enable
+      bit_offset: 14
+      bit_size: 1
+    - name: ASYNCWAIT
+      description: Wait signal during asynchronous transfers
+      bit_offset: 15
+      bit_size: 1
+    - name: CPSIZE
+      description: CRAM page size
+      bit_offset: 16
+      bit_size: 3
+      enum: CPSIZE
+    - name: CBURSTRW
+      description: Write burst enable
+      bit_offset: 19
+      bit_size: 1
+fieldset/BTR:
+  description: SRAM/NOR-Flash chip-select timing register
+  fields:
+    - name: ADDSET
+      description: Address setup phase duration
+      bit_offset: 0
+      bit_size: 4
+    - name: ADDHLD
+      description: Address-hold phase duration
+      bit_offset: 4
+      bit_size: 4
+    - name: DATAST
+      description: Data-phase duration
+      bit_offset: 8
+      bit_size: 8
+    - name: BUSTURN
+      description: Bus turnaround phase duration
+      bit_offset: 16
+      bit_size: 4
+    - name: CLKDIV
+      description: Clock divide ratio (for FMC_CLK signal)
+      bit_offset: 20
+      bit_size: 4
+    - name: DATLAT
+      description: Data latency for synchronous memory
+      bit_offset: 24
+      bit_size: 4
+    - name: ACCMOD
+      description: Access mode
+      bit_offset: 28
+      bit_size: 2
+      enum: ACCMOD
+fieldset/BWTR:
+  description: SRAM/NOR-Flash write timing registers
+  fields:
+    - name: ADDSET
+      description: Address setup phase duration
+      bit_offset: 0
+      bit_size: 4
+    - name: ADDHLD
+      description: Address-hold phase duration
+      bit_offset: 4
+      bit_size: 4
+    - name: DATAST
+      description: Data-phase duration
+      bit_offset: 8
+      bit_size: 8
+    - name: BUSTURN
+      description: Bus turnaround phase duration
+      bit_offset: 16
+      bit_size: 4
+    - name: ACCMOD
+      description: Access mode
+      bit_offset: 28
+      bit_size: 2
+      enum: ACCMOD
+fieldset/PCR:
+  description: PC Card/NAND Flash control register
+  fields:
+    - name: PWAITEN
+      description: Wait feature enable bit
+      bit_offset: 1
+      bit_size: 1
+    - name: PBKEN
+      description: NAND Flash memory bank enable bit
+      bit_offset: 2
+      bit_size: 1
+    - name: PTYP
+      description: Memory type
+      bit_offset: 3
+      bit_size: 1
+      enum: PTYP
+    - name: PWID
+      description: Data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: PWID
+    - name: ECCEN
+      description: ECC computation logic enable bit
+      bit_offset: 6
+      bit_size: 1
+    - name: TCLR
+      description: CLE to RE delay
+      bit_offset: 9
+      bit_size: 4
+    - name: TAR
+      description: ALE to RE delay
+      bit_offset: 13
+      bit_size: 4
+    - name: ECCPS
+      description: ECC page size
+      bit_offset: 17
+      bit_size: 3
+      enum: ECCPS
+fieldset/SR:
+  description: FIFO status and interrupt register
+  fields:
+    - name: IRS
+      description: Interrupt rising edge status
+      bit_offset: 0
+      bit_size: 1
+    - name: ILS
+      description: Interrupt high-level status
+      bit_offset: 1
+      bit_size: 1
+    - name: IFS
+      description: Interrupt falling edge status
+      bit_offset: 2
+      bit_size: 1
+    - name: IREN
+      description: Interrupt rising edge detection enable bit
+      bit_offset: 3
+      bit_size: 1
+    - name: ILEN
+      description: Interrupt high-level detection enable bit
+      bit_offset: 4
+      bit_size: 1
+    - name: IFEN
+      description: Interrupt falling edge detection enable bit
+      bit_offset: 5
+      bit_size: 1
+    - name: FEMPT
+      description: FIFO empty status
+      bit_offset: 6
+      bit_size: 1
+fieldset/PMEM:
+  description: Common memory space timing register
+  fields:
+    - name: MEMSET
+      description: Common memory x setup time
+      bit_offset: 0
+      bit_size: 8
+    - name: MEMWAIT
+      description: Common memory wait time
+      bit_offset: 8
+      bit_size: 8
+    - name: MEMHOLD
+      description: Common memory hold time
+      bit_offset: 16
+      bit_size: 8
+    - name: MEMHIZ
+      description: Common memory x data bus Hi-Z time
+      bit_offset: 24
+      bit_size: 8
+fieldset/PATT:
+  description: Attribute memory space timing register
+  fields:
+    - name: ATTSET
+      description: Attribute memory setup time
+      bit_offset: 0
+      bit_size: 8
+    - name: ATTWAIT
+      description: Attribute memory wait time
+      bit_offset: 8
+      bit_size: 8
+    - name: ATTHOLD
+      description: Attribute memory hold time
+      bit_offset: 16
+      bit_size: 8
+    - name: ATTHIZ
+      description: Attribute memory data bus Hi-Z time
+      bit_offset: 24
+      bit_size: 8
+fieldset/ECCR:
+  description: ECC result register
+  fields:
+    - name: ECC
+      description: ECC computation result value
+      bit_offset: 0
+      bit_size: 32
+fieldset/SDCR:
+  description: SDRAM Control Register
+  fields:
+    - name: NC
+      description: Number of column address bits
+      bit_offset: 0
+      bit_size: 2
+      enum: NC
+    - name: NR
+      description: Number of row address bits
+      bit_offset: 2
+      bit_size: 2
+      enum: NR
+    - name: MWID
+      description: Memory data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: SDCR_MWID
+    - name: NB
+      description: Number of internal banks
+      bit_offset: 6
+      bit_size: 1
+      enum: NB
+    - name: CAS
+      description: CAS latency
+      bit_offset: 7
+      bit_size: 2
+      enum: CAS
+    - name: WP
+      description: Write protection
+      bit_offset: 9
+      bit_size: 1
+    - name: SDCLK
+      description: SDRAM clock configuration
+      bit_offset: 10
+      bit_size: 2
+      enum: SDCLK
+    - name: RBURST
+      description: Burst read
+      bit_offset: 12
+      bit_size: 1
+    - name: RPIPE
+      description: Read pipe
+      bit_offset: 13
+      bit_size: 2
+      enum: RPIPE
+fieldset/SDTR:
+  description: SDRAM Timing register
+  fields:
+    - name: TMRD
+      description: Load Mode Register to Active
+      bit_offset: 0
+      bit_size: 4
+    - name: TXSR
+      description: Exit self-refresh delay
+      bit_offset: 4
+      bit_size: 4
+    - name: TRAS
+      description: Self refresh time
+      bit_offset: 8
+      bit_size: 4
+    - name: TRC
+      description: Row cycle delay
+      bit_offset: 12
+      bit_size: 4
+    - name: TWR
+      description: Recovery delay
+      bit_offset: 16
+      bit_size: 4
+    - name: TRP
+      description: Row precharge delay
+      bit_offset: 20
+      bit_size: 4
+    - name: TRCD
+      description: Row to column delay
+      bit_offset: 24
+      bit_size: 4
+fieldset/SDCMR:
+  description: SDRAM Command Mode register
+  fields:
+    - name: MODE
+      description: Command mode
+      bit_offset: 0
+      bit_size: 3
+      enum_write: MODE
+    - name: CTB2
+      description: Command target bank 2
+      bit_offset: 3
+      bit_size: 1
+    - name: CTB1
+      description: Command target bank 1
+      bit_offset: 4
+      bit_size: 1
+    - name: NRFS
+      description: Number of Auto-refresh
+      bit_offset: 5
+      bit_size: 4
+    - name: MRD
+      description: Mode Register definition
+      bit_offset: 9
+      bit_size: 13
+fieldset/SDRTR:
+  description: SDRAM Refresh Timer register
+  fields:
+    - name: CRE
+      description: Clear Refresh error flag
+      bit_offset: 0
+      bit_size: 1
+      enum_write: CRE
+    - name: COUNT
+      description: Refresh Timer Count
+      bit_offset: 1
+      bit_size: 13
+    - name: REIE
+      description: RES Interrupt Enable
+      bit_offset: 14
+      bit_size: 1
+fieldset/SDSR:
+  description: SDRAM Status register
+  fields:
+    - name: RE
+      description: Refresh error flag
+      bit_offset: 0
+      bit_size: 1
+    - name: MODES1
+      description: Status Mode for Bank 1
+      bit_offset: 1
+      bit_size: 2
+      enum_read: MODES1
+    - name: MODES2
+      description: Status Mode for Bank 2
+      bit_offset: 3
+      bit_size: 2
+      enum_read: MODES1
+    - name: BUSY
+      description: Busy status
+      bit_offset: 5
+      bit_size: 1
+enum/ACCMOD:
+  bit_size: 2
+  variants:
+    - name: A
+      description: Access mode A
+      value: 0
+    - name: B
+      description: Access mode B
+      value: 1
+    - name: C
+      description: Access mode C
+      value: 2
+    - name: D
+      description: Access mode D
+      value: 3
+enum/CAS:
+  bit_size: 2
+  variants:
+    - name: Clocks1
+      description: 1 cycle
+      value: 1
+    - name: Clocks2
+      description: 2 cycles
+      value: 2
+    - name: Clocks3
+      description: 3 cycles
+      value: 3
+enum/CPSIZE:
+  bit_size: 3
+  variants:
+    - name: NoBurstSplit
+      description: No burst split when crossing page boundary
+      value: 0
+    - name: Bytes128
+      description: 128 bytes CRAM page size
+      value: 1
+    - name: Bytes256
+      description: 256 bytes CRAM page size
+      value: 2
+    - name: Bytes512
+      description: 512 bytes CRAM page size
+      value: 3
+    - name: Bytes1024
+      description: 1024 bytes CRAM page size
+      value: 4
+enum/CRE:
+  bit_size: 1
+  variants:
+    - name: Clear
+      description: Refresh Error Flag is cleared
+      value: 1
+enum/ECCPS:
+  bit_size: 3
+  variants:
+    - name: Bytes256
+      description: ECC page size 256 bytes
+      value: 0
+    - name: Bytes512
+      description: ECC page size 512 bytes
+      value: 1
+    - name: Bytes1024
+      description: ECC page size 1024 bytes
+      value: 2
+    - name: Bytes2048
+      description: ECC page size 2048 bytes
+      value: 3
+    - name: Bytes4096
+      description: ECC page size 4096 bytes
+      value: 4
+    - name: Bytes8192
+      description: ECC page size 8192 bytes
+      value: 5
+enum/MODE:
+  bit_size: 3
+  variants:
+    - name: Normal
+      description: Normal Mode
+      value: 0
+    - name: ClockConfigurationEnable
+      description: Clock Configuration Enable
+      value: 1
+    - name: PALL
+      description: PALL (All Bank Precharge) command
+      value: 2
+    - name: AutoRefreshCommand
+      description: Auto-refresh command
+      value: 3
+    - name: LoadModeRegister
+      description: Load Mode Resgier
+      value: 4
+    - name: SelfRefreshCommand
+      description: Self-refresh command
+      value: 5
+    - name: PowerDownCommand
+      description: Power-down command
+      value: 6
+enum/MODES1:
+  bit_size: 2
+  variants:
+    - name: Normal
+      description: Normal Mode
+      value: 0
+    - name: SelfRefresh
+      description: Self-refresh mode
+      value: 1
+    - name: PowerDown
+      description: Power-down mode
+      value: 2
+enum/MTYP:
+  bit_size: 2
+  variants:
+    - name: SRAM
+      description: SRAM memory type
+      value: 0
+    - name: PSRAM
+      description: PSRAM (CRAM) memory type
+      value: 1
+    - name: Flash
+      description: NOR Flash/OneNAND Flash
+      value: 2
+enum/MWID:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: Memory data bus width 8 bits
+      value: 0
+    - name: Bits16
+      description: Memory data bus width 16 bits
+      value: 1
+    - name: Bits32
+      description: Memory data bus width 32 bits
+      value: 2
+enum/NB:
+  bit_size: 1
+  variants:
+    - name: NB2
+      description: Two internal Banks
+      value: 0
+    - name: NB4
+      description: Four internal Banks
+      value: 1
+enum/NC:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: 8 bits
+      value: 0
+    - name: Bits9
+      description: 9 bits
+      value: 1
+    - name: Bits10
+      description: 10 bits
+      value: 2
+    - name: Bits11
+      description: 11 bits
+      value: 3
+enum/NR:
+  bit_size: 2
+  variants:
+    - name: Bits11
+      description: 11 bits
+      value: 0
+    - name: Bits12
+      description: 12 bits
+      value: 1
+    - name: Bits13
+      description: 13 bits
+      value: 2
+enum/PTYP:
+  bit_size: 1
+  variants:
+    - name: NANDFlash
+      description: NAND Flash
+      value: 1
+enum/PWID:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: External memory device width 8 bits
+      value: 0
+    - name: Bits16
+      description: External memory device width 16 bits
+      value: 1
+enum/RPIPE:
+  bit_size: 2
+  variants:
+    - name: NoDelay
+      description: No clock cycle delay
+      value: 0
+    - name: Clocks1
+      description: One clock cycle delay
+      value: 1
+    - name: Clocks2
+      description: Two clock cycles delay
+      value: 2
+enum/SDCLK:
+  bit_size: 2
+  variants:
+    - name: Disabled
+      description: SDCLK clock disabled
+      value: 0
+    - name: Div2
+      description: SDCLK period = 2 x HCLK period
+      value: 2
+    - name: Div3
+      description: SDCLK period = 3 x HCLK period
+      value: 3
+enum/SDCR_MWID:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: Memory data bus width 8 bits
+      value: 0
+    - name: Bits16
+      description: Memory data bus width 16 bits
+      value: 1
+    - name: Bits32
+      description: Memory data bus width 32 bits
+      value: 2
+enum/WAITCFG:
+  bit_size: 1
+  variants:
+    - name: BeforeWaitState
+      description: NWAIT signal is active one data cycle before wait state
+      value: 0
+    - name: DuringWaitState
+      description: NWAIT signal is active during wait state
+      value: 1
+enum/WAITPOL:
+  bit_size: 1
+  variants:
+    - name: ActiveLow
+      description: NWAIT active low
+      value: 0
+    - name: ActiveHigh
+      description: NWAIT active high
+      value: 1

data/registers/fsmc_v1x3.yaml

@@ -0,0 +1,478 @@
+# stm32f3
+---
+block/FMC:
+  description: Flexible memory controller
+  items:
+    - name: BCR1
+      description: SRAM/NOR-Flash chip-select control register 1
+      byte_offset: 0
+      fieldset: BCR1
+    - name: BCR
+      description: SRAM/NOR-Flash chip-select control register 2-4
+      array:
+        len: 3
+        stride: 8
+      byte_offset: 8
+      fieldset: BCR
+    - name: BTR
+      description: SRAM/NOR-Flash chip-select timing register 1-4
+      array:
+        len: 4
+        stride: 8
+      byte_offset: 4
+      fieldset: BTR
+    - name: BWTR
+      description: SRAM/NOR-Flash write timing registers 1-4
+      array:
+        len: 4
+        stride: 8
+      byte_offset: 260
+      fieldset: BWTR
+    - name: PCR
+      description: PC Card/NAND Flash control register 2-4
+      array:
+        len: 3
+        stride: 32
+      byte_offset: 96
+      fieldset: PCR
+    - name: SR
+      description: FIFO status and interrupt register 2-4
+      array:
+        len: 3
+        stride: 32
+      byte_offset: 100
+      fieldset: SR
+    - name: PMEM
+      description: Common memory space timing register 2-4
+      array:
+        len: 3
+        stride: 32
+      byte_offset: 104
+      fieldset: PMEM
+    - name: PATT
+      description: Attribute memory space timing register 2-4
+      array:
+        len: 3
+        stride: 32
+      byte_offset: 108
+      fieldset: PATT
+    - name: PIO4
+      description: I/O space timing register 4
+      byte_offset: 176
+      fieldset: PIO4
+    - name: ECCR
+      description: ECC result register 2-3
+      array:
+        len: 2
+        stride: 32
+      byte_offset: 116
+      access: Read
+      fieldset: ECCR
+fieldset/BCR1:
+  description: SRAM/NOR-Flash chip-select control register 1
+  fields:
+    - name: MBKEN
+      description: Memory bank enable bit
+      bit_offset: 0
+      bit_size: 1
+    - name: MUXEN
+      description: Address/data multiplexing enable bit
+      bit_offset: 1
+      bit_size: 1
+    - name: MTYP
+      description: Memory type
+      bit_offset: 2
+      bit_size: 2
+      enum: MTYP
+    - name: MWID
+      description: Memory data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: MWID
+    - name: FACCEN
+      description: Flash access enable
+      bit_offset: 6
+      bit_size: 1
+    - name: BURSTEN
+      description: Burst enable bit
+      bit_offset: 8
+      bit_size: 1
+    - name: WAITPOL
+      description: Wait signal polarity bit
+      bit_offset: 9
+      bit_size: 1
+      enum: WAITPOL
+    - name: WRAPMOD
+      description: WRAPMOD
+      bit_offset: 10
+      bit_size: 1
+    - name: WAITCFG
+      description: Wait timing configuration
+      bit_offset: 11
+      bit_size: 1
+      enum: WAITCFG
+    - name: WREN
+      description: Write enable bit
+      bit_offset: 12
+      bit_size: 1
+    - name: WAITEN
+      description: Wait enable bit
+      bit_offset: 13
+      bit_size: 1
+    - name: EXTMOD
+      description: Extended mode enable
+      bit_offset: 14
+      bit_size: 1
+    - name: ASYNCWAIT
+      description: Wait signal during asynchronous transfers
+      bit_offset: 15
+      bit_size: 1
+    - name: CBURSTRW
+      description: Write burst enable
+      bit_offset: 19
+      bit_size: 1
+    - name: CCLKEN
+      description: Continuous clock enable
+      bit_offset: 20
+      bit_size: 1
+fieldset/BCR:
+  description: SRAM/NOR-Flash chip-select control register 2-4
+  fields:
+    - name: MBKEN
+      description: Memory bank enable bit
+      bit_offset: 0
+      bit_size: 1
+    - name: MUXEN
+      description: Address/data multiplexing enable bit
+      bit_offset: 1
+      bit_size: 1
+    - name: MTYP
+      description: Memory type
+      bit_offset: 2
+      bit_size: 2
+      enum: MTYP
+    - name: MWID
+      description: Memory data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: MWID
+    - name: FACCEN
+      description: Flash access enable
+      bit_offset: 6
+      bit_size: 1
+    - name: BURSTEN
+      description: Burst enable bit
+      bit_offset: 8
+      bit_size: 1
+    - name: WAITPOL
+      description: Wait signal polarity bit
+      bit_offset: 9
+      bit_size: 1
+      enum: WAITPOL
+    - name: WRAPMOD
+      description: WRAPMOD
+      bit_offset: 10
+      bit_size: 1
+    - name: WAITCFG
+      description: Wait timing configuration
+      bit_offset: 11
+      bit_size: 1
+      enum: WAITCFG
+    - name: WREN
+      description: Write enable bit
+      bit_offset: 12
+      bit_size: 1
+    - name: WAITEN
+      description: Wait enable bit
+      bit_offset: 13
+      bit_size: 1
+    - name: EXTMOD
+      description: Extended mode enable
+      bit_offset: 14
+      bit_size: 1
+    - name: ASYNCWAIT
+      description: Wait signal during asynchronous transfers
+      bit_offset: 15
+      bit_size: 1
+    - name: CBURSTRW
+      description: Write burst enable
+      bit_offset: 19
+      bit_size: 1
+fieldset/BTR:
+  description: SRAM/NOR-Flash chip-select timing register
+  fields:
+    - name: ADDSET
+      description: Address setup phase duration
+      bit_offset: 0
+      bit_size: 4
+    - name: ADDHLD
+      description: Address-hold phase duration
+      bit_offset: 4
+      bit_size: 4
+    - name: DATAST
+      description: Data-phase duration
+      bit_offset: 8
+      bit_size: 8
+    - name: BUSTURN
+      description: Bus turnaround phase duration
+      bit_offset: 16
+      bit_size: 4
+    - name: CLKDIV
+      description: Clock divide ratio (for FMC_CLK signal)
+      bit_offset: 20
+      bit_size: 4
+    - name: DATLAT
+      description: Data latency for synchronous memory
+      bit_offset: 24
+      bit_size: 4
+    - name: ACCMOD
+      description: Access mode
+      bit_offset: 28
+      bit_size: 2
+      enum: ACCMOD
+fieldset/BWTR:
+  description: SRAM/NOR-Flash write timing registers
+  fields:
+    - name: ADDSET
+      description: Address setup phase duration
+      bit_offset: 0
+      bit_size: 4
+    - name: ADDHLD
+      description: Address-hold phase duration
+      bit_offset: 4
+      bit_size: 4
+    - name: DATAST
+      description: Data-phase duration
+      bit_offset: 8
+      bit_size: 8
+    - name: ACCMOD
+      description: Access mode
+      bit_offset: 28
+      bit_size: 2
+      enum: ACCMOD
+fieldset/PCR:
+  description: PC Card/NAND Flash control register
+  fields:
+    - name: PWAITEN
+      description: Wait feature enable bit
+      bit_offset: 1
+      bit_size: 1
+    - name: PBKEN
+      description: NAND Flash memory bank enable bit
+      bit_offset: 2
+      bit_size: 1
+    - name: PTYP
+      description: Memory type
+      bit_offset: 3
+      bit_size: 1
+      enum: PTYP
+    - name: PWID
+      description: Data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: PWID
+    - name: ECCEN
+      description: ECC computation logic enable bit
+      bit_offset: 6
+      bit_size: 1
+    - name: TCLR
+      description: CLE to RE delay
+      bit_offset: 9
+      bit_size: 4
+    - name: TAR
+      description: ALE to RE delay
+      bit_offset: 13
+      bit_size: 4
+    - name: ECCPS
+      description: ECC page size
+      bit_offset: 17
+      bit_size: 3
+      enum: ECCPS
+fieldset/SR:
+  description: FIFO status and interrupt register
+  fields:
+    - name: IRS
+      description: Interrupt rising edge status
+      bit_offset: 0
+      bit_size: 1
+    - name: ILS
+      description: Interrupt high-level status
+      bit_offset: 1
+      bit_size: 1
+    - name: IFS
+      description: Interrupt falling edge status
+      bit_offset: 2
+      bit_size: 1
+    - name: IREN
+      description: Interrupt rising edge detection enable bit
+      bit_offset: 3
+      bit_size: 1
+    - name: ILEN
+      description: Interrupt high-level detection enable bit
+      bit_offset: 4
+      bit_size: 1
+    - name: IFEN
+      description: Interrupt falling edge detection enable bit
+      bit_offset: 5
+      bit_size: 1
+    - name: FEMPT
+      description: FIFO empty status
+      bit_offset: 6
+      bit_size: 1
+fieldset/PMEM:
+  description: Common memory space timing register
+  fields:
+    - name: MEMSET
+      description: Common memory x setup time
+      bit_offset: 0
+      bit_size: 8
+    - name: MEMWAIT
+      description: Common memory wait time
+      bit_offset: 8
+      bit_size: 8
+    - name: MEMHOLD
+      description: Common memory hold time
+      bit_offset: 16
+      bit_size: 8
+    - name: MEMHIZ
+      description: Common memory x data bus Hi-Z time
+      bit_offset: 24
+      bit_size: 8
+fieldset/PATT:
+  description: Attribute memory space timing register
+  fields:
+    - name: ATTSET
+      description: Attribute memory setup time
+      bit_offset: 0
+      bit_size: 8
+    - name: ATTWAIT
+      description: Attribute memory wait time
+      bit_offset: 8
+      bit_size: 8
+    - name: ATTHOLD
+      description: Attribute memory hold time
+      bit_offset: 16
+      bit_size: 8
+    - name: ATTHIZ
+      description: Attribute memory data bus Hi-Z time
+      bit_offset: 24
+      bit_size: 8
+fieldset/PIO4:
+  description: I/O space timing register 4
+  fields:
+    - name: IOSETx
+      description: IOSETx
+      bit_offset: 0
+      bit_size: 8
+    - name: IOWAITx
+      description: IOWAITx
+      bit_offset: 8
+      bit_size: 8
+    - name: IOHOLDx
+      description: IOHOLDx
+      bit_offset: 16
+      bit_size: 8
+    - name: IOHIZx
+      description: IOHIZx
+      bit_offset: 24
+      bit_size: 8
+fieldset/ECCR:
+  description: ECC result register
+  fields:
+    - name: ECC
+      description: ECC computation result value
+      bit_offset: 0
+      bit_size: 32
+enum/ACCMOD:
+  bit_size: 2
+  variants:
+    - name: A
+      description: Access mode A
+      value: 0
+    - name: B
+      description: Access mode B
+      value: 1
+    - name: C
+      description: Access mode C
+      value: 2
+    - name: D
+      description: Access mode D
+      value: 3
+enum/ECCPS:
+  bit_size: 3
+  variants:
+    - name: Bytes256
+      description: ECC page size 256 bytes
+      value: 0
+    - name: Bytes512
+      description: ECC page size 512 bytes
+      value: 1
+    - name: Bytes1024
+      description: ECC page size 1024 bytes
+      value: 2
+    - name: Bytes2048
+      description: ECC page size 2048 bytes
+      value: 3
+    - name: Bytes4096
+      description: ECC page size 4096 bytes
+      value: 4
+    - name: Bytes8192
+      description: ECC page size 8192 bytes
+      value: 5
+enum/MTYP:
+  bit_size: 2
+  variants:
+    - name: SRAM
+      description: SRAM memory type
+      value: 0
+    - name: PSRAM
+      description: PSRAM (CRAM) memory type
+      value: 1
+    - name: Flash
+      description: NOR Flash/OneNAND Flash
+      value: 2
+enum/MWID:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: Memory data bus width 8 bits
+      value: 0
+    - name: Bits16
+      description: Memory data bus width 16 bits
+      value: 1
+    - name: Bits32
+      description: Memory data bus width 32 bits
+      value: 2
+enum/PTYP:
+  bit_size: 1
+  variants:
+    - name: NANDFlash
+      description: NAND Flash
+      value: 1
+enum/PWID:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: External memory device width 8 bits
+      value: 0
+    - name: Bits16
+      description: External memory device width 16 bits
+      value: 1
+enum/WAITCFG:
+  bit_size: 1
+  variants:
+    - name: BeforeWaitState
+      description: NWAIT signal is active one data cycle before wait state
+      value: 0
+    - name: DuringWaitState
+      description: NWAIT signal is active during wait state
+      value: 1
+enum/WAITPOL:
+  bit_size: 1
+  variants:
+    - name: ActiveLow
+      description: NWAIT active low
+      value: 0
+    - name: ActiveHigh
+      description: NWAIT active high
+      value: 1

data/registers/fsmc_v2x1.yaml

@@ -0,0 +1,468 @@
+# stm32l4
+---
+block/FMC:
+  description: Flexible memory controller
+  items:
+    - name: BCR1
+      description: SRAM/NOR-Flash chip-select control register 1
+      byte_offset: 0
+      fieldset: BCR1
+    - name: BCR
+      description: SRAM/NOR-Flash chip-select control register 2-4
+      array:
+        len: 3
+        stride: 8
+      byte_offset: 8
+      fieldset: BCR
+    - name: BTR
+      description: SRAM/NOR-Flash chip-select timing register 1-4
+      array:
+        len: 4
+        stride: 8
+      byte_offset: 4
+      fieldset: BTR
+    - name: BWTR
+      description: SRAM/NOR-Flash write timing registers 1-4
+      array:
+        len: 4
+        stride: 8
+      byte_offset: 260
+      fieldset: BWTR
+    - name: PCR
+      description: PC Card/NAND Flash control register
+      byte_offset: 128
+      fieldset: PCR
+    - name: SR
+      description: FIFO status and interrupt register
+      byte_offset: 132
+      fieldset: SR
+    - name: PMEM
+      description: Common memory space timing register
+      byte_offset: 136
+      fieldset: PMEM
+    - name: PATT
+      description: Attribute memory space timing register
+      byte_offset: 140
+      fieldset: PATT
+    - name: ECCR
+      description: ECC result register
+      byte_offset: 148
+      access: Read
+      fieldset: ECCR
+fieldset/BCR1:
+  description: SRAM/NOR-Flash chip-select control register 1
+  fields:
+    - name: MBKEN
+      description: Memory bank enable bit
+      bit_offset: 0
+      bit_size: 1
+    - name: MUXEN
+      description: Address/data multiplexing enable bit
+      bit_offset: 1
+      bit_size: 1
+    - name: MTYP
+      description: Memory type
+      bit_offset: 2
+      bit_size: 2
+      enum: MTYP
+    - name: MWID
+      description: Memory data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: MWID
+    - name: FACCEN
+      description: Flash access enable
+      bit_offset: 6
+      bit_size: 1
+    - name: BURSTEN
+      description: Burst enable bit
+      bit_offset: 8
+      bit_size: 1
+    - name: WAITPOL
+      description: Wait signal polarity bit
+      bit_offset: 9
+      bit_size: 1
+      enum: WAITPOL
+    - name: WAITCFG
+      description: Wait timing configuration
+      bit_offset: 11
+      bit_size: 1
+      enum: WAITCFG
+    - name: WREN
+      description: Write enable bit
+      bit_offset: 12
+      bit_size: 1
+    - name: WAITEN
+      description: Wait enable bit
+      bit_offset: 13
+      bit_size: 1
+    - name: EXTMOD
+      description: Extended mode enable
+      bit_offset: 14
+      bit_size: 1
+    - name: ASYNCWAIT
+      description: Wait signal during asynchronous transfers
+      bit_offset: 15
+      bit_size: 1
+    - name: CPSIZE
+      description: CRAM page size
+      bit_offset: 16
+      bit_size: 3
+      enum: CPSIZE
+    - name: CBURSTRW
+      description: Write burst enable
+      bit_offset: 19
+      bit_size: 1
+    - name: CCLKEN
+      description: Continuous clock enable
+      bit_offset: 20
+      bit_size: 1
+    - name: WFDIS
+      description: Write FIFO disable
+      bit_offset: 21
+      bit_size: 1
+fieldset/BCR:
+  description: SRAM/NOR-Flash chip-select control register 2-4
+  fields:
+    - name: MBKEN
+      description: Memory bank enable bit
+      bit_offset: 0
+      bit_size: 1
+    - name: MUXEN
+      description: Address/data multiplexing enable bit
+      bit_offset: 1
+      bit_size: 1
+    - name: MTYP
+      description: Memory type
+      bit_offset: 2
+      bit_size: 2
+      enum: MTYP
+    - name: MWID
+      description: Memory data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: MWID
+    - name: FACCEN
+      description: Flash access enable
+      bit_offset: 6
+      bit_size: 1
+    - name: BURSTEN
+      description: Burst enable bit
+      bit_offset: 8
+      bit_size: 1
+    - name: WAITPOL
+      description: Wait signal polarity bit
+      bit_offset: 9
+      bit_size: 1
+      enum: WAITPOL
+    - name: WAITCFG
+      description: Wait timing configuration
+      bit_offset: 11
+      bit_size: 1
+      enum: WAITCFG
+    - name: WREN
+      description: Write enable bit
+      bit_offset: 12
+      bit_size: 1
+    - name: WAITEN
+      description: Wait enable bit
+      bit_offset: 13
+      bit_size: 1
+    - name: EXTMOD
+      description: Extended mode enable
+      bit_offset: 14
+      bit_size: 1
+    - name: ASYNCWAIT
+      description: Wait signal during asynchronous transfers
+      bit_offset: 15
+      bit_size: 1
+    - name: CPSIZE
+      description: CRAM page size
+      bit_offset: 16
+      bit_size: 3
+      enum: CPSIZE
+    - name: CBURSTRW
+      description: Write burst enable
+      bit_offset: 19
+      bit_size: 1
+fieldset/BTR:
+  description: SRAM/NOR-Flash chip-select timing register
+  fields:
+    - name: ADDSET
+      description: Address setup phase duration
+      bit_offset: 0
+      bit_size: 4
+    - name: ADDHLD
+      description: Address-hold phase duration
+      bit_offset: 4
+      bit_size: 4
+    - name: DATAST
+      description: Data-phase duration
+      bit_offset: 8
+      bit_size: 8
+    - name: BUSTURN
+      description: Bus turnaround phase duration
+      bit_offset: 16
+      bit_size: 4
+    - name: CLKDIV
+      description: Clock divide ratio (for FMC_CLK signal)
+      bit_offset: 20
+      bit_size: 4
+    - name: DATLAT
+      description: Data latency for synchronous memory
+      bit_offset: 24
+      bit_size: 4
+    - name: ACCMOD
+      description: Access mode
+      bit_offset: 28
+      bit_size: 2
+      enum: ACCMOD
+fieldset/BWTR:
+  description: SRAM/NOR-Flash write timing registers
+  fields:
+    - name: ADDSET
+      description: Address setup phase duration
+      bit_offset: 0
+      bit_size: 4
+    - name: ADDHLD
+      description: Address-hold phase duration
+      bit_offset: 4
+      bit_size: 4
+    - name: DATAST
+      description: Data-phase duration
+      bit_offset: 8
+      bit_size: 8
+    - name: BUSTURN
+      description: Bus turnaround phase duration
+      bit_offset: 16
+      bit_size: 4
+    - name: ACCMOD
+      description: Access mode
+      bit_offset: 28
+      bit_size: 2
+      enum: ACCMOD
+fieldset/PCR:
+  description: PC Card/NAND Flash control register
+  fields:
+    - name: PWAITEN
+      description: Wait feature enable bit
+      bit_offset: 1
+      bit_size: 1
+    - name: PBKEN
+      description: NAND Flash memory bank enable bit
+      bit_offset: 2
+      bit_size: 1
+    - name: PTYP
+      description: Memory type
+      bit_offset: 3
+      bit_size: 1
+      enum: PTYP
+    - name: PWID
+      description: Data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: PWID
+    - name: ECCEN
+      description: ECC computation logic enable bit
+      bit_offset: 6
+      bit_size: 1
+    - name: TCLR
+      description: CLE to RE delay
+      bit_offset: 9
+      bit_size: 4
+    - name: TAR
+      description: ALE to RE delay
+      bit_offset: 13
+      bit_size: 4
+    - name: ECCPS
+      description: ECC page size
+      bit_offset: 17
+      bit_size: 3
+      enum: ECCPS
+fieldset/SR:
+  description: FIFO status and interrupt register
+  fields:
+    - name: IRS
+      description: Interrupt rising edge status
+      bit_offset: 0
+      bit_size: 1
+    - name: ILS
+      description: Interrupt high-level status
+      bit_offset: 1
+      bit_size: 1
+    - name: IFS
+      description: Interrupt falling edge status
+      bit_offset: 2
+      bit_size: 1
+    - name: IREN
+      description: Interrupt rising edge detection enable bit
+      bit_offset: 3
+      bit_size: 1
+    - name: ILEN
+      description: Interrupt high-level detection enable bit
+      bit_offset: 4
+      bit_size: 1
+    - name: IFEN
+      description: Interrupt falling edge detection enable bit
+      bit_offset: 5
+      bit_size: 1
+    - name: FEMPT
+      description: FIFO empty status
+      bit_offset: 6
+      bit_size: 1
+fieldset/PMEM:
+  description: Common memory space timing register
+  fields:
+    - name: MEMSET
+      description: Common memory x setup time
+      bit_offset: 0
+      bit_size: 8
+    - name: MEMWAIT
+      description: Common memory wait time
+      bit_offset: 8
+      bit_size: 8
+    - name: MEMHOLD
+      description: Common memory hold time
+      bit_offset: 16
+      bit_size: 8
+    - name: MEMHIZ
+      description: Common memory x data bus Hi-Z time
+      bit_offset: 24
+      bit_size: 8
+fieldset/PATT:
+  description: Attribute memory space timing register
+  fields:
+    - name: ATTSET
+      description: Attribute memory setup time
+      bit_offset: 0
+      bit_size: 8
+    - name: ATTWAIT
+      description: Attribute memory wait time
+      bit_offset: 8
+      bit_size: 8
+    - name: ATTHOLD
+      description: Attribute memory hold time
+      bit_offset: 16
+      bit_size: 8
+    - name: ATTHIZ
+      description: Attribute memory data bus Hi-Z time
+      bit_offset: 24
+      bit_size: 8
+fieldset/ECCR:
+  description: ECC result register
+  fields:
+    - name: ECC
+      description: ECC computation result value
+      bit_offset: 0
+      bit_size: 32
+enum/ACCMOD:
+  bit_size: 2
+  variants:
+    - name: A
+      description: Access mode A
+      value: 0
+    - name: B
+      description: Access mode B
+      value: 1
+    - name: C
+      description: Access mode C
+      value: 2
+    - name: D
+      description: Access mode D
+      value: 3
+enum/CPSIZE:
+  bit_size: 3
+  variants:
+    - name: NoBurstSplit
+      description: No burst split when crossing page boundary
+      value: 0
+    - name: Bytes128
+      description: 128 bytes CRAM page size
+      value: 1
+    - name: Bytes256
+      description: 256 bytes CRAM page size
+      value: 2
+    - name: Bytes512
+      description: 512 bytes CRAM page size
+      value: 3
+    - name: Bytes1024
+      description: 1024 bytes CRAM page size
+      value: 4
+enum/ECCPS:
+  bit_size: 3
+  variants:
+    - name: Bytes256
+      description: ECC page size 256 bytes
+      value: 0
+    - name: Bytes512
+      description: ECC page size 512 bytes
+      value: 1
+    - name: Bytes1024
+      description: ECC page size 1024 bytes
+      value: 2
+    - name: Bytes2048
+      description: ECC page size 2048 bytes
+      value: 3
+    - name: Bytes4096
+      description: ECC page size 4096 bytes
+      value: 4
+    - name: Bytes8192
+      description: ECC page size 8192 bytes
+      value: 5
+enum/MTYP:
+  bit_size: 2
+  variants:
+    - name: SRAM
+      description: SRAM memory type
+      value: 0
+    - name: PSRAM
+      description: PSRAM (CRAM) memory type
+      value: 1
+    - name: Flash
+      description: NOR Flash/OneNAND Flash
+      value: 2
+enum/MWID:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: Memory data bus width 8 bits
+      value: 0
+    - name: Bits16
+      description: Memory data bus width 16 bits
+      value: 1
+    - name: Bits32
+      description: Memory data bus width 32 bits
+      value: 2
+enum/PTYP:
+  bit_size: 1
+  variants:
+    - name: NANDFlash
+      description: NAND Flash
+      value: 1
+enum/PWID:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: External memory device width 8 bits
+      value: 0
+    - name: Bits16
+      description: External memory device width 16 bits
+      value: 1
+enum/WAITCFG:
+  bit_size: 1
+  variants:
+    - name: BeforeWaitState
+      description: NWAIT signal is active one data cycle before wait state
+      value: 0
+    - name: DuringWaitState
+      description: NWAIT signal is active during wait state
+      value: 1
+enum/WAITPOL:
+  bit_size: 1
+  variants:
+    - name: ActiveLow
+      description: NWAIT active low
+      value: 0
+    - name: ActiveHigh
+      description: NWAIT active high
+      value: 1

data/registers/fsmc_v3x1.yaml

@@ -0,0 +1,516 @@
+# stm32l5
+# stm32g4
+---
+block/FMC:
+  description: Flexible memory controller
+  items:
+    - name: BCR1
+      description: SRAM/NOR-Flash chip-select control register 1
+      byte_offset: 0
+      fieldset: BCR1
+    - name: BCR
+      description: SRAM/NOR-Flash chip-select control register 2-4
+      array:
+        len: 3
+        stride: 8
+      byte_offset: 8
+      fieldset: BCR
+    - name: BTR
+      description: SRAM/NOR-Flash chip-select timing register 1-4
+      array:
+        len: 4
+        stride: 8
+      byte_offset: 4
+      fieldset: BTR
+    - name: PCSCNTR
+      description: PSRAM chip select counter register
+      byte_offset: 32
+      fieldset: PCSCNTR
+    - name: BWTR
+      description: SRAM/NOR-Flash write timing registers 1-4
+      array:
+        len: 4
+        stride: 8
+      byte_offset: 260
+      fieldset: BWTR
+    - name: PCR
+      description: PC Card/NAND Flash control register
+      byte_offset: 128
+      fieldset: PCR
+    - name: SR
+      description: FIFO status and interrupt register
+      byte_offset: 132
+      fieldset: SR
+    - name: PMEM
+      description: Common memory space timing register
+      byte_offset: 136
+      fieldset: PMEM
+    - name: PATT
+      description: Attribute memory space timing register
+      byte_offset: 140
+      fieldset: PATT
+    - name: ECCR
+      description: ECC result register
+      byte_offset: 148
+      access: Read
+      fieldset: ECCR
+fieldset/BCR1:
+  description: SRAM/NOR-Flash chip-select control register 1
+  fields:
+    - name: MBKEN
+      description: Memory bank enable bit
+      bit_offset: 0
+      bit_size: 1
+    - name: MUXEN
+      description: Address/data multiplexing enable bit
+      bit_offset: 1
+      bit_size: 1
+    - name: MTYP
+      description: Memory type
+      bit_offset: 2
+      bit_size: 2
+      enum: MTYP
+    - name: MWID
+      description: Memory data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: MWID
+    - name: FACCEN
+      description: Flash access enable
+      bit_offset: 6
+      bit_size: 1
+    - name: BURSTEN
+      description: Burst enable bit
+      bit_offset: 8
+      bit_size: 1
+    - name: WAITPOL
+      description: Wait signal polarity bit
+      bit_offset: 9
+      bit_size: 1
+      enum: WAITPOL
+    - name: WAITCFG
+      description: Wait timing configuration
+      bit_offset: 11
+      bit_size: 1
+      enum: WAITCFG
+    - name: WREN
+      description: Write enable bit
+      bit_offset: 12
+      bit_size: 1
+    - name: WAITEN
+      description: Wait enable bit
+      bit_offset: 13
+      bit_size: 1
+    - name: EXTMOD
+      description: Extended mode enable
+      bit_offset: 14
+      bit_size: 1
+    - name: ASYNCWAIT
+      description: Wait signal during asynchronous transfers
+      bit_offset: 15
+      bit_size: 1
+    - name: CPSIZE
+      description: CRAM page size
+      bit_offset: 16
+      bit_size: 3
+      enum: CPSIZE
+    - name: CBURSTRW
+      description: Write burst enable
+      bit_offset: 19
+      bit_size: 1
+    - name: CCLKEN
+      description: Continuous clock enable
+      bit_offset: 20
+      bit_size: 1
+    - name: WFDIS
+      description: Write FIFO disable
+      bit_offset: 21
+      bit_size: 1
+    - name: NBLSET
+      description: Byte lane (NBL) setup
+      bit_offset: 22
+      bit_size: 2
+    - name: FMCEN
+      description: FMC controller enable
+      bit_offset: 31
+      bit_size: 1
+fieldset/BCR:
+  description: SRAM/NOR-Flash chip-select control register 2-4
+  fields:
+    - name: MBKEN
+      description: Memory bank enable bit
+      bit_offset: 0
+      bit_size: 1
+    - name: MUXEN
+      description: Address/data multiplexing enable bit
+      bit_offset: 1
+      bit_size: 1
+    - name: MTYP
+      description: Memory type
+      bit_offset: 2
+      bit_size: 2
+      enum: MTYP
+    - name: MWID
+      description: Memory data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: MWID
+    - name: FACCEN
+      description: Flash access enable
+      bit_offset: 6
+      bit_size: 1
+    - name: BURSTEN
+      description: Burst enable bit
+      bit_offset: 8
+      bit_size: 1
+    - name: WAITPOL
+      description: Wait signal polarity bit
+      bit_offset: 9
+      bit_size: 1
+      enum: WAITPOL
+    - name: WAITCFG
+      description: Wait timing configuration
+      bit_offset: 11
+      bit_size: 1
+      enum: WAITCFG
+    - name: WREN
+      description: Write enable bit
+      bit_offset: 12
+      bit_size: 1
+    - name: WAITEN
+      description: Wait enable bit
+      bit_offset: 13
+      bit_size: 1
+    - name: EXTMOD
+      description: Extended mode enable
+      bit_offset: 14
+      bit_size: 1
+    - name: ASYNCWAIT
+      description: Wait signal during asynchronous transfers
+      bit_offset: 15
+      bit_size: 1
+    - name: CPSIZE
+      description: CRAM page size
+      bit_offset: 16
+      bit_size: 3
+      enum: CPSIZE
+    - name: CBURSTRW
+      description: Write burst enable
+      bit_offset: 19
+      bit_size: 1
+    - name: NBLSET
+      description: Byte lane (NBL) setup
+      bit_offset: 22
+      bit_size: 2
+fieldset/BTR:
+  description: SRAM/NOR-Flash chip-select timing register
+  fields:
+    - name: ADDSET
+      description: Address setup phase duration
+      bit_offset: 0
+      bit_size: 4
+    - name: ADDHLD
+      description: Address-hold phase duration
+      bit_offset: 4
+      bit_size: 4
+    - name: DATAST
+      description: Data-phase duration
+      bit_offset: 8
+      bit_size: 8
+    - name: BUSTURN
+      description: Bus turnaround phase duration
+      bit_offset: 16
+      bit_size: 4
+    - name: CLKDIV
+      description: Clock divide ratio (for FMC_CLK signal)
+      bit_offset: 20
+      bit_size: 4
+    - name: DATLAT
+      description: Data latency for synchronous memory
+      bit_offset: 24
+      bit_size: 4
+    - name: ACCMOD
+      description: Access mode
+      bit_offset: 28
+      bit_size: 2
+      enum: ACCMOD
+    - name: DATAHLD
+      description: Data hold phase duration
+      bit_offset: 30
+      bit_size: 2
+fieldset/PCSCNTR:
+  description: PSRAM chip select counter register
+  fields:
+    - name: CSCOUNT
+      description: Chip select counter
+      bit_offset: 0
+      bit_size: 16
+    - name: CNTB1EN
+      description: Counter Bank 1 enable
+      bit_offset: 16
+      bit_size: 1
+    - name: CNTB2EN
+      description: Counter Bank 2 enable
+      bit_offset: 17
+      bit_size: 1
+    - name: CNTB3EN
+      description: Counter Bank 3 enable
+      bit_offset: 18
+      bit_size: 1
+    - name: CNTB4EN
+      description: Counter Bank 4 enable
+      bit_offset: 19
+      bit_size: 1
+fieldset/BWTR:
+  description: SRAM/NOR-Flash write timing registers
+  fields:
+    - name: ADDSET
+      description: Address setup phase duration
+      bit_offset: 0
+      bit_size: 4
+    - name: ADDHLD
+      description: Address-hold phase duration
+      bit_offset: 4
+      bit_size: 4
+    - name: DATAST
+      description: Data-phase duration
+      bit_offset: 8
+      bit_size: 8
+    - name: BUSTURN
+      description: Bus turnaround phase duration
+      bit_offset: 16
+      bit_size: 4
+    - name: ACCMOD
+      description: Access mode
+      bit_offset: 28
+      bit_size: 2
+      enum: ACCMOD
+    - name: DATAHLD
+      description: Data hold phase duration
+      bit_offset: 30
+      bit_size: 2
+fieldset/PCR:
+  description: PC Card/NAND Flash control register
+  fields:
+    - name: PWAITEN
+      description: Wait feature enable bit
+      bit_offset: 1
+      bit_size: 1
+    - name: PBKEN
+      description: NAND Flash memory bank enable bit
+      bit_offset: 2
+      bit_size: 1
+    - name: PTYP
+      description: Memory type
+      bit_offset: 3
+      bit_size: 1
+      enum: PTYP
+    - name: PWID
+      description: Data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: PWID
+    - name: ECCEN
+      description: ECC computation logic enable bit
+      bit_offset: 6
+      bit_size: 1
+    - name: TCLR
+      description: CLE to RE delay
+      bit_offset: 9
+      bit_size: 4
+    - name: TAR
+      description: ALE to RE delay
+      bit_offset: 13
+      bit_size: 4
+    - name: ECCPS
+      description: ECC page size
+      bit_offset: 17
+      bit_size: 3
+      enum: ECCPS
+fieldset/SR:
+  description: FIFO status and interrupt register
+  fields:
+    - name: IRS
+      description: Interrupt rising edge status
+      bit_offset: 0
+      bit_size: 1
+    - name: ILS
+      description: Interrupt high-level status
+      bit_offset: 1
+      bit_size: 1
+    - name: IFS
+      description: Interrupt falling edge status
+      bit_offset: 2
+      bit_size: 1
+    - name: IREN
+      description: Interrupt rising edge detection enable bit
+      bit_offset: 3
+      bit_size: 1
+    - name: ILEN
+      description: Interrupt high-level detection enable bit
+      bit_offset: 4
+      bit_size: 1
+    - name: IFEN
+      description: Interrupt falling edge detection enable bit
+      bit_offset: 5
+      bit_size: 1
+    - name: FEMPT
+      description: FIFO empty status
+      bit_offset: 6
+      bit_size: 1
+fieldset/PMEM:
+  description: Common memory space timing register
+  fields:
+    - name: MEMSET
+      description: Common memory x setup time
+      bit_offset: 0
+      bit_size: 8
+    - name: MEMWAIT
+      description: Common memory wait time
+      bit_offset: 8
+      bit_size: 8
+    - name: MEMHOLD
+      description: Common memory hold time
+      bit_offset: 16
+      bit_size: 8
+    - name: MEMHIZ
+      description: Common memory x data bus Hi-Z time
+      bit_offset: 24
+      bit_size: 8
+fieldset/PATT:
+  description: Attribute memory space timing register
+  fields:
+    - name: ATTSET
+      description: Attribute memory setup time
+      bit_offset: 0
+      bit_size: 8
+    - name: ATTWAIT
+      description: Attribute memory wait time
+      bit_offset: 8
+      bit_size: 8
+    - name: ATTHOLD
+      description: Attribute memory hold time
+      bit_offset: 16
+      bit_size: 8
+    - name: ATTHIZ
+      description: Attribute memory data bus Hi-Z time
+      bit_offset: 24
+      bit_size: 8
+fieldset/ECCR:
+  description: ECC result register
+  fields:
+    - name: ECC
+      description: ECC computation result value
+      bit_offset: 0
+      bit_size: 32
+enum/ACCMOD:
+  bit_size: 2
+  variants:
+    - name: A
+      description: Access mode A
+      value: 0
+    - name: B
+      description: Access mode B
+      value: 1
+    - name: C
+      description: Access mode C
+      value: 2
+    - name: D
+      description: Access mode D
+      value: 3
+enum/CPSIZE:
+  bit_size: 3
+  variants:
+    - name: NoBurstSplit
+      description: No burst split when crossing page boundary
+      value: 0
+    - name: Bytes128
+      description: 128 bytes CRAM page size
+      value: 1
+    - name: Bytes256
+      description: 256 bytes CRAM page size
+      value: 2
+    - name: Bytes512
+      description: 512 bytes CRAM page size
+      value: 3
+    - name: Bytes1024
+      description: 1024 bytes CRAM page size
+      value: 4
+enum/ECCPS:
+  bit_size: 3
+  variants:
+    - name: Bytes256
+      description: ECC page size 256 bytes
+      value: 0
+    - name: Bytes512
+      description: ECC page size 512 bytes
+      value: 1
+    - name: Bytes1024
+      description: ECC page size 1024 bytes
+      value: 2
+    - name: Bytes2048
+      description: ECC page size 2048 bytes
+      value: 3
+    - name: Bytes4096
+      description: ECC page size 4096 bytes
+      value: 4
+    - name: Bytes8192
+      description: ECC page size 8192 bytes
+      value: 5
+enum/MTYP:
+  bit_size: 2
+  variants:
+    - name: SRAM
+      description: SRAM memory type
+      value: 0
+    - name: PSRAM
+      description: PSRAM (CRAM) memory type
+      value: 1
+    - name: Flash
+      description: NOR Flash/OneNAND Flash
+      value: 2
+enum/MWID:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: Memory data bus width 8 bits
+      value: 0
+    - name: Bits16
+      description: Memory data bus width 16 bits
+      value: 1
+    - name: Bits32
+      description: Memory data bus width 32 bits
+      value: 2
+enum/PTYP:
+  bit_size: 1
+  variants:
+    - name: NANDFlash
+      description: NAND Flash
+      value: 1
+enum/PWID:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: External memory device width 8 bits
+      value: 0
+    - name: Bits16
+      description: External memory device width 16 bits
+      value: 1
+enum/WAITCFG:
+  bit_size: 1
+  variants:
+    - name: BeforeWaitState
+      description: NWAIT signal is active one data cycle before wait state
+      value: 0
+    - name: DuringWaitState
+      description: NWAIT signal is active during wait state
+      value: 1
+enum/WAITPOL:
+  bit_size: 1
+  variants:
+    - name: ActiveLow
+      description: NWAIT active low
+      value: 0
+    - name: ActiveHigh
+      description: NWAIT active high
+      value: 1

data/registers/fsmc_v4x1.yaml

@@ -0,0 +1,519 @@
+# stm32u5
+---
+block/FMC:
+  description: Flexible memory controller
+  items:
+    - name: BCR1
+      description: SRAM/NOR-Flash chip-select control register 1
+      byte_offset: 0
+      fieldset: BCR1
+    - name: BCR
+      description: SRAM/NOR-Flash chip-select control register 2-4
+      array:
+        len: 3
+        stride: 8
+      byte_offset: 8
+      fieldset: BCR
+    - name: BTR
+      description: SRAM/NOR-Flash chip-select timing register 1-4
+      array:
+        len: 4
+        stride: 8
+      byte_offset: 4
+      fieldset: BTR
+    - name: PCSCNTR
+      description: PSRAM chip select counter register
+      byte_offset: 32
+      fieldset: PCSCNTR
+    - name: BWTR
+      description: SRAM/NOR-Flash write timing registers 1-4
+      array:
+        len: 4
+        stride: 8
+      byte_offset: 260
+      fieldset: BWTR
+    - name: PCR
+      description: PC Card/NAND Flash control register
+      byte_offset: 128
+      fieldset: PCR
+    - name: SR
+      description: FIFO status and interrupt register
+      byte_offset: 132
+      fieldset: SR
+    - name: PMEM
+      description: Common memory space timing register
+      byte_offset: 136
+      fieldset: PMEM
+    - name: PATT
+      description: Attribute memory space timing register
+      byte_offset: 140
+      fieldset: PATT
+    - name: ECCR
+      description: ECC result register
+      byte_offset: 148
+      access: Read
+      fieldset: ECCR
+fieldset/BCR1:
+  description: SRAM/NOR-Flash chip-select control register 1
+  fields:
+    - name: MBKEN
+      description: Memory bank enable bit
+      bit_offset: 0
+      bit_size: 1
+    - name: MUXEN
+      description: Address/data multiplexing enable bit
+      bit_offset: 1
+      bit_size: 1
+    - name: MTYP
+      description: Memory type
+      bit_offset: 2
+      bit_size: 2
+      enum: MTYP
+    - name: MWID
+      description: Memory data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: MWID
+    - name: FACCEN
+      description: Flash access enable
+      bit_offset: 6
+      bit_size: 1
+    - name: BURSTEN
+      description: Burst enable bit
+      bit_offset: 8
+      bit_size: 1
+    - name: WAITPOL
+      description: Wait signal polarity bit
+      bit_offset: 9
+      bit_size: 1
+      enum: WAITPOL
+    - name: WAITCFG
+      description: Wait timing configuration
+      bit_offset: 11
+      bit_size: 1
+      enum: WAITCFG
+    - name: WREN
+      description: Write enable bit
+      bit_offset: 12
+      bit_size: 1
+    - name: WAITEN
+      description: Wait enable bit
+      bit_offset: 13
+      bit_size: 1
+    - name: EXTMOD
+      description: Extended mode enable
+      bit_offset: 14
+      bit_size: 1
+    - name: ASYNCWAIT
+      description: Wait signal during asynchronous transfers
+      bit_offset: 15
+      bit_size: 1
+    - name: CPSIZE
+      description: CRAM page size
+      bit_offset: 16
+      bit_size: 3
+      enum: CPSIZE
+    - name: CBURSTRW
+      description: Write burst enable
+      bit_offset: 19
+      bit_size: 1
+    - name: CCLKEN
+      description: Continuous clock enable
+      bit_offset: 20
+      bit_size: 1
+    - name: WFDIS
+      description: Write FIFO disable
+      bit_offset: 21
+      bit_size: 1
+    - name: NBLSET
+      description: Byte lane (NBL) setup
+      bit_offset: 22
+      bit_size: 2
+    - name: FMCEN
+      description: FMC controller enable
+      bit_offset: 31
+      bit_size: 1
+fieldset/BCR:
+  description: SRAM/NOR-Flash chip-select control register 2-4
+  fields:
+    - name: MBKEN
+      description: Memory bank enable bit
+      bit_offset: 0
+      bit_size: 1
+    - name: MUXEN
+      description: Address/data multiplexing enable bit
+      bit_offset: 1
+      bit_size: 1
+    - name: MTYP
+      description: Memory type
+      bit_offset: 2
+      bit_size: 2
+      enum: MTYP
+    - name: MWID
+      description: Memory data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: MWID
+    - name: FACCEN
+      description: Flash access enable
+      bit_offset: 6
+      bit_size: 1
+    - name: BURSTEN
+      description: Burst enable bit
+      bit_offset: 8
+      bit_size: 1
+    - name: WAITPOL
+      description: Wait signal polarity bit
+      bit_offset: 9
+      bit_size: 1
+      enum: WAITPOL
+    - name: WAITCFG
+      description: Wait timing configuration
+      bit_offset: 11
+      bit_size: 1
+      enum: WAITCFG
+    - name: WREN
+      description: Write enable bit
+      bit_offset: 12
+      bit_size: 1
+    - name: WAITEN
+      description: Wait enable bit
+      bit_offset: 13
+      bit_size: 1
+    - name: EXTMOD
+      description: Extended mode enable
+      bit_offset: 14
+      bit_size: 1
+    - name: ASYNCWAIT
+      description: Wait signal during asynchronous transfers
+      bit_offset: 15
+      bit_size: 1
+    - name: CPSIZE
+      description: CRAM page size
+      bit_offset: 16
+      bit_size: 3
+      enum: CPSIZE
+    - name: CBURSTRW
+      description: Write burst enable
+      bit_offset: 19
+      bit_size: 1
+    - name: NBLSET
+      description: Byte lane (NBL) setup
+      bit_offset: 22
+      bit_size: 2
+    - name: FMCEN
+      description: FMC controller enable
+      bit_offset: 31
+      bit_size: 1
+fieldset/BTR:
+  description: SRAM/NOR-Flash chip-select timing register
+  fields:
+    - name: ADDSET
+      description: Address setup phase duration
+      bit_offset: 0
+      bit_size: 4
+    - name: ADDHLD
+      description: Address-hold phase duration
+      bit_offset: 4
+      bit_size: 4
+    - name: DATAST
+      description: Data-phase duration
+      bit_offset: 8
+      bit_size: 8
+    - name: BUSTURN
+      description: Bus turnaround phase duration
+      bit_offset: 16
+      bit_size: 4
+    - name: CLKDIV
+      description: Clock divide ratio (for FMC_CLK signal)
+      bit_offset: 20
+      bit_size: 4
+    - name: DATLAT
+      description: Data latency for synchronous memory
+      bit_offset: 24
+      bit_size: 4
+    - name: ACCMOD
+      description: Access mode
+      bit_offset: 28
+      bit_size: 2
+      enum: ACCMOD
+    - name: DATAHLD
+      description: Data hold phase duration
+      bit_offset: 30
+      bit_size: 2
+fieldset/PCSCNTR:
+  description: PSRAM chip select counter register
+  fields:
+    - name: CSCOUNT
+      description: Chip select counter
+      bit_offset: 0
+      bit_size: 16
+    - name: CNTB1EN
+      description: Counter Bank 1 enable
+      bit_offset: 16
+      bit_size: 1
+    - name: CNTB2EN
+      description: Counter Bank 2 enable
+      bit_offset: 17
+      bit_size: 1
+    - name: CNTB3EN
+      description: Counter Bank 3 enable
+      bit_offset: 18
+      bit_size: 1
+    - name: CNTB4EN
+      description: Counter Bank 4 enable
+      bit_offset: 19
+      bit_size: 1
+fieldset/BWTR:
+  description: SRAM/NOR-Flash write timing registers
+  fields:
+    - name: ADDSET
+      description: Address setup phase duration
+      bit_offset: 0
+      bit_size: 4
+    - name: ADDHLD
+      description: Address-hold phase duration
+      bit_offset: 4
+      bit_size: 4
+    - name: DATAST
+      description: Data-phase duration
+      bit_offset: 8
+      bit_size: 8
+    - name: BUSTURN
+      description: Bus turnaround phase duration
+      bit_offset: 16
+      bit_size: 4
+    - name: ACCMOD
+      description: Access mode
+      bit_offset: 28
+      bit_size: 2
+      enum: ACCMOD
+    - name: DATAHLD
+      description: Data hold phase duration
+      bit_offset: 30
+      bit_size: 2
+fieldset/PCR:
+  description: PC Card/NAND Flash control register
+  fields:
+    - name: PWAITEN
+      description: Wait feature enable bit
+      bit_offset: 1
+      bit_size: 1
+    - name: PBKEN
+      description: NAND Flash memory bank enable bit
+      bit_offset: 2
+      bit_size: 1
+    - name: PTYP
+      description: Memory type
+      bit_offset: 3
+      bit_size: 1
+      enum: PTYP
+    - name: PWID
+      description: Data bus width
+      bit_offset: 4
+      bit_size: 2
+      enum: PWID
+    - name: ECCEN
+      description: ECC computation logic enable bit
+      bit_offset: 6
+      bit_size: 1
+    - name: TCLR
+      description: CLE to RE delay
+      bit_offset: 9
+      bit_size: 4
+    - name: TAR
+      description: ALE to RE delay
+      bit_offset: 13
+      bit_size: 4
+    - name: ECCPS
+      description: ECC page size
+      bit_offset: 17
+      bit_size: 3
+      enum: ECCPS
+fieldset/SR:
+  description: FIFO status and interrupt register
+  fields:
+    - name: IRS
+      description: Interrupt rising edge status
+      bit_offset: 0
+      bit_size: 1
+    - name: ILS
+      description: Interrupt high-level status
+      bit_offset: 1
+      bit_size: 1
+    - name: IFS
+      description: Interrupt falling edge status
+      bit_offset: 2
+      bit_size: 1
+    - name: IREN
+      description: Interrupt rising edge detection enable bit
+      bit_offset: 3
+      bit_size: 1
+    - name: ILEN
+      description: Interrupt high-level detection enable bit
+      bit_offset: 4
+      bit_size: 1
+    - name: IFEN
+      description: Interrupt falling edge detection enable bit
+      bit_offset: 5
+      bit_size: 1
+    - name: FEMPT
+      description: FIFO empty status
+      bit_offset: 6
+      bit_size: 1
+fieldset/PMEM:
+  description: Common memory space timing register
+  fields:
+    - name: MEMSET
+      description: Common memory x setup time
+      bit_offset: 0
+      bit_size: 8
+    - name: MEMWAIT
+      description: Common memory wait time
+      bit_offset: 8
+      bit_size: 8
+    - name: MEMHOLD
+      description: Common memory hold time
+      bit_offset: 16
+      bit_size: 8
+    - name: MEMHIZ
+      description: Common memory x data bus Hi-Z time
+      bit_offset: 24
+      bit_size: 8
+fieldset/PATT:
+  description: Attribute memory space timing register
+  fields:
+    - name: ATTSET
+      description: Attribute memory setup time
+      bit_offset: 0
+      bit_size: 8
+    - name: ATTWAIT
+      description: Attribute memory wait time
+      bit_offset: 8
+      bit_size: 8
+    - name: ATTHOLD
+      description: Attribute memory hold time
+      bit_offset: 16
+      bit_size: 8
+    - name: ATTHIZ
+      description: Attribute memory data bus Hi-Z time
+      bit_offset: 24
+      bit_size: 8
+fieldset/ECCR:
+  description: ECC result register
+  fields:
+    - name: ECC
+      description: ECC computation result value
+      bit_offset: 0
+      bit_size: 32
+enum/ACCMOD:
+  bit_size: 2
+  variants:
+    - name: A
+      description: Access mode A
+      value: 0
+    - name: B
+      description: Access mode B
+      value: 1
+    - name: C
+      description: Access mode C
+      value: 2
+    - name: D
+      description: Access mode D
+      value: 3
+enum/CPSIZE:
+  bit_size: 3
+  variants:
+    - name: NoBurstSplit
+      description: No burst split when crossing page boundary
+      value: 0
+    - name: Bytes128
+      description: 128 bytes CRAM page size
+      value: 1
+    - name: Bytes256
+      description: 256 bytes CRAM page size
+      value: 2
+    - name: Bytes512
+      description: 512 bytes CRAM page size
+      value: 3
+    - name: Bytes1024
+      description: 1024 bytes CRAM page size
+      value: 4
+enum/ECCPS:
+  bit_size: 3
+  variants:
+    - name: Bytes256
+      description: ECC page size 256 bytes
+      value: 0
+    - name: Bytes512
+      description: ECC page size 512 bytes
+      value: 1
+    - name: Bytes1024
+      description: ECC page size 1024 bytes
+      value: 2
+    - name: Bytes2048
+      description: ECC page size 2048 bytes
+      value: 3
+    - name: Bytes4096
+      description: ECC page size 4096 bytes
+      value: 4
+    - name: Bytes8192
+      description: ECC page size 8192 bytes
+      value: 5
+enum/MTYP:
+  bit_size: 2
+  variants:
+    - name: SRAM
+      description: SRAM memory type
+      value: 0
+    - name: PSRAM
+      description: PSRAM (CRAM) memory type
+      value: 1
+    - name: Flash
+      description: NOR Flash/OneNAND Flash
+      value: 2
+enum/MWID:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: Memory data bus width 8 bits
+      value: 0
+    - name: Bits16
+      description: Memory data bus width 16 bits
+      value: 1
+    - name: Bits32
+      description: Memory data bus width 32 bits
+      value: 2
+enum/PTYP:
+  bit_size: 1
+  variants:
+    - name: NANDFlash
+      description: NAND Flash
+      value: 1
+enum/PWID:
+  bit_size: 2
+  variants:
+    - name: Bits8
+      description: External memory device width 8 bits
+      value: 0
+    - name: Bits16
+      description: External memory device width 16 bits
+      value: 1
+enum/WAITCFG:
+  bit_size: 1
+  variants:
+    - name: BeforeWaitState
+      description: NWAIT signal is active one data cycle before wait state
+      value: 0
+    - name: DuringWaitState
+      description: NWAIT signal is active during wait state
+      value: 1
+enum/WAITPOL:
+  bit_size: 1
+  variants:
+    - name: ActiveLow
+      description: NWAIT active low
+      value: 0
+    - name: ActiveHigh
+      description: NWAIT active high
+      value: 1