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Use arrays and blocks for everything in EXTI

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This commit is contained in:
Dominik Boehi 2021-06-21 17:47:55 +02:00
parent 481e607977
commit 51395f941a
2 changed files with 101 additions and 437 deletions
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434
data/registers/exti_wb55.yaml
View File

@ -2,300 +2,91 @@
block/EXTI:
description: External interrupt/event controller
items:
- name: RTSR1
- name: RTSR
description: rising trigger selection register
byte_offset: 0
fieldset: RTSR1
- name: FTSR1
fieldset: RTSR
array:
len: 2
stride: 32
- name: FTSR
description: falling trigger selection register
byte_offset: 4
fieldset: FTSR1
- name: SWIER1
fieldset: FTSR
array:
len: 2
stride: 32
- name: SWIER
description: software interrupt event register
byte_offset: 8
fieldset: SWIER1
- name: PR1
fieldset: SWIER
array:
len: 2
stride: 32
- name: PR
description: EXTI pending register
byte_offset: 12
fieldset: PR1
- name: RTSR2
description: rising trigger selection register
byte_offset: 32
fieldset: RTSR2
- name: FTSR2
description: falling trigger selection register
byte_offset: 36
fieldset: FTSR2
- name: SWIER2
description: software interrupt event register
byte_offset: 40
fieldset: SWIER2
- name: PR2
description: pending register
byte_offset: 44
fieldset: PR2
- name: C1IMR1
description: CPUm wakeup with interrupt mask register
byte_offset: 128
fieldset: C1IMR1
- name: C1EMR1
description: CPUm wakeup with event mask register
byte_offset: 132
fieldset: C1EMR1
- name: C1IMR2
description: CPUm wakeup with interrupt mask register
byte_offset: 144
fieldset: C1IMR2
- name: C1EMR2
description: CPUm wakeup with event mask register
byte_offset: 148
fieldset: C1EMR2
- name: C2IMR1
description: CPUm wakeup with interrupt mask register
byte_offset: 192
fieldset: C2IMR1
- name: C2EMR1
description: CPUm wakeup with event mask register
byte_offset: 196
fieldset: C2EMR1
- name: C2IMR2
description: CPUm wakeup with interrupt mask register
byte_offset: 208
fieldset: C2IMR2
- name: C2EMR2
description: CPUm wakeup with event mask register
byte_offset: 212
fieldset: C2EMR2
- name: HWCFGR7
description: EXTI Hardware configuration registers
byte_offset: 984
access: Read
fieldset: HWCFGR7
- name: HWCFGR6
description: Hardware configuration registers
byte_offset: 988
access: Read
fieldset: HWCFGR6
- name: HWCFGR5
description: Hardware configuration registers
byte_offset: 992
access: Read
fieldset: HWCFGR5
- name: HWCFGR4
description: Hardware configuration registers
byte_offset: 996
access: Read
fieldset: HWCFGR4
- name: HWCFGR3
description: Hardware configuration registers
byte_offset: 1000
access: Read
fieldset: HWCFGR3
- name: HWCFGR2
description: Hardware configuration registers
byte_offset: 1004
access: Read
fieldset: HWCFGR2
- name: HWCFGR1
description: Hardware configuration register 1
byte_offset: 1008
access: Read
fieldset: HWCFGR1
- name: VERR
description: EXTI IP Version register
byte_offset: 1012
access: Read
fieldset: VERR
- name: IPIDR
description: Identification register
byte_offset: 1016
access: Read
fieldset: IPIDR
- name: SIDR
description: Size ID register
byte_offset: 1020
access: Read
fieldset: SIDR
fieldset/C1EMR1:
description: CPUm wakeup with event mask register
fields:
- name: EM0_15
description: CPU(m) Wakeup with event generation Mask on Event input
bit_offset: 0
bit_size: 16
- name: EM17_21
description: CPU(m) Wakeup with event generation Mask on Event input
bit_offset: 17
bit_size: 5
fieldset/C1EMR2:
description: CPUm wakeup with event mask register
fields:
- name: EM
description: CPU(m) Wakeup with event generation Mask on Event input
bit_offset: 8
bit_size: 2
fieldset/C1IMR1:
description: CPUm wakeup with interrupt mask register
fields:
- name: IM
description: CPU(m) wakeup with interrupt Mask on Event input
bit_offset: 0
bit_size: 1
array:
len: 32
stride: 1
enum: MR
fieldset/C1IMR2:
description: CPUm wakeup with interrupt mask register
fields:
- name: IM
description: CPUm Wakeup with interrupt Mask on Event input
bit_offset: 0
bit_size: 1
array:
len: 17
stride: 1
enum: MR
fieldset/C2EMR1:
description: CPUm wakeup with event mask register
fields:
- name: EM0_15
description: CPU(m) Wakeup with event generation Mask on Event input
bit_offset: 0
bit_size: 16
- name: EM17_21
description: CPU(m) Wakeup with event generation Mask on Event input
bit_offset: 17
bit_size: 5
fieldset/C2EMR2:
description: CPUm wakeup with event mask register
fields:
- name: EM
description: CPU(m) Wakeup with event generation Mask on Event input
bit_offset: 8
bit_size: 2
fieldset/C2IMR1:
description: CPUm wakeup with interrupt mask register
fields:
- name: IM
description: CPU(m) wakeup with interrupt Mask on Event input
bit_offset: 0
bit_size: 1
array:
len: 32
stride: 1
enum: MR
fieldset/C2IMR2:
description: CPUm wakeup with interrupt mask register
fields:
- name: IM
description: CPUm Wakeup with interrupt Mask on Event input
bit_offset: 0
bit_size: 1
array:
len: 17
stride: 1
enum: MR
fieldset/FTSR1:
description: falling trigger selection register
fields:
- name: FT
description: Falling trigger event configuration bit of Configurable Event input
bit_offset: 0
bit_size: 1
array:
len: 22
stride: 1
enum: FT
- name: FT_31
description: Falling trigger event configuration bit of Configurable Event input
bit_offset: 31
bit_size: 1
enum: FT
fieldset/FTSR2:
description: falling trigger selection register
fields:
- name: FT
description: Falling trigger event configuration bit of Configurable Event input
bit_offset: 1
bit_size: 1
array:
len: 1
stride: 0
enum: FT
- name: FT40_41
description: Falling trigger event configuration bit of Configurable Event input
bit_offset: 8
bit_size: 1
fieldset: PR
array:
len: 2
stride: 32
- name: CPU
description: CPU specific registers
byte_offset: 128
block: CPU_MASK
array:
len: 2
stride: 64
block/CPU_MASK:
description: CPU-specific mask registers
items:
- name: IMR
description: CPUm wakeup with interrupt mask register
byte_offset: 0
fieldset: C1IMR
array:
len: 2
stride: 16
- name: EMR
description: CPUm wakeup with event mask register
byte_offset: 4
fieldset: C1EMR
array:
len: 2
stride: 16
fieldset/C1EMR:
description: CPUm wakeup with event mask register
fields:
- name: EM
description: CPU(m) Wakeup with event generation Mask on Event input
bit_offset: 0
bit_size: 16
array:
len: 32
stride: 1
fieldset/C1IMR:
description: CPUm wakeup with interrupt mask register
fields:
- name: IM
description: CPU(m) wakeup with interrupt Mask on Event input
bit_offset: 0
bit_size: 1
array:
len: 32
stride: 1
enum: MR
fieldset/FTSR:
description: falling trigger selection register
fields:
- name: FT
description: Falling trigger event configuration bit of Configurable Event input
bit_offset: 0
bit_size: 1
array:
len: 32
stride: 1
enum: FT
fieldset/HWCFGR1:
description: Hardware configuration register 1
fields:
- name: NBEVENTS
description: HW configuration number of event
bit_offset: 0
bit_size: 8
- name: NBCPUS
description: HW configuration number of CPUs
bit_offset: 8
bit_size: 4
- name: CPUEVTEN
description: HW configuration of CPU(m) event output enable
bit_offset: 12
bit_size: 4
fieldset/HWCFGR2:
description: Hardware configuration registers
fields:
- name: EVENT_TRG
description: HW configuration event trigger type
bit_offset: 0
bit_size: 32
fieldset/HWCFGR3:
description: Hardware configuration registers
fields:
- name: EVENT_TRG
description: HW configuration event trigger type
bit_offset: 0
bit_size: 32
fieldset/HWCFGR4:
description: Hardware configuration registers
fields:
- name: EVENT_TRG
description: HW configuration event trigger type
bit_offset: 0
bit_size: 32
fieldset/HWCFGR5:
description: Hardware configuration registers
fields:
- name: CPUEVENT
description: HW configuration CPU event generation
bit_offset: 0
bit_size: 32
fieldset/HWCFGR6:
description: Hardware configuration registers
fields:
- name: CPUEVENT
description: HW configuration CPU event generation
bit_offset: 0
bit_size: 32
fieldset/HWCFGR7:
description: EXTI Hardware configuration registers
fields:
- name: CPUEVENT
description: HW configuration CPU event generation
bit_offset: 0
bit_size: 32
fieldset/IPIDR:
description: Identification register
fields:
- name: IPID
description: IP Identification
bit_offset: 0
bit_size: 32
fieldset/PR1:
fieldset/PR:
description: EXTI pending register
fields:
- name: PIF
@ -303,98 +94,31 @@ fieldset/PR1:
bit_offset: 0
bit_size: 1
array:
len: 22
len: 32
stride: 1
enum_read: PRR
enum_write: PRW
- name: PIF_31
description: Configurable event inputs Pending bit
bit_offset: 31
bit_size: 1
enum_read: PRR
enum_write: PRW
fieldset/PR2:
description: pending register
fields:
- name: PIF
description: Configurable event inputs x+32 Pending bit.
bit_offset: 1
bit_size: 1
enum_read: PRR
enum_write: PRW
- name: PIF40_41
description: Configurable event inputs x+32 Pending bit.
bit_offset: 8
bit_size: 1
array:
len: 2
stride: 1
enum_read: PRR
enum_write: PRW
fieldset/RTSR1:
fieldset/RTSR:
description: rising trigger selection register
fields:
- name: RT
description: Rising trigger event configuration bit of Configurable Event input
bit_offset: 0
bit_size: 22
array:
len: 22
stride: 1
enum: RT
- name: RT_31
description: Rising trigger event configuration bit of Configurable Event input
bit_offset: 31
bit_size: 1
enum: RT
fieldset/RTSR2:
description: rising trigger selection register
fields:
- name: RT
description: Rising trigger event configuration bit of Configurable Event input
bit_offset: 1
bit_size: 1
enum: RT
- name: RT40_41
description: Rising trigger event configuration bit of Configurable Event input
bit_offset: 8
bit_size: 1
array:
len: 2
len: 32
stride: 1
enum: RT
fieldset/SIDR:
description: Size ID register
fields:
- name: SID
description: Size Identification
bit_offset: 0
bit_size: 32
fieldset/SWIER1:
fieldset/SWIER:
description: software interrupt event register
fields:
- name: SWI
description: Software interrupt on event
bit_offset: 0
bit_size: 22
- name: SWI_31
description: Software interrupt on event
bit_offset: 31
bit_size: 1
fieldset/SWIER2:
description: software interrupt event register
fields:
- name: SWI
description: Software interrupt on event
bit_offset: 1
bit_size: 1
array:
len: 1
stride: 0
- name: SWI40_41
description: Software interrupt on event
bit_offset: 8
bit_size: 2
len: 32
stride: 1
fieldset/VERR:
description: EXTI IP Version register
fields:

92
data/registers/ipcc_v1.yaml
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@ -2,62 +2,34 @@
block/IPCC:
description: IPCC
items:
- name: C1CR
description: Control register CPU1
- name: CPU
description: CPU specific registers
byte_offset: 0
array:
len: 2
stride: 16
block/IPCC_CPU:
description: IPCC
items:
- name: CR
description: Control register CPUx
byte_offset: 0
fieldset: C1CR
- name: C1MR
description: Mask register CPU1
- name: MR
description: Mask register CPUx
byte_offset: 4
fieldset: C1MR
- name: C1SCR
- name: SCR
description: Status Set or Clear register CPU1
byte_offset: 8
access: Write
fieldset: C1SCR
- name: C1TO2SR
- name: SR
description: CPU1 to CPU2 status register
byte_offset: 12
access: Read
fieldset: C1TO2SR
- name: C2CR
description: Control register CPU2
byte_offset: 16
fieldset: C2CR
- name: C2MR
description: Mask register CPU2
byte_offset: 20
fieldset: C2MR
- name: C2SCR
description: Status Set or Clear register CPU2
byte_offset: 24
access: Write
fieldset: C2SCR
- name: C2TOC1SR
description: CPU2 to CPU1 status register
byte_offset: 28
access: Read
fieldset: C2TOC1SR
- name: HWCFGR
description: IPCC Hardware configuration register
byte_offset: 1008
access: Read
fieldset: HWCFGR
- name: VERR
description: IPCC version register
byte_offset: 1012
access: Read
fieldset: VERR
- name: IPIDR
description: IPCC indentification register
byte_offset: 1016
access: Read
fieldset: IPIDR
- name: SIDR
description: IPCC size indentification register
byte_offset: 1020
access: Read
fieldset: SIDR
fieldset/C1CR:
description: Control register CPU1
fields:
@ -168,35 +140,3 @@ fieldset/C2TOC1SR:
array:
len: 6
stride: 1
fieldset/HWCFGR:
description: IPCC Hardware configuration register
fields:
- name: CHANNELS
description: "Number of channels per CPU supported by the IP, range 1 to 16"
bit_offset: 0
bit_size: 8
fieldset/IPIDR:
description: IPCC indentification register
fields:
- name: IPID
description: Identification Code
bit_offset: 0
bit_size: 32
fieldset/SIDR:
description: IPCC size indentification register
fields:
- name: SID
description: Size Identification Code
bit_offset: 0
bit_size: 32
fieldset/VERR:
description: IPCC version register
fields:
- name: MINREV
description: Minor Revision
bit_offset: 0
bit_size: 4
- name: MAJREV
description: Major Revision
bit_offset: 4
bit_size: 4