Merge pull request #150 from chemicstry/iwdg_v1

Add IWDG v1 definitions

data/registers/iwdg_v1.yaml

@@ -0,0 +1,95 @@
+---
+block/IWDG:
+  description: Independent watchdog
+  items:
+    - name: KR
+      description: Key register
+      byte_offset: 0
+      access: Write
+      fieldset: KR
+    - name: PR
+      description: Prescaler register
+      byte_offset: 4
+      fieldset: PR
+    - name: RLR
+      description: Reload register
+      byte_offset: 8
+      fieldset: RLR
+    - name: SR
+      description: Status register
+      byte_offset: 12
+      access: Read
+      fieldset: SR
+fieldset/KR:
+  description: Key register
+  fields:
+    - name: KEY
+      description: "Key value (write only, read 0000h)"
+      bit_offset: 0
+      bit_size: 16
+      enum: KEY
+fieldset/PR:
+  description: Prescaler register
+  fields:
+    - name: PR
+      description: Prescaler divider
+      bit_offset: 0
+      bit_size: 3
+      enum: PR
+fieldset/RLR:
+  description: Reload register
+  fields:
+    - name: RL
+      description: Watchdog counter reload value
+      bit_offset: 0
+      bit_size: 12
+fieldset/SR:
+  description: Status register
+  fields:
+    - name: PVU
+      description: Watchdog prescaler value update
+      bit_offset: 0
+      bit_size: 1
+    - name: RVU
+      description: Watchdog counter reload value update
+      bit_offset: 1
+      bit_size: 1
+enum/KEY:
+  bit_size: 16
+  variants:
+    - name: Enable
+      description: "Enable access to PR, RLR and WINR registers (0x5555)"
+      value: 21845
+    - name: Reset
+      description: Reset the watchdog value (0xAAAA)
+      value: 43690
+    - name: Start
+      description: Start the watchdog (0xCCCC)
+      value: 52428
+enum/PR:
+  bit_size: 3
+  variants:
+    - name: DivideBy4
+      description: Divider /4
+      value: 0
+    - name: DivideBy8
+      description: Divider /8
+      value: 1
+    - name: DivideBy16
+      description: Divider /16
+      value: 2
+    - name: DivideBy32
+      description: Divider /32
+      value: 3
+    - name: DivideBy64
+      description: Divider /64
+      value: 4
+    - name: DivideBy128
+      description: Divider /128
+      value: 5
+    - name: DivideBy256
+      description: Divider /256
+      value: 6
+    - name: DivideBy256bis
+      description: Divider /256
+      value: 7

stm32data/__main__.py

@@ -155,6 +155,7 @@ perimap = [
     ('STM32WL5.*:SYSCFG:.*', ('syscfg', 'wl5', 'SYSCFG')),
     ('STM32WLE.*:SYSCFG:.*', ('syscfg', 'wle', 'SYSCFG')),
 
+    ('.*:IWDG:iwdg1_v1_1', ('iwdg', 'v1', 'IWDG')),
     ('.*:IWDG:iwdg1_v2_0', ('iwdg', 'v2', 'IWDG')),
     ('.*:WWDG:wwdg1_v1_0', ('wwdg', 'v1', 'WWDG')),
     ('.*:JPEG:jpeg1_v1_0', ('jpeg', 'v1', 'JPEG')),