From 4ddcb77c9d213d11eebb048f40e112bc54163cdc Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Mon, 23 Oct 2023 00:27:35 +0200 Subject: [PATCH] rcc: rename NONE -> DISABLED --- data/registers/rcc_h5.yaml | 2 +- data/registers/rcc_h50.yaml | 2 +- data/registers/rcc_h7.yaml | 2 +- data/registers/rcc_h7ab.yaml | 2 +- data/registers/rcc_h7rm0433.yaml | 2 +- data/registers/rcc_l4.yaml | 2 +- data/registers/rcc_l4plus.yaml | 2 +- data/registers/rcc_l5.yaml | 4 ++-- data/registers/rcc_u5.yaml | 4 ++-- data/registers/rcc_wba.yaml | 2 +- 10 files changed, 12 insertions(+), 12 deletions(-) diff --git a/data/registers/rcc_h5.yaml b/data/registers/rcc_h5.yaml index 72193c9..3ddf959 100644 --- a/data/registers/rcc_h5.yaml +++ b/data/registers/rcc_h5.yaml @@ -3868,7 +3868,7 @@ enum/PLLRGE: enum/PLLSRC: bit_size: 2 variants: - - name: None + - name: DISABLE description: no clock send to DIVMx divider and PLLs (default after reset) value: 0 - name: HSI diff --git a/data/registers/rcc_h50.yaml b/data/registers/rcc_h50.yaml index 859f9c1..1376225 100644 --- a/data/registers/rcc_h50.yaml +++ b/data/registers/rcc_h50.yaml @@ -3036,7 +3036,7 @@ enum/PLLRGE: enum/PLLSRC: bit_size: 2 variants: - - name: None + - name: DISABLE description: no clock send to DIVMx divider and PLLs (default after reset) value: 0 - name: HSI diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index 2f45aef..32a408d 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -5251,7 +5251,7 @@ enum/PLLSRC: - name: HSE description: HSE selected as PLL clock value: 2 - - name: None + - name: DISABLE description: No clock sent to DIVMx dividers and PLLs value: 3 enum/PLLVCOSEL: diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml index c1956c5..a074b3b 100644 --- a/data/registers/rcc_h7ab.yaml +++ b/data/registers/rcc_h7ab.yaml @@ -4186,7 +4186,7 @@ enum/PLLSRC: - name: HSE description: HSE selected as PLL clock value: 2 - - name: None + - name: DISABLE description: No clock sent to DIVMx dividers and PLLs value: 3 enum/PLLVCOSEL: diff --git a/data/registers/rcc_h7rm0433.yaml b/data/registers/rcc_h7rm0433.yaml index 0c88ad0..352e67b 100644 --- a/data/registers/rcc_h7rm0433.yaml +++ b/data/registers/rcc_h7rm0433.yaml @@ -5251,7 +5251,7 @@ enum/PLLSRC: - name: HSE description: HSE selected as PLL clock value: 2 - - name: None + - name: DISABLE description: No clock sent to DIVMx dividers and PLLs value: 3 enum/PLLVCOSEL: diff --git a/data/registers/rcc_l4.yaml b/data/registers/rcc_l4.yaml index 35a5001..70018d1 100644 --- a/data/registers/rcc_l4.yaml +++ b/data/registers/rcc_l4.yaml @@ -2171,7 +2171,7 @@ enum/PLLR: enum/PLLSRC: bit_size: 2 variants: - - name: None + - name: DISABLE description: No clock sent to PLL value: 0 - name: MSI diff --git a/data/registers/rcc_l4plus.yaml b/data/registers/rcc_l4plus.yaml index 80f7fec..c5f829e 100644 --- a/data/registers/rcc_l4plus.yaml +++ b/data/registers/rcc_l4plus.yaml @@ -2347,7 +2347,7 @@ enum/PLLR: enum/PLLSRC: bit_size: 2 variants: - - name: None + - name: DISABLE description: No clock sent to PLL value: 0 - name: MSI diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml index 8f7e0ab..2933f71 100644 --- a/data/registers/rcc_l5.yaml +++ b/data/registers/rcc_l5.yaml @@ -2014,7 +2014,7 @@ enum/MCOPRE: enum/MCOSEL: bit_size: 4 variants: - - name: None + - name: DISABLE description: MCO output disabled, no clock on MCO value: 0 - name: SYS @@ -2462,7 +2462,7 @@ enum/PLLR: enum/PLLSRC: bit_size: 2 variants: - - name: None + - name: DISABLE description: No clock sent to PLL value: 0 - name: MSI diff --git a/data/registers/rcc_u5.yaml b/data/registers/rcc_u5.yaml index 9fb13e8..7af2222 100644 --- a/data/registers/rcc_u5.yaml +++ b/data/registers/rcc_u5.yaml @@ -2825,10 +2825,10 @@ enum/MSIRANGE: enum/MSIRGSEL: bit_size: 1 variants: - - name: RCC_CSR + - name: CSR description: MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR value: 0 - - name: RCC_ICSCR1 + - name: ICSCR1 description: MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1 value: 1 enum/MSIXSRANGE: diff --git a/data/registers/rcc_wba.yaml b/data/registers/rcc_wba.yaml index 66479d2..a31a1e6 100644 --- a/data/registers/rcc_wba.yaml +++ b/data/registers/rcc_wba.yaml @@ -1471,7 +1471,7 @@ enum/PPRE: enum/RADIOSTSEL: bit_size: 2 variants: - - name: None + - name: DISABLE description: no clock selected, 2.4 GHz RADIO sleep timer kernel clock disabled value: 0 - name: LSE