From c3548f2b7a4278aef91b3fbf50dfe5ca77208fdd Mon Sep 17 00:00:00 2001 From: xoviat Date: Thu, 14 Sep 2023 17:10:04 -0500 Subject: [PATCH 1/4] add pwr l0 --- data/registers/pwr_l0.yaml | 257 ++++++++++++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 1 + 2 files changed, 258 insertions(+) create mode 100644 data/registers/pwr_l0.yaml diff --git a/data/registers/pwr_l0.yaml b/data/registers/pwr_l0.yaml new file mode 100644 index 0000000..c3afb3d --- /dev/null +++ b/data/registers/pwr_l0.yaml @@ -0,0 +1,257 @@ +--- +block/PWR: + description: Power control + items: + - name: CR + description: power control register + byte_offset: 0 + fieldset: CR + - name: CSR + description: power control/status register + byte_offset: 4 + fieldset: CSR +fieldset/CR: + description: power control register + fields: + - name: LPSDSR + description: Low-power deepsleep/Sleep/Low-power run + bit_offset: 0 + bit_size: 1 + enum: LPSDSR + - name: PDDS + description: Power down deepsleep + bit_offset: 1 + bit_size: 1 + enum: PDDS + - name: CWUF + description: Clear wakeup flag + bit_offset: 2 + bit_size: 1 + - name: CSBF + description: Clear standby flag + bit_offset: 3 + bit_size: 1 + - name: PVDE + description: Power voltage detector enable + bit_offset: 4 + bit_size: 1 + - name: PLS + description: PVD level selection + bit_offset: 5 + bit_size: 3 + enum: PLS + - name: DBP + description: Disable backup domain write protection + bit_offset: 8 + bit_size: 1 + - name: ULP + description: Ultra-low-power mode + bit_offset: 9 + bit_size: 1 + - name: FWU + description: Fast wakeup + bit_offset: 10 + bit_size: 1 + - name: VOS + description: Voltage scaling range selection + bit_offset: 11 + bit_size: 2 + enum: VOS + - name: DS_EE_KOFF + description: Deep sleep mode with Flash memory kept off + bit_offset: 13 + bit_size: 1 + enum: DS_EE_KOFF + - name: LPRUN + description: Low power run mode + bit_offset: 14 + bit_size: 1 + enum: LPRUN + - name: LPDS + description: Regulator in Low-power deepsleep mode + bit_offset: 16 + bit_size: 1 + enum: LPDS +fieldset/CSR: + description: power control/status register + fields: + - name: WUF + description: Wakeup flag + bit_offset: 0 + bit_size: 1 + enum_read: WUFR + - name: SBF + description: Standby flag + bit_offset: 1 + bit_size: 1 + enum_read: SBFR + - name: PVDO + description: PVD output + bit_offset: 2 + bit_size: 1 + enum_read: PVDOR + - name: VREFINTRDYF + description: Internal voltage reference ready flag + bit_offset: 3 + bit_size: 1 + enum_read: VREFINTRDYFR + - name: VOSF + description: Voltage Scaling select flag + bit_offset: 4 + bit_size: 1 + enum_read: VOSFR + - name: REGLPF + description: Regulator LP flag + bit_offset: 5 + bit_size: 1 + enum_read: REGLPFR + - name: EWUP1 + description: Enable WKUP pin 1 + bit_offset: 8 + bit_size: 1 + - name: EWUP2 + description: Enable WKUP pin 2 + bit_offset: 9 + bit_size: 1 + - name: EWUP3 + description: Enable WKUP pin 3 + bit_offset: 10 + bit_size: 1 +enum/DS_EE_KOFF: + bit_size: 1 + variants: + - name: NVMWakeUp + description: NVM woken up when exiting from Deepsleep mode even if the bit RUN_PD is set + value: 0 + - name: NVMSleep + description: NVM not woken up when exiting from low-power mode (if the bit RUN_PD is set) + value: 1 +enum/LPDS: + bit_size: 1 + variants: + - name: MAIN_MODE + description: Voltage regulator in Main mode during Deepsleep mode (Stop mode) + value: 0 + - name: LOW_POWER_MODE + description: Voltage regulator switches to low-power mode when the CPU enters Deepsleep mode (Stop mode) + value: 1 +enum/LPRUN: + bit_size: 1 + variants: + - name: MAIN_MODE + description: Voltage regulator in Main mode in Low-power run mode + value: 0 + - name: LOW_POWER_MODE + description: Voltage regulator in low-power mode in Low-power run mode + value: 1 +enum/LPSDSR: + bit_size: 1 + variants: + - name: MAIN_MODE + description: Voltage regulator on during Deepsleep/Sleep/Low-power run mode + value: 0 + - name: LOW_POWER_MODE + description: Voltage regulator in low-power mode during Deepsleep/Sleep/Low-power run mode + value: 1 +enum/PDDS: + bit_size: 1 + variants: + - name: STOP_MODE + description: Enter Stop mode when the CPU enters deepsleep + value: 0 + - name: STANDBY_MODE + description: Enter Standby mode when the CPU enters deepsleep + value: 1 +enum/PLS: + bit_size: 3 + variants: + - name: V1_9 + description: 1.9 V + value: 0 + - name: V2_1 + description: 2.1 V + value: 1 + - name: V2_3 + description: 2.3 V + value: 2 + - name: V2_5 + description: 2.5 V + value: 3 + - name: V2_7 + description: 2.7 V + value: 4 + - name: V2_9 + description: 2.9 V + value: 5 + - name: V3_1 + description: 3.1 V + value: 6 + - name: External + description: External input analog voltage (Compare internally to VREFINT) + value: 7 +enum/PVDOR: + bit_size: 1 + variants: + - name: AboveThreshold + description: "VDD is higher than the PVD threshold selected with the PLS[2:0] bits" + value: 0 + - name: BelowThreshold + description: "VDD is lower than the PVD threshold selected with the PLS[2:0] bits" + value: 1 +enum/REGLPFR: + bit_size: 1 + variants: + - name: Ready + description: Regulator is ready in Main mode + value: 0 + - name: NotReady + description: Regulator voltage is in low-power mode + value: 1 +enum/SBFR: + bit_size: 1 + variants: + - name: NoStandbyEvent + description: Device has not been in Standby mode + value: 0 + - name: StandbyEvent + description: Device has been in Standby mode + value: 1 +enum/VOS: + bit_size: 2 + variants: + - name: V1_8 + description: 1.8 V (range 1) + value: 1 + - name: V1_5 + description: 1.5 V (range 2) + value: 2 + - name: V1_2 + description: 1.2 V (range 3) + value: 3 +enum/VOSFR: + bit_size: 1 + variants: + - name: Ready + description: Regulator is ready in the selected voltage range + value: 0 + - name: NotReady + description: Regulator voltage output is changing to the required VOS level + value: 1 +enum/VREFINTRDYFR: + bit_size: 1 + variants: + - name: NotReady + description: VREFINT is OFF + value: 0 + - name: Ready + description: VREFINT is ready + value: 1 +enum/WUFR: + bit_size: 1 + variants: + - name: NoWakeupEvent + description: No wakeup event occurred + value: 0 + - name: WakeupEvent + description: "A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup)" + value: 1 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 5ddd3c2..6bb769f 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -330,6 +330,7 @@ impl PeriMatcher { ("STM32F3.*:PWR:.*", ("pwr", "f3", "PWR")), ("STM32F4.*:PWR:.*", ("pwr", "f4", "PWR")), ("STM32F7.*:PWR:.*", ("pwr", "f7", "PWR")), + ("STM32L0.*:PWR:.*", ("pwr", "l0", "PWR")), ("STM32L1.*:PWR:.*", ("pwr", "l1", "PWR")), ("STM32L4.*:PWR:.*", ("pwr", "l4", "PWR")), ("STM32L5.*:PWR:.*", ("pwr", "l5", "PWR")), From 1118eb4c965527760c1031fe305f3d7dc49c06b0 Mon Sep 17 00:00:00 2001 From: xoviat Date: Thu, 14 Sep 2023 17:10:13 -0500 Subject: [PATCH 2/4] cleanup adc common v2 --- data/registers/adccommon_v2.yaml | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/data/registers/adccommon_v2.yaml b/data/registers/adccommon_v2.yaml index 037ade7..5d9a6a7 100644 --- a/data/registers/adccommon_v2.yaml +++ b/data/registers/adccommon_v2.yaml @@ -47,12 +47,10 @@ fieldset/CCR: description: VBAT enable bit_offset: 22 bit_size: 1 - enum: VBATE - name: TSVREFE description: Temperature sensor and VREFINT enable bit_offset: 23 bit_size: 1 - enum: TSVREFE fieldset/CDR: description: ADC common regular data register for dual and triple modes fields: @@ -249,21 +247,3 @@ enum/STRT: - name: Started description: Regular channel conversion has started value: 1 -enum/TSVREFE: - bit_size: 1 - variants: - - name: Disabled - description: Temperature sensor and V_REFINT channel disabled - value: 0 - - name: Enabled - description: Temperature sensor and V_REFINT channel enabled - value: 1 -enum/VBATE: - bit_size: 1 - variants: - - name: Disabled - description: V_BAT channel disabled - value: 0 - - name: Enabled - description: V_BAT channel enabled - value: 1 From 1e9067e0f0e5ff58558dae3be0645c6486f176a9 Mon Sep 17 00:00:00 2001 From: xoviat Date: Thu, 14 Sep 2023 17:32:36 -0500 Subject: [PATCH 3/4] pwr/l0: cleanup enums --- data/registers/pwr_l0.yaml | 30 ++++++------------------------ 1 file changed, 6 insertions(+), 24 deletions(-) diff --git a/data/registers/pwr_l0.yaml b/data/registers/pwr_l0.yaml index c3afb3d..40aaa6b 100644 --- a/data/registers/pwr_l0.yaml +++ b/data/registers/pwr_l0.yaml @@ -17,7 +17,7 @@ fieldset/CR: description: Low-power deepsleep/Sleep/Low-power run bit_offset: 0 bit_size: 1 - enum: LPSDSR + enum: MODE - name: PDDS description: Power down deepsleep bit_offset: 1 @@ -66,12 +66,12 @@ fieldset/CR: description: Low power run mode bit_offset: 14 bit_size: 1 - enum: LPRUN + enum: MODE - name: LPDS description: Regulator in Low-power deepsleep mode bit_offset: 16 bit_size: 1 - enum: LPDS + enum: MODE fieldset/CSR: description: power control/status register fields: @@ -126,32 +126,14 @@ enum/DS_EE_KOFF: - name: NVMSleep description: NVM not woken up when exiting from low-power mode (if the bit RUN_PD is set) value: 1 -enum/LPDS: +enum/MODE: bit_size: 1 variants: - name: MAIN_MODE - description: Voltage regulator in Main mode during Deepsleep mode (Stop mode) + description: Voltage regulator in Main mode value: 0 - name: LOW_POWER_MODE - description: Voltage regulator switches to low-power mode when the CPU enters Deepsleep mode (Stop mode) - value: 1 -enum/LPRUN: - bit_size: 1 - variants: - - name: MAIN_MODE - description: Voltage regulator in Main mode in Low-power run mode - value: 0 - - name: LOW_POWER_MODE - description: Voltage regulator in low-power mode in Low-power run mode - value: 1 -enum/LPSDSR: - bit_size: 1 - variants: - - name: MAIN_MODE - description: Voltage regulator on during Deepsleep/Sleep/Low-power run mode - value: 0 - - name: LOW_POWER_MODE - description: Voltage regulator in low-power mode during Deepsleep/Sleep/Low-power run mode + description: Voltage regulator switches to low-power mode value: 1 enum/PDDS: bit_size: 1 From 2304100192e5b596a515aacb78b501dbb49f8b83 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Fri, 15 Sep 2023 00:47:15 +0200 Subject: [PATCH 4/4] ci: fix diff generation for PRs from forks. --- .github/ci/build.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.github/ci/build.sh b/.github/ci/build.sh index d9e1478..cc57d5e 100755 --- a/.github/ci/build.sh +++ b/.github/ci/build.sh @@ -15,7 +15,9 @@ cargo fmt -- --check # clone stm32-data-generated at the merge base # so the diff will show this PR's effect -git clone --depth 1 --branch stm32-data-$(git merge-base HEAD main) https://github.com/embassy-rs/stm32-data-generated/ build +git remote add upstream https://github.com/embassy-rs/stm32-data +git fetch --depth 1 upstream main +git clone --depth 1 --branch stm32-data-$(git merge-base HEAD upstream/main) https://github.com/embassy-rs/stm32-data-generated/ build ./d ci