From 4a2802facc17807d3c19ca764618512b23b92d97 Mon Sep 17 00:00:00 2001 From: Torin Cooper-Bennun Date: Thu, 22 Feb 2024 10:59:50 +0000 Subject: [PATCH] adc h5: add missing enums --- data/registers/adc_h5.yaml | 89 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/data/registers/adc_h5.yaml b/data/registers/adc_h5.yaml index 5af1121..902bea4 100644 --- a/data/registers/adc_h5.yaml +++ b/data/registers/adc_h5.yaml @@ -140,6 +140,7 @@ fieldset/CFGR: description: 'Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 3 bit_size: 2 + enum: RES - name: EXTSEL description: 'External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).' bit_offset: 5 @@ -151,6 +152,7 @@ fieldset/CFGR: description: 'External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).' bit_offset: 10 bit_size: 2 + enum: EXTEN - name: OVRMOD description: 'Overrun mode This bit is set and cleared by software and configure the way data overrun is managed. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).' bit_offset: 12 @@ -222,6 +224,7 @@ fieldset/CFGR2: description: 'Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 2 bit_size: 3 + enum: OVSR - name: OVSS description: 'Oversampling shift This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result. Other codes reserved Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 5 @@ -457,6 +460,7 @@ fieldset/SMPR1: description: 'Channel 0-9 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.' bit_offset: 0 bit_size: 3 + enum: SAMPLE_TIME array: len: 10 stride: 3 @@ -471,6 +475,7 @@ fieldset/SMPR2: description: 'Channel 10-19 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.' bit_offset: 0 bit_size: 3 + enum: SAMPLE_TIME array: len: 10 stride: 3 @@ -555,3 +560,87 @@ fieldset/TR3: description: 'Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 16 bit_size: 8 +enum/RES: + bit_size: 2 + variants: + - name: TwelveBit + description: 12-bit resolution + value: 0 + - name: TenBit + description: 10-bit resolution + value: 1 + - name: EightBit + description: 8-bit resolution + value: 2 + - name: SixBit + description: 6-bit resolution + value: 3 +enum/EXTEN: + bit_size: 2 + variants: + - name: Disabled + description: Hardware trigger detection disabled (conversions can be launched by software) + value: 0 + - name: RisingEdge + description: Hardware trigger detection on the rising edge + value: 1 + - name: FallingEdge + description: Hardware trigger detection on the falling edge + value: 2 + - name: BothEdges + description: Hardware trigger detection on both the rising and falling edge + value: 3 +enum/OVSR: + bit_size: 3 + variants: + - name: x2 + description: x2 + value: 0 + - name: x4 + description: x4 + value: 1 + - name: x8 + description: x8 + value: 2 + - name: x16 + description: x16 + value: 3 + - name: x32 + description: x32 + value: 4 + - name: x64 + description: x64 + value: 5 + - name: x128 + description: x128 + value: 6 + - name: x256 + description: x256 + value: 7 +enum/SAMPLE_TIME: + bit_size: 3 + variants: + - name: Cycles2_5 + description: 2.5 ADC cycles + value: 0 + - name: Cycles6_5 + description: 6.5 ADC cycles + value: 1 + - name: Cycles12_5 + description: 12.5 ADC cycles + value: 2 + - name: Cycles24_5 + description: 24.5 ADC cycles + value: 3 + - name: Cycles47_5 + description: 47.5 ADC cycles + value: 4 + - name: Cycles92_5 + description: 92.5 ADC cycles + value: 5 + - name: Cycles247_5 + description: 247.5 ADC cycles + value: 6 + - name: Cycles640_5 + description: 640.5 ADC cycles + value: 7