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eZio Pan 2024-02-24 16:46:36 +08:00
parent 68fa1b173a
commit 45f5429068
2 changed files with 125 additions and 543 deletions
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data/registers/fmc_v4.yaml
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@ -5,34 +5,20 @@ block/FMC:
description: SRAM/NOR-Flash chip-select control register for bank 1.
byte_offset: 0
fieldset: BCR1
- name: BTR1
- name: BTR
description: SRAM/NOR-Flash chip-select timing register for bank 1.
array:
len: 4
stride: 8
byte_offset: 4
fieldset: BTR1
- name: BCR2
fieldset: BTR
- name: BCR
description: SRAM/NOR-Flash chip-select control register for bank 2.
array:
len: 3
stride: 8
byte_offset: 8
fieldset: BCR2
- name: BTR2
description: SRAM/NOR-Flash chip-select timing register for bank 2.
byte_offset: 12
fieldset: BTR2
- name: BCR3
description: SRAM/NOR-Flash chip-select control register for bank 3.
byte_offset: 16
fieldset: BCR3
- name: BTR3
description: SRAM/NOR-Flash chip-select timing register for bank 3.
byte_offset: 20
fieldset: BTR3
- name: BCR4
description: SRAM/NOR-Flash chip-select control register for bank 4.
byte_offset: 24
fieldset: BCR4
- name: BTR4
description: SRAM/NOR-Flash chip-select timing register for bank 4.
byte_offset: 28
fieldset: BTR4
fieldset: BCR
- name: PCSCNTR
description: PSRAM chip select counter register.
byte_offset: 32
@ -56,39 +42,27 @@ block/FMC:
- name: ECCR
description: ECC result registers.
byte_offset: 148
fieldset: ECCR
- name: BWTR1
- name: BWTR
description: SRAM/NOR-Flash write timing registers 1.
array:
len: 4
stride: 8
byte_offset: 260
fieldset: BWTR1
- name: BWTR2
description: SRAM/NOR-Flash write timing registers 2.
byte_offset: 268
fieldset: BWTR2
- name: BWTR3
description: SRAM/NOR-Flash write timing registers 3.
byte_offset: 276
fieldset: BWTR3
- name: BWTR4
description: SRAM/NOR-Flash write timing registers 4.
byte_offset: 284
fieldset: BWTR4
- name: SDCR1
fieldset: BWTR
- name: SDCR
description: SDRAM control registers 1.
array:
len: 2
stride: 4
byte_offset: 320
fieldset: SDCR1
- name: SDCR2
description: SDRAM control registers 2.
byte_offset: 324
fieldset: SDCR2
- name: SDTR1
fieldset: SDCR
- name: SDTR
description: SDRAM timing registers 1.
array:
len: 2
stride: 4
byte_offset: 328
fieldset: SDTR1
- name: SDTR2
description: SDRAM timing registers 2.
byte_offset: 332
fieldset: SDTR2
fieldset: SDTR
- name: SDCMR
description: SDRAM Command Mode register.
byte_offset: 336
@ -101,6 +75,81 @@ block/FMC:
description: SDRAM status register.
byte_offset: 344
fieldset: SDSR
fieldset/BCR:
description: SRAM/NOR-Flash chip-select control register for bank 4.
fields:
- name: MBKEN
description: Memory bank enable bit Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus.
bit_offset: 0
bit_size: 1
- name: MUXEN
description: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.
bit_offset: 1
bit_size: 1
- name: MTYP
description: Memory type Defines the type of external memory attached to the corresponding memory bank.
bit_offset: 2
bit_size: 2
- name: MWID
description: Memory data bus width Defines the external memory device width, valid for all type of memories.
bit_offset: 4
bit_size: 2
- name: FACCEN
description: Flash access enable Enables NOR Flash memory access operations.
bit_offset: 6
bit_size: 1
- name: BURSTEN
description: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode.
bit_offset: 8
bit_size: 1
- name: WAITPOL
description: Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode.
bit_offset: 9
bit_size: 1
- name: WAITCFG
description: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.
bit_offset: 11
bit_size: 1
- name: WREN
description: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC.
bit_offset: 12
bit_size: 1
- name: WAITEN
description: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode.
bit_offset: 13
bit_size: 1
- name: EXTMOD
description: 'Extended mode enable This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).'
bit_offset: 14
bit_size: 1
- name: ASYNCWAIT
description: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol.
bit_offset: 15
bit_size: 1
- name: CPSIZE
description: 'CRAM page size These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved.'
bit_offset: 16
bit_size: 3
- name: CBURSTRW
description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register.
bit_offset: 19
bit_size: 1
- name: CCLKEN
description: 'Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).'
bit_offset: 20
bit_size: 1
- name: WFDIS
description: 'Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.'
bit_offset: 21
bit_size: 1
- name: NBLSET
description: Byte lane (NBL) setup These bits configure the NBL setup timing from NBLx low to chip select NEx low.
bit_offset: 22
bit_size: 2
- name: FMCEN
description: 'FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.'
bit_offset: 31
bit_size: 1
fieldset/BCR1:
description: SRAM/NOR-Flash chip-select control register for bank 1.
fields:
@ -176,232 +225,7 @@ fieldset/BCR1:
description: 'FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.'
bit_offset: 31
bit_size: 1
fieldset/BCR2:
description: SRAM/NOR-Flash chip-select control register for bank 2.
fields:
- name: MBKEN
description: Memory bank enable bit Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus.
bit_offset: 0
bit_size: 1
- name: MUXEN
description: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.
bit_offset: 1
bit_size: 1
- name: MTYP
description: Memory type Defines the type of external memory attached to the corresponding memory bank.
bit_offset: 2
bit_size: 2
- name: MWID
description: Memory data bus width Defines the external memory device width, valid for all type of memories.
bit_offset: 4
bit_size: 2
- name: FACCEN
description: Flash access enable Enables NOR Flash memory access operations.
bit_offset: 6
bit_size: 1
- name: BURSTEN
description: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode.
bit_offset: 8
bit_size: 1
- name: WAITPOL
description: Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode.
bit_offset: 9
bit_size: 1
- name: WAITCFG
description: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.
bit_offset: 11
bit_size: 1
- name: WREN
description: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC.
bit_offset: 12
bit_size: 1
- name: WAITEN
description: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode.
bit_offset: 13
bit_size: 1
- name: EXTMOD
description: 'Extended mode enable This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).'
bit_offset: 14
bit_size: 1
- name: ASYNCWAIT
description: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol.
bit_offset: 15
bit_size: 1
- name: CPSIZE
description: 'CRAM page size These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved.'
bit_offset: 16
bit_size: 3
- name: CBURSTRW
description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register.
bit_offset: 19
bit_size: 1
- name: CCLKEN
description: 'Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).'
bit_offset: 20
bit_size: 1
- name: WFDIS
description: 'Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.'
bit_offset: 21
bit_size: 1
- name: NBLSET
description: Byte lane (NBL) setup These bits configure the NBL setup timing from NBLx low to chip select NEx low.
bit_offset: 22
bit_size: 2
- name: FMCEN
description: 'FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.'
bit_offset: 31
bit_size: 1
fieldset/BCR3:
description: SRAM/NOR-Flash chip-select control register for bank 3.
fields:
- name: MBKEN
description: Memory bank enable bit Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus.
bit_offset: 0
bit_size: 1
- name: MUXEN
description: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.
bit_offset: 1
bit_size: 1
- name: MTYP
description: Memory type Defines the type of external memory attached to the corresponding memory bank.
bit_offset: 2
bit_size: 2
- name: MWID
description: Memory data bus width Defines the external memory device width, valid for all type of memories.
bit_offset: 4
bit_size: 2
- name: FACCEN
description: Flash access enable Enables NOR Flash memory access operations.
bit_offset: 6
bit_size: 1
- name: BURSTEN
description: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode.
bit_offset: 8
bit_size: 1
- name: WAITPOL
description: Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode.
bit_offset: 9
bit_size: 1
- name: WAITCFG
description: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.
bit_offset: 11
bit_size: 1
- name: WREN
description: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC.
bit_offset: 12
bit_size: 1
- name: WAITEN
description: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode.
bit_offset: 13
bit_size: 1
- name: EXTMOD
description: 'Extended mode enable This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).'
bit_offset: 14
bit_size: 1
- name: ASYNCWAIT
description: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol.
bit_offset: 15
bit_size: 1
- name: CPSIZE
description: 'CRAM page size These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved.'
bit_offset: 16
bit_size: 3
- name: CBURSTRW
description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register.
bit_offset: 19
bit_size: 1
- name: CCLKEN
description: 'Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).'
bit_offset: 20
bit_size: 1
- name: WFDIS
description: 'Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.'
bit_offset: 21
bit_size: 1
- name: NBLSET
description: Byte lane (NBL) setup These bits configure the NBL setup timing from NBLx low to chip select NEx low.
bit_offset: 22
bit_size: 2
- name: FMCEN
description: 'FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.'
bit_offset: 31
bit_size: 1
fieldset/BCR4:
description: SRAM/NOR-Flash chip-select control register for bank 4.
fields:
- name: MBKEN
description: Memory bank enable bit Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus.
bit_offset: 0
bit_size: 1
- name: MUXEN
description: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.
bit_offset: 1
bit_size: 1
- name: MTYP
description: Memory type Defines the type of external memory attached to the corresponding memory bank.
bit_offset: 2
bit_size: 2
- name: MWID
description: Memory data bus width Defines the external memory device width, valid for all type of memories.
bit_offset: 4
bit_size: 2
- name: FACCEN
description: Flash access enable Enables NOR Flash memory access operations.
bit_offset: 6
bit_size: 1
- name: BURSTEN
description: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode.
bit_offset: 8
bit_size: 1
- name: WAITPOL
description: Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode.
bit_offset: 9
bit_size: 1
- name: WAITCFG
description: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.
bit_offset: 11
bit_size: 1
- name: WREN
description: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC.
bit_offset: 12
bit_size: 1
- name: WAITEN
description: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode.
bit_offset: 13
bit_size: 1
- name: EXTMOD
description: 'Extended mode enable This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).'
bit_offset: 14
bit_size: 1
- name: ASYNCWAIT
description: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol.
bit_offset: 15
bit_size: 1
- name: CPSIZE
description: 'CRAM page size These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved.'
bit_offset: 16
bit_size: 3
- name: CBURSTRW
description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register.
bit_offset: 19
bit_size: 1
- name: CCLKEN
description: 'Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).'
bit_offset: 20
bit_size: 1
- name: WFDIS
description: 'Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.'
bit_offset: 21
bit_size: 1
- name: NBLSET
description: Byte lane (NBL) setup These bits configure the NBL setup timing from NBLx low to chip select NEx low.
bit_offset: 22
bit_size: 2
- name: FMCEN
description: 'FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.'
bit_offset: 31
bit_size: 1
fieldset/BTR1:
fieldset/BTR:
description: SRAM/NOR-Flash chip-select timing register for bank 1.
fields:
- name: ADDSET
@ -436,112 +260,7 @@ fieldset/BTR1:
description: 'Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: For read accesses For write accesses.'
bit_offset: 30
bit_size: 2
fieldset/BTR2:
description: SRAM/NOR-Flash chip-select timing register for bank 2.
fields:
- name: ADDSET
description: 'Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure 21 to Figure 33), used in SRAMs, ROMs, asynchronous NOR Flash and PSRAM: ... For each access mode address setup phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is don’t care. Note: In Muxed mode or mode D, the minimum value for ADDSET is 1. Note: In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.'
bit_offset: 0
bit_size: 4
- name: ADDHLD
description: 'Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 21 to Figure 33), used in mode D or multiplexed accesses: ... For each access mode address-hold phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.'
bit_offset: 4
bit_size: 4
- name: DATAST
description: 'Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... For each memory type and access mode data-phase duration, refer to the respective figure (Figure 21 to Figure 33). Example: Mode 1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock cycles. Note: In synchronous accesses, this value is don’t care.'
bit_offset: 8
bit_size: 8
- name: BUSTURN
description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current read or write transaction to next transaction on the same bank. This delay allows to match the minimum time between consecutive transactions (t<sub>EHEL</sub> from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (t<sub>EHQZ</sub>, chip enable high to output Hi-Z). This delay is recommended for mode D and muxed mode. For non-muxed memory, the bus turnaround delay can be set to minimum value. (BUSTURN + 1)HCLK period ≥ max(t<sub>EHEL</sub> min, t<sub>EHQZ</sub> max) For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read) to match the tPC memory timing. The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ t<sub>PC</sub> min ...
bit_offset: 16
bit_size: 4
- name: CLKDIV
description: 'Clock divide ratio (for FMC_CLK signal) Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care. Note: Refer to Section 5.6.5: Synchronous transactions for FMC_CLK divider ratio formula).'
bit_offset: 20
bit_size: 4
- name: DATLAT
description: '(see note below bit descriptions): Data latency for synchronous memory For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods. For asynchronous access, this value is don''t care.'
bit_offset: 24
bit_size: 4
- name: ACCMOD
description: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
bit_offset: 28
bit_size: 2
- name: DATAHLD
description: 'Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: For read accesses For write accesses.'
bit_offset: 30
bit_size: 2
fieldset/BTR3:
description: SRAM/NOR-Flash chip-select timing register for bank 3.
fields:
- name: ADDSET
description: 'Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure 21 to Figure 33), used in SRAMs, ROMs, asynchronous NOR Flash and PSRAM: ... For each access mode address setup phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is don’t care. Note: In Muxed mode or mode D, the minimum value for ADDSET is 1. Note: In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.'
bit_offset: 0
bit_size: 4
- name: ADDHLD
description: 'Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 21 to Figure 33), used in mode D or multiplexed accesses: ... For each access mode address-hold phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.'
bit_offset: 4
bit_size: 4
- name: DATAST
description: 'Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... For each memory type and access mode data-phase duration, refer to the respective figure (Figure 21 to Figure 33). Example: Mode 1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock cycles. Note: In synchronous accesses, this value is don’t care.'
bit_offset: 8
bit_size: 8
- name: BUSTURN
description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current read or write transaction to next transaction on the same bank. This delay allows to match the minimum time between consecutive transactions (t<sub>EHEL</sub> from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (t<sub>EHQZ</sub>, chip enable high to output Hi-Z). This delay is recommended for mode D and muxed mode. For non-muxed memory, the bus turnaround delay can be set to minimum value. (BUSTURN + 1)HCLK period ≥ max(t<sub>EHEL</sub> min, t<sub>EHQZ</sub> max) For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read) to match the tPC memory timing. The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ t<sub>PC</sub> min ...
bit_offset: 16
bit_size: 4
- name: CLKDIV
description: 'Clock divide ratio (for FMC_CLK signal) Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care. Note: Refer to Section 5.6.5: Synchronous transactions for FMC_CLK divider ratio formula).'
bit_offset: 20
bit_size: 4
- name: DATLAT
description: '(see note below bit descriptions): Data latency for synchronous memory For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods. For asynchronous access, this value is don''t care.'
bit_offset: 24
bit_size: 4
- name: ACCMOD
description: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
bit_offset: 28
bit_size: 2
- name: DATAHLD
description: 'Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: For read accesses For write accesses.'
bit_offset: 30
bit_size: 2
fieldset/BTR4:
description: SRAM/NOR-Flash chip-select timing register for bank 4.
fields:
- name: ADDSET
description: 'Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure 21 to Figure 33), used in SRAMs, ROMs, asynchronous NOR Flash and PSRAM: ... For each access mode address setup phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is don’t care. Note: In Muxed mode or mode D, the minimum value for ADDSET is 1. Note: In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.'
bit_offset: 0
bit_size: 4
- name: ADDHLD
description: 'Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 21 to Figure 33), used in mode D or multiplexed accesses: ... For each access mode address-hold phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.'
bit_offset: 4
bit_size: 4
- name: DATAST
description: 'Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... For each memory type and access mode data-phase duration, refer to the respective figure (Figure 21 to Figure 33). Example: Mode 1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock cycles. Note: In synchronous accesses, this value is don’t care.'
bit_offset: 8
bit_size: 8
- name: BUSTURN
description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current read or write transaction to next transaction on the same bank. This delay allows to match the minimum time between consecutive transactions (t<sub>EHEL</sub> from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (t<sub>EHQZ</sub>, chip enable high to output Hi-Z). This delay is recommended for mode D and muxed mode. For non-muxed memory, the bus turnaround delay can be set to minimum value. (BUSTURN + 1)HCLK period ≥ max(t<sub>EHEL</sub> min, t<sub>EHQZ</sub> max) For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read) to match the tPC memory timing. The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ t<sub>PC</sub> min ...
bit_offset: 16
bit_size: 4
- name: CLKDIV
description: 'Clock divide ratio (for FMC_CLK signal) Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care. Note: Refer to Section 5.6.5: Synchronous transactions for FMC_CLK divider ratio formula).'
bit_offset: 20
bit_size: 4
- name: DATLAT
description: '(see note below bit descriptions): Data latency for synchronous memory For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods. For asynchronous access, this value is don''t care.'
bit_offset: 24
bit_size: 4
- name: ACCMOD
description: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
bit_offset: 28
bit_size: 2
- name: DATAHLD
description: 'Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: For read accesses For write accesses.'
bit_offset: 30
bit_size: 2
fieldset/BWTR1:
fieldset/BWTR:
description: SRAM/NOR-Flash write timing registers 1.
fields:
- name: ADDSET
@ -568,94 +287,6 @@ fieldset/BWTR1:
description: Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous write accesses:.
bit_offset: 30
bit_size: 2
fieldset/BWTR2:
description: SRAM/NOR-Flash write timing registers 2.
fields:
- name: ADDSET
description: 'Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1.'
bit_offset: 0
bit_size: 4
- name: ADDHLD
description: 'Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 30 to Figure 33), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.'
bit_offset: 4
bit_size: 4
- name: DATAST
description: 'Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: ...'
bit_offset: 8
bit_size: 8
- name: BUSTURN
description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current write transaction to next transaction on the same bank. For FRAM memories, the bus turnaround delay should be configured to match the minimum t<sub>PC</sub> (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read). The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ...
bit_offset: 16
bit_size: 4
- name: ACCMOD
description: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
bit_offset: 28
bit_size: 2
- name: DATAHLD
description: Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous write accesses:.
bit_offset: 30
bit_size: 2
fieldset/BWTR3:
description: SRAM/NOR-Flash write timing registers 3.
fields:
- name: ADDSET
description: 'Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1.'
bit_offset: 0
bit_size: 4
- name: ADDHLD
description: 'Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 30 to Figure 33), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.'
bit_offset: 4
bit_size: 4
- name: DATAST
description: 'Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: ...'
bit_offset: 8
bit_size: 8
- name: BUSTURN
description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current write transaction to next transaction on the same bank. For FRAM memories, the bus turnaround delay should be configured to match the minimum t<sub>PC</sub> (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read). The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ...
bit_offset: 16
bit_size: 4
- name: ACCMOD
description: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
bit_offset: 28
bit_size: 2
- name: DATAHLD
description: Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous write accesses:.
bit_offset: 30
bit_size: 2
fieldset/BWTR4:
description: SRAM/NOR-Flash write timing registers 4.
fields:
- name: ADDSET
description: 'Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1.'
bit_offset: 0
bit_size: 4
- name: ADDHLD
description: 'Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 30 to Figure 33), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.'
bit_offset: 4
bit_size: 4
- name: DATAST
description: 'Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: ...'
bit_offset: 8
bit_size: 8
- name: BUSTURN
description: Bus turnaround phase duration These bits are written by software to add a delay at the end of current write transaction to next transaction on the same bank. For FRAM memories, the bus turnaround delay should be configured to match the minimum t<sub>PC</sub> (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read). The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min ...
bit_offset: 16
bit_size: 4
- name: ACCMOD
description: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
bit_offset: 28
bit_size: 2
- name: DATAHLD
description: Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous write accesses:.
bit_offset: 30
bit_size: 2
fieldset/ECCR:
description: ECC result registers.
fields:
- name: ECC
description: ECC result This field contains the value computed by the ECC computation logic. Table 99 describes the contents of these bitfields.
bit_offset: 0
bit_size: 32
fieldset/PATT:
description: Attribute memory space timing register.
fields:
@ -779,7 +410,7 @@ fieldset/SDCMR:
description: Mode Register definition This 13-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command.
bit_offset: 9
bit_size: 13
fieldset/SDCR1:
fieldset/SDCR:
description: SDRAM control registers 1.
fields:
- name: NC
@ -818,45 +449,6 @@ fieldset/SDCR1:
description: 'Read pipe These bits define the delay, in clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only.'
bit_offset: 13
bit_size: 2
fieldset/SDCR2:
description: SDRAM control registers 2.
fields:
- name: NC
description: Number of column address bits These bits define the number of bits of a column address.
bit_offset: 0
bit_size: 2
- name: NR
description: Number of row address bits These bits define the number of bits of a row address.
bit_offset: 2
bit_size: 2
- name: MWID
description: Memory data bus width. These bits define the memory device width.
bit_offset: 4
bit_size: 2
- name: NB
description: Number of internal banks This bit sets the number of internal banks.
bit_offset: 6
bit_size: 1
- name: CAS
description: CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles.
bit_offset: 7
bit_size: 2
- name: WP
description: Write protection This bit enables write mode access to the SDRAM bank.
bit_offset: 9
bit_size: 1
- name: SDCLK
description: 'SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register are don’t care.'
bit_offset: 10
bit_size: 2
- name: RBURST
description: 'Burst read This bit enables Burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is don’t care.'
bit_offset: 12
bit_size: 1
- name: RPIPE
description: 'Read pipe These bits define the delay, in clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only.'
bit_offset: 13
bit_size: 2
fieldset/SDRTR:
description: SDRAM refresh timer register.
fields:
@ -891,7 +483,7 @@ fieldset/SDSR:
description: Busy status This bit defines the status of the SDRAM controller after a Command Mode request 1; SDRAM Controller is not ready to accept a new request.
bit_offset: 5
bit_size: 1
fieldset/SDTR1:
fieldset/SDTR:
description: SDRAM timing registers 1.
fields:
- name: TMRD
@ -922,37 +514,6 @@ fieldset/SDTR1:
description: Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. ....
bit_offset: 24
bit_size: 4
fieldset/SDTR2:
description: SDRAM timing registers 2.
fields:
- name: TMRD
description: Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. ....
bit_offset: 0
bit_size: 4
- name: TXSR
description: 'Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. .... Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device.'
bit_offset: 4
bit_size: 4
- name: TRAS
description: Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. ....
bit_offset: 8
bit_size: 4
- name: TRC
description: 'Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. .... Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are don’t care.'
bit_offset: 12
bit_size: 4
- name: TWR
description: 'Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. .... Note: TWR must be programmed to match the write recovery time (t<sub>WR</sub>) defined in the SDRAM datasheet, and to guarantee that: Note: TWR ≥ TRAS - TRCD and TWR ≥TRC - TRCD - TRP Note: Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be programmed to 0x1. Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device. Note: If only one SDRAM device is used, the TWR timing must be kept at reset value (0xF) for the not used bank.'
bit_offset: 16
bit_size: 4
- name: TRP
description: 'Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. .... Note: The corresponding bits in the FMC_SDTR2 register are don’t care.'
bit_offset: 20
bit_size: 4
- name: TRCD
description: Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. ....
bit_offset: 24
bit_size: 4
fieldset/SR:
description: FIFO status and interrupt register.
fields:

21
transforms/FMC.yaml Normal file
View File

@ -0,0 +1,21 @@
transforms:
- !DeleteFieldsets
from: ^ECCR$
- !MergeFieldsets
from: ^(BCR)[2-4]$
to: $1
- !MergeFieldsets
from: ^(BTR|BWTR|SDCR|SDTR)\d+$
to: $1
- !MakeRegisterArray
blocks: FMC
from: ^(BCR)[2-4]$
to: $1
- !MakeRegisterArray
blocks: FMC
from: ^(BTR|BWTR|SDCR|SDTR)\d+$
to: $1