diff --git a/data/registers/rcc_c0.yaml b/data/registers/rcc_c0.yaml
index 555f289..8424e47 100644
--- a/data/registers/rcc_c0.yaml
+++ b/data/registers/rcc_c0.yaml
@@ -472,24 +472,24 @@ fieldset/CR:
     bit_size: 3
     enum: SYSDIV
   - name: HSIKERDIV
-    description: "HSI48 kernel clock division factor\r This bitfield controlled by software sets the division factor of the kernel clock divider to produce HSIKER clock:"
+    description: "HSI kernel clock division factor\r This bitfield controlled by software sets the division factor of the kernel clock divider to produce HSIKER clock:"
     bit_offset: 5
     bit_size: 3
     enum: HSIKERDIV
   - name: HSION
-    description: "HSI48 clock enable\r Set and cleared by software and hardware, with hardware taking priority.\r Kept low by hardware as long as the device is in a low-power mode.\r Kept high by hardware as long as the system is clocked with a clock derived from HSI48. This includes the exit from low-power modes and the system clock fall-back to HSI48 upon failing HSE oscillator clock selected as system clock source."
+    description: "HSI clock enable\r Set and cleared by software and hardware, with hardware taking priority.\r Kept low by hardware as long as the device is in a low-power mode.\r Kept high by hardware as long as the system is clocked with a clock derived from HSI. This includes the exit from low-power modes and the system clock fall-back to HSI upon failing HSE oscillator clock selected as system clock source."
     bit_offset: 8
     bit_size: 1
   - name: HSIKERON
-    description: "HSI48 always-enable for peripheral kernels.\r Set and cleared by software.\r Setting the bit activates the HSI48 oscillator in Run and Stop modes, regardless of the HSION bit state. The HSI48 clock can only feed USART1, USART2, and I2C1 peripherals configured with HSI48 as kernel clock.\r Note: Keeping the HSI48 active in Stop mode allows speeding up the serial interface communication as the HSI48 clock is ready immediately upon exiting Stop mode."
+    description: "HSI always-enable for peripheral kernels.\r Set and cleared by software.\r Setting the bit activates the HSI oscillator in Run and Stop modes, regardless of the HSION bit state. The HSI clock can only feed USART1, USART2, and I2C1 peripherals configured with HSI as kernel clock.\r Note: Keeping the HSI active in Stop mode allows speeding up the serial interface communication as the HSI clock is ready immediately upon exiting Stop mode."
     bit_offset: 9
     bit_size: 1
   - name: HSIRDY
-    description: "HSI48 clock ready flag\r Set by hardware when the HSI48 oscillator is enabled through HSION and ready to use (stable).\r Note: Upon clearing HSION, HSIRDY goes low after six HSI48 clock cycles."
+    description: "HSI clock ready flag\r Set by hardware when the HSI oscillator is enabled through HSION and ready to use (stable).\r Note: Upon clearing HSION, HSIRDY goes low after six HSI clock cycles."
     bit_offset: 10
     bit_size: 1
   - name: HSIDIV
-    description: "HSI48 clock division factor\r This bitfield controlled by software sets the division factor of the HSI48 clock divider to produce HSISYS clock:"
+    description: "HSI clock division factor\r This bitfield controlled by software sets the division factor of the HSI clock divider to produce HSISYS clock:"
     bit_offset: 11
     bit_size: 3
     enum: HSIDIV
@@ -675,11 +675,11 @@ fieldset/ICSCR:
   description: RCC internal clock source calibration register
   fields:
   - name: HSICAL
-    description: "HSI48 clock calibration\r This bitfield directly acts on the HSI48 clock frequency. Its value is a sum of an internal factory-programmed number and the value of the HSITRIM[6:0] bitfield. In the factory, the internal number is set to calibrate the HSI48 clock frequency to 48 MHz (with HSITRIM[6:0] left at its reset value). Refer to the device datasheet for HSI48 calibration accuracy and for the frequency trimming granularity.\r Note: The trimming effect presents discontinuities at HSICAL[7:0] multiples of 64."
+    description: "HSI clock calibration\r This bitfield directly acts on the HSI clock frequency. Its value is a sum of an internal factory-programmed number and the value of the HSITRIM[6:0] bitfield. In the factory, the internal number is set to calibrate the HSI clock frequency to 48 MHz (with HSITRIM[6:0] left at its reset value). Refer to the device datasheet for HSI calibration accuracy and for the frequency trimming granularity.\r Note: The trimming effect presents discontinuities at HSICAL[7:0] multiples of 64."
     bit_offset: 0
     bit_size: 8
   - name: HSITRIM
-    description: "HSI48 clock trimming\r The value of this bitfield contributes to the HSICAL[7:0] bitfield value.\r It allows HSI48 clock frequency user trimming.\r The HSI48 frequency accuracy as stated in the device datasheet applies when this bitfield is left at its reset value."
+    description: "HSI clock trimming\r The value of this bitfield contributes to the HSICAL[7:0] bitfield value.\r It allows HSI clock frequency user trimming.\r The HSI frequency accuracy as stated in the device datasheet applies when this bitfield is left at its reset value."
     bit_offset: 8
     bit_size: 7
 enum/ADCSEL:
@@ -859,8 +859,8 @@ enum/MCOSEL:
   - name: SYS
     description: SYSCLK selected as MCO source
     value: 1
-  - name: HSI48
-    description: HSI48 selected as MCO source
+  - name: HSI
+    description: HSI selected as MCO source
     value: 3
   - name: HSE
     description: HSE selected as MCO source