first working state with bad sorting
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2865a53446
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@ -68,7 +68,7 @@ pub struct ChipGroup {
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chip_names: Vec<String>,
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chip_names: Vec<String>,
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xml: xml::Mcu,
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xml: xml::Mcu,
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ips: HashMap<String, xml::Ip>,
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ips: HashMap<String, xml::Ip>,
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pins: HashMap<stm32_data_serde::chip::core::peripheral::pin::Pin, xml::Pin>,
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pins: HashMap<String, xml::Pin>,
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family: Option<String>,
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family: Option<String>,
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line: Option<String>,
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line: Option<String>,
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die: Option<String>,
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die: Option<String>,
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@ -480,18 +480,20 @@ fn merge_periph_pins_info(
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}
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}
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// covert to hashmap
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// covert to hashmap
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let af_pins: HashMap<(stm32_data_serde::chip::core::peripheral::pin::Pin, &str), Option<u8>> =
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let af_pins: HashMap<(&str, &str), Option<u8>> = af_pins
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af_pins.iter().map(|v| ((v.pin, v.signal.as_str()), v.af)).collect();
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.iter()
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.map(|v| ((v.pin.as_str(), v.signal.as_str()), v.af))
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.collect();
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for pin in core_pins {
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for pin in core_pins {
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let af = af_pins.get(&(pin.pin, &pin.signal)).copied().flatten();
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let af = af_pins.get(&(&pin.pin, &pin.signal)).copied().flatten();
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// try to look for a signal with another name
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// try to look for a signal with another name
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let af = af.or_else(|| {
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let af = af.or_else(|| {
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if pin.signal == "CTS" {
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if pin.signal == "CTS" {
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// for some godforsaken reason UART4's and UART5's CTS are called CTS_NSS in the GPIO xml
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// for some godforsaken reason UART4's and UART5's CTS are called CTS_NSS in the GPIO xml
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// so try to match with these
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// so try to match with these
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af_pins.get(&(pin.pin, "CTS_NSS")).copied().flatten()
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af_pins.get(&(pin.pin.as_str(), "CTS_NSS")).copied().flatten()
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} else if periph_name == "I2C1" {
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} else if periph_name == "I2C1" {
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// it appears that for __some__ STM32 MCUs there is no AFIO specified in GPIO file
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// it appears that for __some__ STM32 MCUs there is no AFIO specified in GPIO file
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// (notably - STM32F030C6 with it's I2C1 on PF6 and PF7)
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// (notably - STM32F030C6 with it's I2C1 on PF6 and PF7)
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@ -887,7 +889,7 @@ fn process_core(
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if let Some(signal) = signal.strip_prefix(&format!("{periph}_")) {
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if let Some(signal) = signal.strip_prefix(&format!("{periph}_")) {
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periph_pins.entry(periph.to_string()).or_default().push(
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periph_pins.entry(periph.to_string()).or_default().push(
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stm32_data_serde::chip::core::peripheral::Pin {
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stm32_data_serde::chip::core::peripheral::Pin {
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pin: *pin_name,
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pin: pin_name.clone(),
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signal: signal.to_string(),
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signal: signal.to_string(),
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af: None,
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af: None,
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},
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},
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@ -975,7 +977,7 @@ fn process_core(
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}
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}
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p.pins.extend(i2s_pins.iter().map(|p| Pin {
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p.pins.extend(i2s_pins.iter().map(|p| Pin {
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pin: p.pin,
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pin: p.pin.clone(),
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signal: "I2S_".to_owned() + &p.signal,
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signal: "I2S_".to_owned() + &p.signal,
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af: p.af,
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af: p.af,
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}));
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}));
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@ -38,16 +38,9 @@ mod xml {
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}
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}
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}
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}
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pub fn clean_pin(pin_name: &str) -> Option<stm32_data_serde::chip::core::peripheral::pin::Pin> {
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pub fn clean_pin(pin_name: &str) -> Option<String> {
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// some H7s have analog-only pins like PC2_C, PC3_C. Ignore these for now since the
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// Some H7 chips have additonal "_C" pins.
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// data model can't deal with pins that are not part of a GPIO port yet.
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Some(regex!(r"^P[A-Z]\d+(?:_C)?").find(pin_name)?.as_str().into())
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if regex!(r"^P[A-Z]\d+_C$").is_match(pin_name) {
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return None;
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}
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let pin_name = regex!(r"^P[A-Z]\d+").find(pin_name)?.as_str();
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stm32_data_serde::chip::core::peripheral::pin::Pin::parse(pin_name)
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}
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}
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#[derive(Debug, PartialEq, Eq)]
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#[derive(Debug, PartialEq, Eq)]
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@ -87,7 +80,7 @@ impl Af {
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};
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};
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peris.entry(peri_name.to_string()).or_default().push(
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peris.entry(peri_name.to_string()).or_default().push(
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stm32_data_serde::chip::core::peripheral::Pin {
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stm32_data_serde::chip::core::peripheral::Pin {
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pin: pin_name,
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pin: pin_name.clone(),
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signal: signal_name.to_string(),
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signal: signal_name.to_string(),
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af: afn,
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af: afn,
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},
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},
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@ -123,77 +123,12 @@ pub mod chip {
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#[derive(Clone, Debug, Eq, PartialEq, Hash, PartialOrd, Ord, Serialize, Deserialize)]
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#[derive(Clone, Debug, Eq, PartialEq, Hash, PartialOrd, Ord, Serialize, Deserialize)]
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pub struct Pin {
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pub struct Pin {
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pub pin: pin::Pin,
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pub pin: String,
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pub signal: String,
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pub signal: String,
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#[serde(skip_serializing_if = "Option::is_none")]
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#[serde(skip_serializing_if = "Option::is_none")]
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pub af: Option<u8>,
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pub af: Option<u8>,
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}
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}
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pub mod pin {
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use serde::{Deserialize, Serialize};
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#[derive(Clone, Copy, Debug, Eq, PartialEq, Hash, PartialOrd, Ord)]
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pub struct Pin {
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pub port: char,
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pub num: u8,
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}
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impl Pin {
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pub fn parse(pin: &str) -> Option<Self> {
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let mut chars = pin.chars();
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let p = chars.next()?;
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if p != 'P' {
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return None;
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}
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let port = chars.next()?;
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let num = chars.as_str().parse().ok()?;
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Some(Self { port, num })
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}
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}
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impl std::fmt::Display for Pin {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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write!(f, "P{}{}", self.port, self.num)
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}
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}
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impl Serialize for Pin {
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fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
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where
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S: serde::Serializer,
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{
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serializer.serialize_str(&format!("{self}"))
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}
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}
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struct PinVisitor;
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impl<'de> serde::de::Visitor<'de> for PinVisitor {
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type Value = Pin;
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fn expecting(&self, formatter: &mut std::fmt::Formatter) -> std::fmt::Result {
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formatter.write_str("pin")
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}
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fn visit_str<E>(self, v: &str) -> Result<Self::Value, E>
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where
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E: serde::de::Error,
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{
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Ok(Pin::parse(v).unwrap())
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}
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}
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impl<'de> Deserialize<'de> for Pin {
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fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
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where
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D: serde::Deserializer<'de>,
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{
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deserializer.deserialize_str(PinVisitor)
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}
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}
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}
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#[derive(Clone, Debug, Eq, PartialEq, Hash, PartialOrd, Ord, Serialize, Deserialize)]
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#[derive(Clone, Debug, Eq, PartialEq, Hash, PartialOrd, Ord, Serialize, Deserialize)]
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pub struct Interrupt {
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pub struct Interrupt {
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pub signal: String,
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pub signal: String,
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