first working state with bad sorting

This commit is contained in:
JuliDi 2023-09-13 18:21:16 +02:00
parent 2865a53446
commit 4484603dbd
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GPG Key ID: E1E90AE563D09D63
3 changed files with 14 additions and 84 deletions

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@ -68,7 +68,7 @@ pub struct ChipGroup {
chip_names: Vec<String>, chip_names: Vec<String>,
xml: xml::Mcu, xml: xml::Mcu,
ips: HashMap<String, xml::Ip>, ips: HashMap<String, xml::Ip>,
pins: HashMap<stm32_data_serde::chip::core::peripheral::pin::Pin, xml::Pin>, pins: HashMap<String, xml::Pin>,
family: Option<String>, family: Option<String>,
line: Option<String>, line: Option<String>,
die: Option<String>, die: Option<String>,
@ -480,18 +480,20 @@ fn merge_periph_pins_info(
} }
// covert to hashmap // covert to hashmap
let af_pins: HashMap<(stm32_data_serde::chip::core::peripheral::pin::Pin, &str), Option<u8>> = let af_pins: HashMap<(&str, &str), Option<u8>> = af_pins
af_pins.iter().map(|v| ((v.pin, v.signal.as_str()), v.af)).collect(); .iter()
.map(|v| ((v.pin.as_str(), v.signal.as_str()), v.af))
.collect();
for pin in core_pins { for pin in core_pins {
let af = af_pins.get(&(pin.pin, &pin.signal)).copied().flatten(); let af = af_pins.get(&(&pin.pin, &pin.signal)).copied().flatten();
// try to look for a signal with another name // try to look for a signal with another name
let af = af.or_else(|| { let af = af.or_else(|| {
if pin.signal == "CTS" { if pin.signal == "CTS" {
// for some godforsaken reason UART4's and UART5's CTS are called CTS_NSS in the GPIO xml // for some godforsaken reason UART4's and UART5's CTS are called CTS_NSS in the GPIO xml
// so try to match with these // so try to match with these
af_pins.get(&(pin.pin, "CTS_NSS")).copied().flatten() af_pins.get(&(pin.pin.as_str(), "CTS_NSS")).copied().flatten()
} else if periph_name == "I2C1" { } else if periph_name == "I2C1" {
// it appears that for __some__ STM32 MCUs there is no AFIO specified in GPIO file // it appears that for __some__ STM32 MCUs there is no AFIO specified in GPIO file
// (notably - STM32F030C6 with it's I2C1 on PF6 and PF7) // (notably - STM32F030C6 with it's I2C1 on PF6 and PF7)
@ -887,7 +889,7 @@ fn process_core(
if let Some(signal) = signal.strip_prefix(&format!("{periph}_")) { if let Some(signal) = signal.strip_prefix(&format!("{periph}_")) {
periph_pins.entry(periph.to_string()).or_default().push( periph_pins.entry(periph.to_string()).or_default().push(
stm32_data_serde::chip::core::peripheral::Pin { stm32_data_serde::chip::core::peripheral::Pin {
pin: *pin_name, pin: pin_name.clone(),
signal: signal.to_string(), signal: signal.to_string(),
af: None, af: None,
}, },
@ -975,7 +977,7 @@ fn process_core(
} }
p.pins.extend(i2s_pins.iter().map(|p| Pin { p.pins.extend(i2s_pins.iter().map(|p| Pin {
pin: p.pin, pin: p.pin.clone(),
signal: "I2S_".to_owned() + &p.signal, signal: "I2S_".to_owned() + &p.signal,
af: p.af, af: p.af,
})); }));

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@ -38,16 +38,9 @@ mod xml {
} }
} }
pub fn clean_pin(pin_name: &str) -> Option<stm32_data_serde::chip::core::peripheral::pin::Pin> { pub fn clean_pin(pin_name: &str) -> Option<String> {
// some H7s have analog-only pins like PC2_C, PC3_C. Ignore these for now since the // Some H7 chips have additonal "_C" pins.
// data model can't deal with pins that are not part of a GPIO port yet. Some(regex!(r"^P[A-Z]\d+(?:_C)?").find(pin_name)?.as_str().into())
if regex!(r"^P[A-Z]\d+_C$").is_match(pin_name) {
return None;
}
let pin_name = regex!(r"^P[A-Z]\d+").find(pin_name)?.as_str();
stm32_data_serde::chip::core::peripheral::pin::Pin::parse(pin_name)
} }
#[derive(Debug, PartialEq, Eq)] #[derive(Debug, PartialEq, Eq)]
@ -87,7 +80,7 @@ impl Af {
}; };
peris.entry(peri_name.to_string()).or_default().push( peris.entry(peri_name.to_string()).or_default().push(
stm32_data_serde::chip::core::peripheral::Pin { stm32_data_serde::chip::core::peripheral::Pin {
pin: pin_name, pin: pin_name.clone(),
signal: signal_name.to_string(), signal: signal_name.to_string(),
af: afn, af: afn,
}, },

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@ -123,77 +123,12 @@ pub mod chip {
#[derive(Clone, Debug, Eq, PartialEq, Hash, PartialOrd, Ord, Serialize, Deserialize)] #[derive(Clone, Debug, Eq, PartialEq, Hash, PartialOrd, Ord, Serialize, Deserialize)]
pub struct Pin { pub struct Pin {
pub pin: pin::Pin, pub pin: String,
pub signal: String, pub signal: String,
#[serde(skip_serializing_if = "Option::is_none")] #[serde(skip_serializing_if = "Option::is_none")]
pub af: Option<u8>, pub af: Option<u8>,
} }
pub mod pin {
use serde::{Deserialize, Serialize};
#[derive(Clone, Copy, Debug, Eq, PartialEq, Hash, PartialOrd, Ord)]
pub struct Pin {
pub port: char,
pub num: u8,
}
impl Pin {
pub fn parse(pin: &str) -> Option<Self> {
let mut chars = pin.chars();
let p = chars.next()?;
if p != 'P' {
return None;
}
let port = chars.next()?;
let num = chars.as_str().parse().ok()?;
Some(Self { port, num })
}
}
impl std::fmt::Display for Pin {
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
write!(f, "P{}{}", self.port, self.num)
}
}
impl Serialize for Pin {
fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
where
S: serde::Serializer,
{
serializer.serialize_str(&format!("{self}"))
}
}
struct PinVisitor;
impl<'de> serde::de::Visitor<'de> for PinVisitor {
type Value = Pin;
fn expecting(&self, formatter: &mut std::fmt::Formatter) -> std::fmt::Result {
formatter.write_str("pin")
}
fn visit_str<E>(self, v: &str) -> Result<Self::Value, E>
where
E: serde::de::Error,
{
Ok(Pin::parse(v).unwrap())
}
}
impl<'de> Deserialize<'de> for Pin {
fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
where
D: serde::Deserializer<'de>,
{
deserializer.deserialize_str(PinVisitor)
}
}
}
#[derive(Clone, Debug, Eq, PartialEq, Hash, PartialOrd, Ord, Serialize, Deserialize)] #[derive(Clone, Debug, Eq, PartialEq, Hash, PartialOrd, Ord, Serialize, Deserialize)]
pub struct Interrupt { pub struct Interrupt {
pub signal: String, pub signal: String,