From 435ed7b163c444b7cd623494d827ef41b7f12267 Mon Sep 17 00:00:00 2001 From: Torin Cooper-Bennun Date: Tue, 27 Feb 2024 14:57:06 +0000 Subject: [PATCH] can_fdcan: add enum for tfqm --- data/registers/can_fdcan_h7.yaml | 10 ++++++++++ data/registers/can_fdcan_v1.yaml | 10 ++++++++++ 2 files changed, 20 insertions(+) diff --git a/data/registers/can_fdcan_h7.yaml b/data/registers/can_fdcan_h7.yaml index 1080567..9f332e8 100644 --- a/data/registers/can_fdcan_h7.yaml +++ b/data/registers/can_fdcan_h7.yaml @@ -1608,6 +1608,7 @@ fieldset/TXBC: description: Tx FIFO/Queue Mode bit_offset: 30 bit_size: 1 + enum: TFQM fieldset/TXBCF: description: FDCAN Tx Buffer Cancellation Finished Register fields: @@ -1757,3 +1758,12 @@ fieldset/XIDFC: description: List Size Extended bit_offset: 16 bit_size: 8 +enum/TFQM: + bit_size: 1 + variants: + - name: FIFO + description: Tx FIFO operation + value: 0 + - name: QUEUE + description: Tx queue operation + value: 1 diff --git a/data/registers/can_fdcan_v1.yaml b/data/registers/can_fdcan_v1.yaml index 8ac762d..15ff8d3 100644 --- a/data/registers/can_fdcan_v1.yaml +++ b/data/registers/can_fdcan_v1.yaml @@ -783,6 +783,7 @@ fieldset/TXBC: description: Tx FIFO/queue mode. This is a protected write (P) bit, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1 bit_offset: 24 bit_size: 1 + enum: TFQM fieldset/TXBCF: description: FDCAN Tx buffer cancellation finished register fields: @@ -1073,3 +1074,12 @@ enum/TX: - name: RECESSIVE description: Recessive (1) at pin FDCANx_TX value: 3 +enum/TFQM: + bit_size: 1 + variants: + - name: FIFO + description: Tx FIFO operation + value: 0 + - name: QUEUE + description: Tx queue operation + value: 1