diff --git a/data/registers/rtc_v2.yaml b/data/registers/rtc_v2.yaml
new file mode 100644
index 0000000..33f84b6
--- /dev/null
+++ b/data/registers/rtc_v2.yaml
@@ -0,0 +1,1786 @@
+---
+block/RTC:
+  description: Real-time clock
+  items:
+    - name: TR
+      description: time register
+      byte_offset: 0
+      fieldset: TR
+    - name: DR
+      description: date register
+      byte_offset: 4
+      fieldset: DR
+    - name: CR
+      description: control register
+      byte_offset: 8
+      fieldset: CR
+    - name: ISR
+      description: initialization and status register
+      byte_offset: 12
+      fieldset: ISR
+    - name: PRER
+      description: prescaler register
+      byte_offset: 16
+      fieldset: PRER
+    - name: WUTR
+      description: wakeup timer register
+      byte_offset: 20
+      fieldset: WUTR
+    - name: ALRMR
+      description: alarm register
+      array:
+        len: 1
+        stride: 4
+      byte_offset: 28
+      fieldset: ALRMR
+    - name: WPR
+      description: write protection register
+      byte_offset: 36
+      access: Write
+      fieldset: WPR
+    - name: TSTR
+      description: timestamp time register
+      byte_offset: 48
+      access: Read
+      fieldset: TSTR
+    - name: TSDR
+      description: timestamp date register
+      byte_offset: 52
+      access: Read
+      fieldset: TSDR
+    - name: TSSSR
+      description: timestamp sub second register
+      byte_offset: 56
+      access: Read
+      fieldset: TSSSR
+    - name: CALR
+      description: calibration register
+      byte_offset: 60
+      fieldset: CALR
+    - name: TAMPCR
+      description: tamper and alternate function configuration register
+      byte_offset: 64
+      fieldset: TAMPCR
+    - name: ALRMSSR
+      description: alarm sub second register
+      array:
+        len: 1
+        stride: 4
+      byte_offset: 68
+      fieldset: ALRMSSR
+block/RTC_F0:
+  description: Real-time clock
+  extends: RTC_BASE
+  items:
+    - name: SSR
+      description: sub second register
+      byte_offset: 40
+      access: Read
+      fieldset: SSR
+    - name: SHIFTR
+      description: shift control register
+      byte_offset: 44
+      access: Write
+      fieldset: SHIFTR
+    - name: TAMPCR
+      description: tamper and alternate function configuration register
+      byte_offset: 64
+      fieldset: TAFCR_F0
+    - name: BKPR
+      description: backup register
+      array:
+        len: 5
+        stride: 4
+      byte_offset: 80
+      fieldset: BKPR
+block/RTC_F2:
+  description: Real-time clock
+  extends: RTC_BASE
+  items:
+    - name: CALIBR
+      description: calibration register
+      byte_offset: 24
+      fieldset: CALIBR
+    - name: ALRMR
+      description: alarm register
+      array:
+        len: 2
+        stride: 4
+      byte_offset: 28
+      fieldset: ALRMR
+    - name: TAMPCR
+      description: tamper and alternate function configuration register
+      byte_offset: 64
+      fieldset: TAFCR_F2
+    - name: ALRMSSR
+      description: alarm sub second register
+      array:
+        len: 2
+        stride: 4
+      byte_offset: 68
+      fieldset: ALRMSSR
+    - name: BKPR
+      description: backup register
+      array:
+        len: 32
+        stride: 4
+      byte_offset: 80
+      fieldset: BKPR
+block/RTC_F3:
+  description: Real-time clock
+  extends: RTC_BASE
+  items:
+    - name: ALRMR
+      description: alarm register
+      array:
+        len: 2
+        stride: 4
+      byte_offset: 28
+      fieldset: ALRMR
+    - name: SSR
+      description: sub second register
+      byte_offset: 40
+      access: Read
+      fieldset: SSR
+    - name: SHIFTR
+      description: shift control register
+      byte_offset: 44
+      access: Write
+      fieldset: SHIFTR
+    - name: TAMPCR
+      description: tamper and alternate function configuration register
+      byte_offset: 64
+      fieldset: TAFCR_F0_F3
+    - name: ALRMSSR
+      description: alarm sub second register
+      array:
+        len: 2
+        stride: 4
+      byte_offset: 68
+      fieldset: ALRMSSR
+    - name: BKPR
+      description: backup register
+      array:
+        len: 32
+        stride: 4
+      byte_offset: 80
+      fieldset: BKPR
+block/RTC_F4:
+  description: Real-time clock
+  extends: RTC_BASE
+  items:
+    - name: CALIBR
+      description: calibration register
+      byte_offset: 24
+      fieldset: CALIBR
+    - name: ALRMR
+      description: alarm register
+      array:
+        len: 2
+        stride: 4
+      byte_offset: 28
+      fieldset: ALRMR
+    - name: SSR
+      description: sub second register
+      byte_offset: 40
+      access: Read
+      fieldset: SSR
+    - name: SHIFTR
+      description: shift control register
+      byte_offset: 44
+      access: Write
+      fieldset: SHIFTR
+    - name: TAMPCR
+      description: tamper and alternate function configuration register
+      byte_offset: 64
+      fieldset: TAFCR_F4
+    - name: ALRMSSR
+      description: alarm sub second register
+      array:
+        len: 2
+        stride: 4
+      byte_offset: 68
+      fieldset: ALRMSSR
+    - name: BKPR
+      description: backup register
+      array:
+        len: 20
+        stride: 4
+      byte_offset: 80
+      fieldset: BKPR
+block/RTC_F7_H7:
+  description: Real-time clock
+  extends: RTC_BASE
+  items:
+    - name: ALRMR
+      description: alarm register
+      array:
+        len: 2
+        stride: 4
+      byte_offset: 28
+      fieldset: ALRMR
+    - name: SSR
+      description: sub second register
+      byte_offset: 40
+      access: Read
+      fieldset: SSR
+    - name: SHIFTR
+      description: shift control register
+      byte_offset: 44
+      access: Write
+      fieldset: SHIFTR
+    - name: TAMPCR
+      description: tamper and alternate function configuration register
+      byte_offset: 64
+      fieldset: TAMPCR_F7
+    - name: ALRMSSR
+      description: alarm sub second register
+      array:
+        len: 2
+        stride: 4
+      byte_offset: 68
+      fieldset: ALRMSSR
+    - name: OR
+      description: option register
+      byte_offset: 76
+      fieldset: OR
+    - name: BKPR
+      description: backup register
+      array:
+        len: 32
+        stride: 4
+      byte_offset: 80
+      fieldset: BKPR
+block/RTC_L0:
+  description: Real-time clock
+  extends: RTC_BASE
+  items:
+    - name: ALRMR
+      description: alarm register
+      array:
+        len: 2
+        stride: 4
+      byte_offset: 28
+      fieldset: ALRMR
+    - name: SSR
+      description: sub second register
+      byte_offset: 40
+      access: Read
+      fieldset: SSR
+    - name: SHIFTR
+      description: shift control register
+      byte_offset: 44
+      access: Write
+      fieldset: SHIFTR
+    - name: TAMPCR
+      description: tamper and alternate function configuration register
+      byte_offset: 64
+      fieldset: TAMPCR_L0
+    - name: ALRMSSR
+      description: alarm sub second register
+      array:
+        len: 2
+        stride: 4
+      byte_offset: 68
+      fieldset: ALRMSSR
+    - name: OR
+      description: option register
+      byte_offset: 76
+      fieldset: OR_L0
+    - name: BKPR
+      description: backup register
+      array:
+        len: 5
+        stride: 4
+      byte_offset: 80
+      fieldset: BKPR
+block/RTC_L1:
+  description: Real-time clock
+  extends: RTC_BASE
+  items:
+    - name: CALIBR
+      description: calibration register
+      byte_offset: 24
+      fieldset: CALIBR
+    - name: ALRMR
+      description: alarm register
+      array:
+        len: 2
+        stride: 4
+      byte_offset: 28
+      fieldset: ALRMR
+    - name: SSR
+      description: sub second register
+      byte_offset: 40
+      access: Read
+      fieldset: SSR
+    - name: SHIFTR
+      description: shift control register
+      byte_offset: 44
+      access: Write
+      fieldset: SHIFTR
+    - name: TAMPCR
+      description: tamper and alternate function configuration register
+      byte_offset: 64
+      fieldset: TAMPCR_L0
+    - name: ALRMSSR
+      description: alarm sub second register
+      array:
+        len: 2
+        stride: 4
+      byte_offset: 68
+      fieldset: ALRMSSR
+    - name: BKPR
+      description: backup register
+      array:
+        len: 32
+        stride: 4
+      byte_offset: 80
+      fieldset: BKPR
+fieldset/ALRMR:
+  description: alarm register
+  fields:
+    - name: SU
+      description: Second units in BCD format
+      bit_offset: 0
+      bit_size: 4
+    - name: ST
+      description: Second tens in BCD format
+      bit_offset: 4
+      bit_size: 3
+    - name: MSK1
+      description: Alarm seconds mask
+      bit_offset: 7
+      bit_size: 1
+      enum: ALRMR_MSK
+    - name: MNU
+      description: Minute units in BCD format
+      bit_offset: 8
+      bit_size: 4
+    - name: MNT
+      description: Minute tens in BCD format
+      bit_offset: 12
+      bit_size: 3
+    - name: MSK2
+      description: Alarm minutes mask
+      bit_offset: 15
+      bit_size: 1
+    - name: HU
+      description: Hour units in BCD format
+      bit_offset: 16
+      bit_size: 4
+    - name: HT
+      description: Hour tens in BCD format
+      bit_offset: 20
+      bit_size: 2
+    - name: PM
+      description: AM/PM notation
+      bit_offset: 22
+      bit_size: 1
+      enum: ALRMR_PM
+    - name: MSK3
+      description: Alarm hours mask
+      bit_offset: 23
+      bit_size: 1
+    - name: DU
+      description: Date units or day in BCD format
+      bit_offset: 24
+      bit_size: 4
+    - name: DT
+      description: Date tens in BCD format
+      bit_offset: 28
+      bit_size: 2
+    - name: WDSEL
+      description: Week day selection
+      bit_offset: 30
+      bit_size: 1
+      enum: ALRMR_WDSEL
+    - name: MSK4
+      description: Alarm date mask
+      bit_offset: 31
+      bit_size: 1
+fieldset/ALRMSSR:
+  description: alarm sub second register
+  fields:
+    - name: SS
+      description: Sub seconds value
+      bit_offset: 0
+      bit_size: 15
+    - name: MASKSS
+      description: Mask the most-significant bits starting at this bit
+      bit_offset: 24
+      bit_size: 4
+fieldset/BKPR:
+  description: backup register
+  fields:
+    - name: BKP
+      description: BKP
+      bit_offset: 0
+      bit_size: 32
+fieldset/CALIBR:
+  description: calibration register
+  fields:
+    - name: DC
+      description: Digital calibration
+      bit_offset: 0
+      bit_size: 5
+    - name: DCS
+      description: Digital calibration sign
+      bit_offset: 7
+      bit_size: 1
+fieldset/CALR:
+  description: calibration register
+  fields:
+    - name: CALM
+      description: Calibration minus
+      bit_offset: 0
+      bit_size: 9
+    - name: CALW16
+      description: Use a 16-second calibration cycle period
+      bit_offset: 13
+      bit_size: 1
+    - name: CALW8
+      description: Use a 8-second calibration cycle period
+      bit_offset: 14
+      bit_size: 1
+    - name: CALP
+      description: Increase frequency of RTC by 488.5 ppm
+      bit_offset: 15
+      bit_size: 1
+      enum: CALP
+fieldset/CR:
+  description: control register
+  fields:
+    - name: WUCKSEL
+      description: Wakeup clock selection
+      bit_offset: 0
+      bit_size: 3
+      enum: WUCKSEL
+    - name: TSEDGE
+      description: Time-stamp event active edge
+      bit_offset: 3
+      bit_size: 1
+      enum: TSEDGE
+    - name: REFCKON
+      description: Reference clock detection enable (50 or 60 Hz)
+      bit_offset: 4
+      bit_size: 1
+      enum: REFCKON
+    - name: FMT
+      description: Hour format
+      bit_offset: 6
+      bit_size: 1
+      enum: FMT
+    - name: ALRE
+      description: Alarm enable
+      array:
+        len: 1
+        stride: 1
+      bit_offset: 8
+      bit_size: 1
+      enum: ALRE
+    - name: WUTE
+      description: Wakeup timer enable
+      bit_offset: 10
+      bit_size: 1
+      enum: WUTE
+    - name: TSE
+      description: Timestamp enable
+      bit_offset: 11
+      bit_size: 1
+      enum: TSE
+    - name: ALRIE
+      description: Alarm interrupt enable
+      array:
+        len: 1
+        stride: 1
+      bit_offset: 12
+      bit_size: 1
+      enum: ALRIE
+    - name: WUTIE
+      description: Wakeup timer interrupt enable
+      bit_offset: 14
+      bit_size: 1
+      enum: WUTIE
+    - name: TSIE
+      description: Time-stamp interrupt enable
+      bit_offset: 15
+      bit_size: 1
+      enum: TSIE
+    - name: ADD1H
+      description: Add 1 hour (summer time change)
+      bit_offset: 16
+      bit_size: 1
+      enum_write: ADDHW
+    - name: SUB1H
+      description: Subtract 1 hour (winter time change)
+      bit_offset: 17
+      bit_size: 1
+      enum_write: SUBHW
+    - name: BKP
+      description: Backup
+      bit_offset: 18
+      bit_size: 1
+      enum: BKP
+    - name: POL
+      description: Output polarity
+      bit_offset: 20
+      bit_size: 1
+      enum: POL
+    - name: OSEL
+      description: Output selection
+      bit_offset: 21
+      bit_size: 2
+      enum: OSEL
+    - name: COE
+      description: Calibration output enable
+      bit_offset: 23
+      bit_size: 1
+      enum: COE
+fieldset/CR_F0:
+  extemds: CR
+  description: control register
+  fields:
+    - name: BYPSHAD
+      description: Bypass the shadow registers
+      bit_offset: 5
+      bit_size: 1
+      enum: BYPSHAD
+    - name: COSEL
+      description: Calibration output selection
+      bit_offset: 19
+      bit_size: 1
+      enum: COSEL
+fieldset/CR_F2:
+  extemds: CR
+  description: control register
+  fields:
+    - name: DCE
+      description: Coarse digital calibration enable
+      bit_offset: 7
+      bit_size: 1
+    - name: ALRE
+      description: Alarm enable
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 8
+      bit_size: 1
+      enum: ALRE
+    - name: ALRIE
+      description: Alarm interrupt enable
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 12
+      bit_size: 1
+      enum: ALRIE
+fieldset/CR_F3:
+  extemds: CR
+  description: control register
+  fields:
+    - name: BYPSHAD
+      description: Bypass the shadow registers
+      bit_offset: 5
+      bit_size: 1
+      enum: BYPSHAD
+    - name: ALRE
+      description: Alarm enable
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 8
+      bit_size: 1
+      enum: ALRE
+    - name: ALRIE
+      description: Alarm interrupt enable
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 12
+      bit_size: 1
+      enum: ALRIE
+    - name: COSEL
+      description: Calibration output selection
+      bit_offset: 19
+      bit_size: 1
+      enum: COSEL
+fieldset/CR_F4:
+  extemds: CR
+  description: control register
+  fields:
+    - name: BYPSHAD
+      description: Bypass the shadow registers
+      bit_offset: 5
+      bit_size: 1
+      enum: BYPSHAD
+    - name: DCE
+      description: Coarse digital calibration enable
+      bit_offset: 7
+      bit_size: 1
+    - name: ALRE
+      description: Alarm enable
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 8
+      bit_size: 1
+      enum: ALRE
+    - name: ALRIE
+      description: Alarm interrupt enable
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 12
+      bit_size: 1
+      enum: ALRIE
+    - name: COSEL
+      description: Calibration output selection
+      bit_offset: 19
+      bit_size: 1
+      enum: COSEL
+fieldset/CR_F7_H7:
+  extemds: CR
+  description: control register
+  fields:
+    - name: BYPSHAD
+      description: Bypass the shadow registers
+      bit_offset: 5
+      bit_size: 1
+      enum: BYPSHAD
+    - name: ALRE
+      description: Alarm enable
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 8
+      bit_size: 1
+      enum: ALRE
+    - name: ALRIE
+      description: Alarm interrupt enable
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 12
+      bit_size: 1
+      enum: ALRIE
+    - name: COSEL
+      description: Calibration output selection
+      bit_offset: 19
+      bit_size: 1
+      enum: COSEL
+    - name: ITSE
+      description: timestamp on internal event enable
+      bit_offset: 24
+      bit_size: 1
+fieldset/CR_L0:
+  extemds: CR
+  description: control register
+  fields:
+    - name: BYPSHAD
+      description: Bypass the shadow registers
+      bit_offset: 5
+      bit_size: 1
+      enum: BYPSHAD
+    - name: ALRE
+      description: Alarm enable
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 8
+      bit_size: 1
+      enum: ALRE
+    - name: ALRIE
+      description: Alarm interrupt enable
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 12
+      bit_size: 1
+      enum: ALRIE
+    - name: COSEL
+      description: Calibration output selection
+      bit_offset: 19
+      bit_size: 1
+      enum: COSEL
+fieldset/CR_L1:
+  extemds: CR
+  description: control register
+  fields:
+    - name: DCE
+      description: Coarse digital calibration enable
+      bit_offset: 7
+      bit_size: 1
+fieldset/DR:
+  description: date register
+  fields:
+    - name: DU
+      description: Date units in BCD format
+      bit_offset: 0
+      bit_size: 4
+    - name: DT
+      description: Date tens in BCD format
+      bit_offset: 4
+      bit_size: 2
+    - name: MU
+      description: Month units in BCD format
+      bit_offset: 8
+      bit_size: 4
+    - name: MT
+      description: Month tens in BCD format
+      bit_offset: 12
+      bit_size: 1
+    - name: WDU
+      description: Week day units
+      bit_offset: 13
+      bit_size: 3
+    - name: YU
+      description: Year units in BCD format
+      bit_offset: 16
+      bit_size: 4
+    - name: YT
+      description: Year tens in BCD format
+      bit_offset: 20
+      bit_size: 4
+fieldset/ISR:
+  description: initialization and status register
+  fields:
+    - name: ALRWF
+      description: Alarm write flag
+      array:
+        len: 1
+        stride: 1
+      bit_offset: 0
+      bit_size: 1
+      enum_read: ALRWFR
+    - name: WUTWF
+      description: Wakeup timer write flag
+      bit_offset: 2
+      bit_size: 1
+      enum_read: WUTWFR
+    - name: INITS
+      description: Initialization status flag
+      bit_offset: 4
+      bit_size: 1
+      enum_read: INITSR
+    - name: RSF
+      description: Registers synchronization flag
+      bit_offset: 5
+      bit_size: 1
+      enum_read: RSFR
+      enum_write: RSFW
+    - name: INITF
+      description: Initialization flag
+      bit_offset: 6
+      bit_size: 1
+      enum_read: INITFR
+    - name: INIT
+      description: Initialization mode
+      bit_offset: 7
+      bit_size: 1
+      enum: INIT
+    - name: ALRF
+      description: Alarm flag
+      array:
+        len: 1
+        stride: 1
+      bit_offset: 8
+      bit_size: 1
+      enum_read: ALRFR
+      enum_write: ALRFW
+    - name: WUTF
+      description: Wakeup timer flag
+      bit_offset: 10
+      bit_size: 1
+      enum_read: WUTFR
+      enum_write: WUTFW
+    - name: TSF
+      description: Time-stamp flag
+      bit_offset: 11
+      bit_size: 1
+      enum_read: TSFR
+      enum_write: TSFW
+    - name: TSOVF
+      description: Time-stamp overflow flag
+      bit_offset: 12
+      bit_size: 1
+      enum_read: TSOVFR
+      enum_write: TSOVFW
+    - name: TAMPF
+      description: Tamper detection flag
+      array:
+        len: 1
+        stride: 1
+      bit_offset: 13
+      bit_size: 1
+      enum_read: TAMPFR
+      enum_write: TAMPFW
+fieldset/ISR_F0:
+  extedns: ISR
+  description: initialization and status register
+  fields:
+    - name: SHPF
+      description: Shift operation pending
+      bit_offset: 3
+      bit_size: 1
+      enum_read: SHPFR
+    - name: TAMPF
+      description: Tamper detection flag
+      array:
+        len: 3
+        stride: 1
+      bit_offset: 13
+      bit_size: 1
+      enum_read: TAMPFR
+      enum_write: TAMPFW
+    - name: RECALPF
+      description: Recalibration pending Flag
+      bit_offset: 16
+      bit_size: 1
+      enum_read: RECALPFR
+fieldset/ISR_F2:
+  extedns: ISR
+  description: initialization and status register
+  fields:
+    - name: ALRWF
+      description: Alarm write flag
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 0
+      bit_size: 1
+      enum_read: ALRWFR
+    - name: ALRF
+      description: Alarm flag
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 8
+      bit_size: 1
+      enum_read: ALRFR
+      enum_write: ALRFW
+fieldset/ISR_F3:
+  extedns: ISR
+  description: initialization and status register
+  fields:
+    - name: ALRWF
+      description: Alarm write flag
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 0
+      bit_size: 1
+      enum_read: ALRWFR
+    - name: SHPF
+      description: Shift operation pending
+      bit_offset: 3
+      bit_size: 1
+      enum_read: SHPFR
+    - name: ALRF
+      description: Alarm flag
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 8
+      bit_size: 1
+      enum_read: ALRFR
+      enum_write: ALRFW
+    - name: RECALPF
+      description: Recalibration pending Flag
+      bit_offset: 16
+      bit_size: 1
+      enum_read: RECALPFR
+fieldset/ISR_F4:
+  extedns: ISR
+  description: initialization and status register
+  fields:
+    - name: ALRWF
+      description: Alarm write flag
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 0
+      bit_size: 1
+      enum_read: ALRWFR
+    - name: SHPF
+      description: Shift operation pending
+      bit_offset: 3
+      bit_size: 1
+      enum_read: SHPFR
+    - name: ALRF
+      description: Alarm flag
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 8
+      bit_size: 1
+      enum_read: ALRFR
+      enum_write: ALRFW
+    - name: RECALPF
+      description: Recalibration pending Flag
+      bit_offset: 16
+      bit_size: 1
+      enum_read: RECALPFR
+fieldset/ISR_F7_H7:
+  extedns: ISR
+  description: initialization and status register
+  fields:
+    - name: ALRWF
+      description: Alarm write flag
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 0
+      bit_size: 1
+      enum_read: ALRWFR
+    - name: SHPF
+      description: Shift operation pending
+      bit_offset: 3
+      bit_size: 1
+      enum_read: SHPFR
+    - name: ALRF
+      description: Alarm flag
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 8
+      bit_size: 1
+      enum_read: ALRFR
+      enum_write: ALRFW
+    - name: TAMPF
+      description: Tamper detection flag
+      array:
+        len: 3
+        stride: 1
+      bit_offset: 13
+      bit_size: 1
+      enum_read: TAMPFR
+      enum_write: TAMPFW
+    - name: RECALPF
+      description: Recalibration pending Flag
+      bit_offset: 16
+      bit_size: 1
+      enum_read: RECALPFR
+    - name: ITSF
+      description: Internal timestamp flag
+      bit_offset: 17
+      bit_size: 1
+fieldset/ISR_L0:
+  extedns: ISR
+  description: initialization and status register
+  fields:
+    - name: ALRWF
+      description: Alarm write flag
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 0
+      bit_size: 1
+      enum_read: ALRWFR
+    - name: SHPF
+      description: Shift operation pending
+      bit_offset: 3
+      bit_size: 1
+      enum_read: SHPFR
+    - name: ALRF
+      description: Alarm flag
+      array:
+        len: 2
+        stride: 1
+      bit_offset: 8
+      bit_size: 1
+      enum_read: ALRFR
+      enum_write: ALRFW
+    - name: TAMPF
+      description: Tamper detection flag
+      array:
+        len: 3
+        stride: 1
+      bit_offset: 13
+      bit_size: 1
+      enum_read: TAMPFR
+      enum_write: TAMPFW
+    - name: RECALPF
+      description: Recalibration pending Flag
+      bit_offset: 16
+      bit_size: 1
+      enum_read: RECALPFR
+fieldset/OR_F7:
+  description: option register
+  fields:
+    - name: TSINSEL
+      description: TIMESTAMP mapping
+      bit_offset: 1
+      bit_size: 2
+    - name: RTC_ALARM_TYPE
+      description: RTC_ALARM on PC13 output type
+      bit_offset: 3
+      bit_size: 1
+fieldset/OR_H7_L0:
+  description: option register
+  fields:
+    - name: RTC_ALARM_TYPE
+      description: RTC_ALARM on PC13 output type
+      bit_offset: 0
+      bit_size: 1
+    - name: RTC_OUT_RMP
+      description: RTC_OUT remap
+      bit_offset: 1
+      bit_size: 1
+fieldset/PRER:
+  description: prescaler register
+  fields:
+    - name: PREDIV_S
+      description: Synchronous prescaler factor
+      bit_offset: 0
+      bit_size: 15
+    - name: PREDIV_A
+      description: Asynchronous prescaler factor
+      bit_offset: 16
+      bit_size: 7
+fieldset/PRER_F2:
+  extends: PRER
+  description: prescaler register
+  fields:
+    - name: PREDIV_S
+      description: Synchronous prescaler factor
+      bit_offset: 0
+      bit_size: 13
+fieldset/SHIFTR:
+  description: shift control register
+  fields:
+    - name: SUBFS
+      description: Subtract a fraction of a second
+      bit_offset: 0
+      bit_size: 15
+    - name: ADD1S
+      description: Add one second
+      bit_offset: 31
+      bit_size: 1
+      enum_write: ADDSW
+fieldset/SSR:
+  description: sub second register
+  fields:
+    - name: SS
+      description: Sub second value
+      bit_offset: 0
+      bit_size: 16
+fieldset/TAMPCR:
+  description: tamper configuration register
+  fields:
+    - name: TAMP1E
+      description: Tamper 1 detection enable
+      bit_offset: 0
+      bit_size: 1
+    - name: TAMP1TRG
+      description: Active level for tamper 1
+      bit_offset: 1
+      bit_size: 1
+    - name: TAMPIE
+      description: Tamper interrupt enable
+      bit_offset: 2
+      bit_size: 1
+fieldset/TAMPCR_2:
+  extends: TAMPCR
+  description: tamper configuration register
+  fields:
+    - name: TAMP2E
+      description: Tamper 2 detection enable
+      bit_offset: 3
+      bit_size: 1
+    - name: TAMP2TRG
+      description: Active level for tamper 2
+      bit_offset: 4
+      bit_size: 1
+    - name: TAMPTS
+      description: Activate timestamp on tamper detection event
+      bit_offset: 7
+      bit_size: 1
+    - name: TAMPFREQ
+      description: Tamper sampling frequency
+      bit_offset: 8
+      bit_size: 3
+    - name: TAMPFLT
+      description: Tamper filter count
+      bit_offset: 11
+      bit_size: 2
+    - name: TAMPPRCH
+      description: Tamper precharge duration
+      bit_offset: 13
+      bit_size: 2
+    - name: TAMPPUDIS
+      description: Tamper pull-up disable
+      bit_offset: 15
+      bit_size: 1
+fieldset/TAMPCR_3:
+  extends: TAMPCR_2
+  description: tamper configuration register
+  fields:
+    - name: TAMP3E
+      description: Tamper 3 detection enable
+      bit_offset: 5
+      bit_size: 1
+    - name: TAMP3TRG
+      description: Active level for tamper 3
+      bit_offset: 6
+      bit_size: 1
+fieldset/TAFCR_F0_F3:
+  extedns: TAMPCR_3
+  description: tamper and alternate function configuration register
+  fields:
+    - name: PC13VALUE
+      description: "RTC_ALARM output type/PC13 value"
+      bit_offset: 18
+      bit_size: 1
+      enum: PCVALUE
+    - name: PC13MODE
+      description: PC13 mode
+      bit_offset: 19
+      bit_size: 1
+      enum: PCMODE
+    - name: PC14VALUE
+      description: PC14 value
+      bit_offset: 20
+      bit_size: 1
+      enum: PCVALUE
+    - name: PC14MODE
+      description: PC14 mode
+      bit_offset: 21
+      bit_size: 1
+      enum: PCMODE
+    - name: PC15VALUE
+      description: PC15 value
+      bit_offset: 22
+      bit_size: 1
+      enum: PCVALUE
+    - name: PC15MODE
+      description: PC15 mode
+      bit_offset: 23
+      bit_size: 1
+      enum: PCMODE
+fieldset/TAFCR_F2:
+  extedns: TAMPCR
+  description: tamper and alternate function configuration register
+  fields:
+    - name: TAMP1INSEL
+      description: TAMPER1 mapping
+      bit_offset: 16
+      bit_size: 1
+    - name: TSINSEL
+      description: TIMESTAMP mapping
+      bit_offset: 17
+      bit_size: 1
+    - name: ALARMOUTTYPE
+      description: AFO_ALARM output type
+      bit_offset: 18
+      bit_size: 1
+fieldset/TAFCR_F4:
+  extedns: TAMPCR
+  description: tamper and alternate function configuration register
+  fields:
+    - name: TAMP1INSEL
+      description: TAMPER1 mapping
+      bit_offset: 16
+      bit_size: 1
+    - name: TSINSEL
+      description: TIMESTAMP mapping
+      bit_offset: 17
+      bit_size: 1
+    - name: ALARMOUTTYPE
+      description: AFO_ALARM output type
+      bit_offset: 18
+      bit_size: 1
+fieldset/TAMPCR_F7_H7_L0:
+  extedns: TAMPCR_3
+  description: tamper configuration register
+  fields:
+    - name: TAMP1IE
+      description: Tamper 1 interrupt enable
+      bit_offset: 16
+      bit_size: 1
+    - name: TAMP1NOERASE
+      description: Tamper 1 no erase
+      bit_offset: 17
+      bit_size: 1
+    - name: TAMP1MF
+      description: Tamper 1 mask flag
+      bit_offset: 18
+      bit_size: 1
+    - name: TAMP2IE
+      description: Tamper 2 interrupt enable
+      bit_offset: 19
+      bit_size: 1
+    - name: TAMP2NOERASE
+      description: Tamper 2 no erase
+      bit_offset: 20
+      bit_size: 1
+    - name: TAMP2MF
+      description: Tamper 2 mask flag
+      bit_offset: 21
+      bit_size: 1
+    - name: TAMP3IE
+      description: Tamper 3 interrupt enable
+      bit_offset: 22
+      bit_size: 1
+    - name: TAMP3NOERASE
+      description: Tamper 3 no erase
+      bit_offset: 23
+      bit_size: 1
+    - name: TAMP3MF
+      description: Tamper 3 mask flag
+      bit_offset: 24
+      bit_size: 1
+fieldset/TR:
+  description: time register
+  fields:
+    - name: SU
+      description: Second units in BCD format
+      bit_offset: 0
+      bit_size: 4
+    - name: ST
+      description: Second tens in BCD format
+      bit_offset: 4
+      bit_size: 3
+    - name: MNU
+      description: Minute units in BCD format
+      bit_offset: 8
+      bit_size: 4
+    - name: MNT
+      description: Minute tens in BCD format
+      bit_offset: 12
+      bit_size: 3
+    - name: HU
+      description: Hour units in BCD format
+      bit_offset: 16
+      bit_size: 4
+    - name: HT
+      description: Hour tens in BCD format
+      bit_offset: 20
+      bit_size: 2
+    - name: PM
+      description: AM/PM notation
+      bit_offset: 22
+      bit_size: 1
+      enum: TR_PM
+fieldset/TSDR:
+  description: timestamp date register
+  fields:
+    - name: DU
+      description: Date units in BCD format
+      bit_offset: 0
+      bit_size: 4
+    - name: DT
+      description: Date tens in BCD format
+      bit_offset: 4
+      bit_size: 2
+    - name: MU
+      description: Month units in BCD format
+      bit_offset: 8
+      bit_size: 4
+    - name: MT
+      description: Month tens in BCD format
+      bit_offset: 12
+      bit_size: 1
+    - name: WDU
+      description: Week day units
+      bit_offset: 13
+      bit_size: 3
+fieldset/TSSSR:
+  description: timestamp sub second register
+  fields:
+    - name: SS
+      description: Sub second value
+      bit_offset: 0
+      bit_size: 16
+fieldset/TSTR:
+  description: timestamp time register
+  fields:
+    - name: SU
+      description: Second units in BCD format
+      bit_offset: 0
+      bit_size: 4
+    - name: ST
+      description: Second tens in BCD format
+      bit_offset: 4
+      bit_size: 3
+    - name: MNU
+      description: Minute units in BCD format
+      bit_offset: 8
+      bit_size: 4
+    - name: MNT
+      description: Minute tens in BCD format
+      bit_offset: 12
+      bit_size: 3
+    - name: HU
+      description: Hour units in BCD format
+      bit_offset: 16
+      bit_size: 4
+    - name: HT
+      description: Hour tens in BCD format
+      bit_offset: 20
+      bit_size: 2
+    - name: PM
+      description: AM/PM notation
+      bit_offset: 22
+      bit_size: 1
+fieldset/WPR:
+  description: write protection register
+  fields:
+    - name: KEY
+      description: Write protection key
+      bit_offset: 0
+      bit_size: 8
+fieldset/WUTR:
+  description: wakeup timer register
+  fields:
+    - name: WUT
+      description: Wakeup auto-reload value bits
+      bit_offset: 0
+      bit_size: 16
+enum/ADDHW:
+  bit_size: 1
+  variants:
+    - name: Add1
+      description: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode
+      value: 1
+enum/ADDSW:
+  bit_size: 1
+  variants:
+    - name: Add1
+      description: Add one second to the clock/calendar
+      value: 1
+enum/ALRAE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Alarm A disabled
+      value: 0
+    - name: Enabled
+      description: Alarm A enabled
+      value: 1
+enum/ALRAFR:
+  bit_size: 1
+  variants:
+    - name: Match
+      description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)
+      value: 1
+enum/ALRAFW:
+  bit_size: 1
+  variants:
+    - name: Clear
+      description: This flag is cleared by software by writing 0
+      value: 0
+enum/ALRAIE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Alarm A interrupt disabled
+      value: 0
+    - name: Enabled
+      description: Alarm A interrupt enabled
+      value: 1
+enum/ALRAWFR:
+  bit_size: 1
+  variants:
+    - name: UpdateNotAllowed
+      description: Alarm update not allowed
+      value: 0
+    - name: UpdateAllowed
+      description: Alarm update allowed
+      value: 1
+enum/ALRBE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Alarm B disabled
+      value: 0
+    - name: Enabled
+      description: Alarm B enabled
+      value: 1
+enum/ALRBFR:
+  bit_size: 1
+  variants:
+    - name: Match
+      description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR)
+      value: 1
+enum/ALRBFW:
+  bit_size: 1
+  variants:
+    - name: Clear
+      description: This flag is cleared by software by writing 0
+      value: 0
+enum/ALRBIE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Alarm B Interrupt disabled
+      value: 0
+    - name: Enabled
+      description: Alarm B Interrupt enabled
+      value: 1
+enum/ALRMAR_MSK:
+  bit_size: 1
+  variants:
+    - name: Mask
+      description: Alarm set if the date/day match
+      value: 0
+    - name: NotMask
+      description: Date/day don’t care in Alarm comparison
+      value: 1
+enum/ALRMAR_PM:
+  bit_size: 1
+  variants:
+    - name: AM
+      description: AM or 24-hour format
+      value: 0
+    - name: PM
+      description: PM
+      value: 1
+enum/ALRMAR_WDSEL:
+  bit_size: 1
+  variants:
+    - name: DateUnits
+      description: "DU[3:0] represents the date units"
+      value: 0
+    - name: WeekDay
+      description: "DU[3:0] represents the week day. DT[1:0] is don’t care."
+      value: 1
+enum/ALRMBR_MSK:
+  bit_size: 1
+  variants:
+    - name: Mask
+      description: Alarm set if the date/day match
+      value: 0
+    - name: NotMask
+      description: Date/day don’t care in Alarm comparison
+      value: 1
+enum/ALRMBR_PM:
+  bit_size: 1
+  variants:
+    - name: AM
+      description: AM or 24-hour format
+      value: 0
+    - name: PM
+      description: PM
+      value: 1
+enum/ALRMBR_WDSEL:
+  bit_size: 1
+  variants:
+    - name: DateUnits
+      description: "DU[3:0] represents the date units"
+      value: 0
+    - name: WeekDay
+      description: "DU[3:0] represents the week day. DT[1:0] is don’t care."
+      value: 1
+enum/BKP:
+  bit_size: 1
+  variants:
+    - name: DST_Not_Changed
+      description: Daylight Saving Time change has not been performed
+      value: 0
+    - name: DST_Changed
+      description: Daylight Saving Time change has been performed
+      value: 1
+enum/BYPSHAD:
+  bit_size: 1
+  variants:
+    - name: ShadowReg
+      description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles"
+      value: 0
+    - name: BypassShadowReg
+      description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters"
+      value: 1
+enum/CALP:
+  bit_size: 1
+  variants:
+    - name: NoChange
+      description: No RTCCLK pulses are added
+      value: 0
+    - name: IncreaseFreq
+      description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)
+      value: 1
+enum/CALW16:
+  bit_size: 1
+  variants:
+    - name: Sixteen_Second
+      description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1"
+      value: 1
+enum/CALW8:
+  bit_size: 1
+  variants:
+    - name: Eight_Second
+      description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected"
+      value: 1
+enum/COE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Calibration output disabled
+      value: 0
+    - name: Enabled
+      description: Calibration output enabled
+      value: 1
+enum/COSEL:
+  bit_size: 1
+  variants:
+    - name: CalFreq_512Hz
+      description: Calibration output is 512 Hz (with default prescaler setting)
+      value: 0
+    - name: CalFreq_1Hz
+      description: Calibration output is 1 Hz (with default prescaler setting)
+      value: 1
+enum/FMT:
+  bit_size: 1
+  variants:
+    - name: Twenty_Four_Hour
+      description: 24 hour/day format
+      value: 0
+    - name: AM_PM
+      description: AM/PM hour format
+      value: 1
+enum/INIT:
+  bit_size: 1
+  variants:
+    - name: FreeRunningMode
+      description: Free running mode
+      value: 0
+    - name: InitMode
+      description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset."
+      value: 1
+enum/INITFR:
+  bit_size: 1
+  variants:
+    - name: NotAllowed
+      description: Calendar registers update is not allowed
+      value: 0
+    - name: Allowed
+      description: Calendar registers update is allowed
+      value: 1
+enum/INITSR:
+  bit_size: 1
+  variants:
+    - name: NotInitalized
+      description: Calendar has not been initialized
+      value: 0
+    - name: Initalized
+      description: Calendar has been initialized
+      value: 1
+enum/OSEL:
+  bit_size: 2
+  variants:
+    - name: Disabled
+      description: Output disabled
+      value: 0
+    - name: AlarmA
+      description: Alarm A output enabled
+      value: 1
+    - name: AlarmB
+      description: Alarm B output enabled
+      value: 2
+    - name: Wakeup
+      description: Wakeup output enabled
+      value: 3
+enum/PCMODE:
+  bit_size: 1
+  variants:
+    - name: Floating
+      description: PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode
+      value: 0
+    - name: PushPull
+      description: PCx is forced to push-pull output if LSE is disabled
+      value: 1
+enum/PCVALUE:
+  bit_size: 1
+  variants:
+    - name: Low
+      description: "If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low"
+      value: 0
+    - name: High
+      description: "If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high"
+      value: 1
+enum/POL:
+  bit_size: 1
+  variants:
+    - name: High
+      description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"
+      value: 0
+    - name: Low
+      description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"
+      value: 1
+enum/RECALPFR:
+  bit_size: 1
+  variants:
+    - name: Pending
+      description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0"
+      value: 1
+enum/REFCKON:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: RTC_REFIN detection disabled
+      value: 0
+    - name: Enabled
+      description: RTC_REFIN detection enabled
+      value: 1
+enum/RSFR:
+  bit_size: 1
+  variants:
+    - name: NotSynced
+      description: Calendar shadow registers not yet synchronized
+      value: 0
+    - name: Synced
+      description: Calendar shadow registers synchronized
+      value: 1
+enum/RSFW:
+  bit_size: 1
+  variants:
+    - name: Clear
+      description: This flag is cleared by software by writing 0
+      value: 0
+enum/SHPFR:
+  bit_size: 1
+  variants:
+    - name: NoShiftPending
+      description: No shift operation is pending
+      value: 0
+    - name: ShiftPending
+      description: A shift operation is pending
+      value: 1
+enum/SUBHW:
+  bit_size: 1
+  variants:
+    - name: Sub1
+      description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode
+      value: 1
+enum/TAMPFR:
+  bit_size: 1
+  variants:
+    - name: Tampered
+      description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
+      value: 1
+enum/TAMPFW:
+  bit_size: 1
+  variants:
+    - name: Clear
+      description: Flag cleared by software writing 0
+      value: 0
+enum/TR_PM:
+  bit_size: 1
+  variants:
+    - name: AM
+      description: AM or 24-hour format
+      value: 0
+    - name: PM
+      description: PM
+      value: 1
+enum/TSE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Timestamp disabled
+      value: 0
+    - name: Enabled
+      description: Timestamp enabled
+      value: 1
+enum/TSEDGE:
+  bit_size: 1
+  variants:
+    - name: RisingEdge
+      description: RTC_TS input rising edge generates a time-stamp event
+      value: 0
+    - name: FallingEdge
+      description: RTC_TS input falling edge generates a time-stamp event
+      value: 1
+enum/TSFR:
+  bit_size: 1
+  variants:
+    - name: TimestampEvent
+      description: This flag is set by hardware when a time-stamp event occurs
+      value: 1
+enum/TSFW:
+  bit_size: 1
+  variants:
+    - name: Clear
+      description: This flag is cleared by software by writing 0
+      value: 0
+enum/TSIE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Time-stamp Interrupt disabled
+      value: 0
+    - name: Enabled
+      description: Time-stamp Interrupt enabled
+      value: 1
+enum/TSOVFR:
+  bit_size: 1
+  variants:
+    - name: Overflow
+      description: This flag is set by hardware when a time-stamp event occurs while TSF is already set
+      value: 1
+enum/TSOVFW:
+  bit_size: 1
+  variants:
+    - name: Clear
+      description: This flag is cleared by software by writing 0
+      value: 0
+enum/WUCKSEL:
+  bit_size: 3
+  variants:
+    - name: Div16
+      description: RTC/16 clock is selected
+      value: 0
+    - name: Div8
+      description: RTC/8 clock is selected
+      value: 1
+    - name: Div4
+      description: RTC/4 clock is selected
+      value: 2
+    - name: Div2
+      description: RTC/2 clock is selected
+      value: 3
+    - name: ClockSpare
+      description: ck_spre (usually 1 Hz) clock is selected
+      value: 4
+    - name: ClockSpareWithOffset
+      description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
+      value: 6
+enum/WUTE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Wakeup timer disabled
+      value: 0
+    - name: Enabled
+      description: Wakeup timer enabled
+      value: 1
+enum/WUTFR:
+  bit_size: 1
+  variants:
+    - name: Zero
+      description: This flag is set by hardware when the wakeup auto-reload counter reaches 0
+      value: 1
+enum/WUTFW:
+  bit_size: 1
+  variants:
+    - name: Clear
+      description: This flag is cleared by software by writing 0
+      value: 0
+enum/WUTIE:
+  bit_size: 1
+  variants:
+    - name: Disabled
+      description: Wakeup timer interrupt disabled
+      value: 0
+    - name: Enabled
+      description: Wakeup timer interrupt enabled
+      value: 1
+enum/WUTWFR:
+  bit_size: 1
+  variants:
+    - name: UpdateNotAllowed
+      description: Wakeup timer configuration update not allowed
+      value: 0
+    - name: UpdateAllowed
+      description: Wakeup timer configuration update allowed
+      value: 1