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Add more peripherals for wl5x

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This commit is contained in:
Ulf Lilleengen 2021-06-16 16:07:00 +02:00
parent 9161dbcac9
commit 3ef6421aa8
4 changed files with 185 additions and 3 deletions
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181
data/registers/dbgmcu_wl5x.yaml Normal file
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@ -0,0 +1,181 @@
---
block/DBGMCU:
description: Microcontroller Debug Unit
items:
- name: IDCODER
description: DBGMCU Identity Code Register
byte_offset: 0
access: Read
fieldset: IDCODER
- name: CR
description: DBGMCU Configuration Register
byte_offset: 4
fieldset: CR
- name: APB1FZR1
description: DBGMCU CPU1 APB1 Peripheral Freeze Register 1
byte_offset: 60
fieldset: APB1FZR1
- name: C2APB1FZR1
description: "DBGMCU CPU2 APB1 Peripheral Freeze Register 1 [dual core device"
byte_offset: 64
fieldset: C2APB1FZR1
- name: APB1FZR2
description: DBGMCU CPU1 APB1 Peripheral Freeze Register 2
byte_offset: 68
fieldset: APB1FZR2
- name: C2APB1FZR2
description: "DBGMCU CPU2 APB1 Peripheral Freeze Register 2 [dual core device"
byte_offset: 72
fieldset: C2APB1FZR2
- name: APB2FZR
description: DBGMCU CPU1 APB2 Peripheral Freeze Register
byte_offset: 76
fieldset: APB2FZR
- name: C2APB2FZR
description: "DBGMCU CPU2 APB2 Peripheral Freeze Register [dual core device"
byte_offset: 80
fieldset: C2APB2FZR
fieldset/APB1FZR1:
description: DBGMCU CPU1 APB1 Peripheral Freeze Register 1
fields:
- name: DBG_TIM2_STOP
description: TIM2 stop in CPU1 debug
bit_offset: 0
bit_size: 1
- name: DBG_RTC_STOP
description: RTC stop in CPU1 debug
bit_offset: 10
bit_size: 1
- name: DBG_WWDG_STOP
description: WWDG stop in CPU1 debug
bit_offset: 11
bit_size: 1
- name: DBG_IWDG_STOP
description: IWDG stop in CPU1 debug
bit_offset: 12
bit_size: 1
- name: DBG_I2C1_STOP
description: I2C1 SMBUS timeout stop in CPU1 debug
bit_offset: 21
bit_size: 1
- name: DBG_I2C2_STOP
description: I2C2 SMBUS timeout stop in CPU1 debug
bit_offset: 22
bit_size: 1
- name: DBG_I2C3_STOP
description: I2C3 SMBUS timeout stop in CPU1 debug
bit_offset: 23
bit_size: 1
- name: DBG_LPTIM1_STOP
description: LPTIM1 stop in CPU1 debug
bit_offset: 31
bit_size: 1
fieldset/APB1FZR2:
description: DBGMCU CPU1 APB1 Peripheral Freeze Register 2
fields:
- name: DBG_LPTIM2_STOP
description: DBG_LPTIM2_STOP
bit_offset: 5
bit_size: 1
- name: DBG_LPTIM3_STOP
description: DBG_LPTIM3_STOP
bit_offset: 6
bit_size: 1
fieldset/APB2FZR:
description: DBGMCU CPU1 APB2 Peripheral Freeze Register
fields:
- name: DBG_TIM1_STOP
description: DBG_TIM1_STOP
bit_offset: 11
bit_size: 1
- name: DBG_TIM16_STOP
description: DBG_TIM16_STOP
bit_offset: 17
bit_size: 1
- name: DBG_TIM17_STOP
description: DBG_TIM17_STOP
bit_offset: 18
bit_size: 1
fieldset/C2APB1FZR1:
description: "DBGMCU CPU2 APB1 Peripheral Freeze Register 1 [dual core device"
fields:
- name: DBG_TIM2_STOP
description: DBG_TIM2_STOP
bit_offset: 0
bit_size: 1
- name: DBG_RTC_STOP
description: DBG_RTC_STOP
bit_offset: 10
bit_size: 1
- name: DBG_IWDG_STOP
description: DBG_IWDG_STOP
bit_offset: 12
bit_size: 1
- name: DBG_I2C1_STOP
description: DBG_I2C1_STOP
bit_offset: 21
bit_size: 1
- name: DBG_I2C2_STOP
description: DBG_I2C2_STOP
bit_offset: 22
bit_size: 1
- name: DBG_I2C3_STOP
description: DBG_I2C3_STOP
bit_offset: 23
bit_size: 1
- name: DBG_LPTIM1_STOP
description: DBG_LPTIM1_STOP
bit_offset: 31
bit_size: 1
fieldset/C2APB1FZR2:
description: "DBGMCU CPU2 APB1 Peripheral Freeze Register 2 [dual core device"
fields:
- name: DBG_LPTIM2_STOP
description: DBG_LPTIM2_STOP
bit_offset: 5
bit_size: 1
- name: DBG_LPTIM3_STOP
description: DBG_LPTIM3_STOP
bit_offset: 6
bit_size: 1
fieldset/C2APB2FZR:
description: "DBGMCU CPU2 APB2 Peripheral Freeze Register [dual core device"
fields:
- name: DBG_TIM1_STOP
description: DBG_TIM1_STOP
bit_offset: 11
bit_size: 1
- name: DBG_TIM16_STOP
description: DBG_TIM16_STOP
bit_offset: 17
bit_size: 1
- name: DBG_TIM17_STOP
description: DBG_TIM17_STOP
bit_offset: 18
bit_size: 1
fieldset/CR:
description: DBGMCU Configuration Register
fields:
- name: DBG_SLEEP
description: Allow debug in SLEEP mode
bit_offset: 0
bit_size: 1
- name: DBG_STOP
description: Allow debug in STOP mode
bit_offset: 1
bit_size: 1
- name: DBG_STANDBY
description: Allow debug in STANDBY mode
bit_offset: 2
bit_size: 1
fieldset/IDCODER:
description: DBGMCU Identity Code Register
fields:
- name: DEV_ID
description: Device ID
bit_offset: 0
bit_size: 12
- name: REV_ID
description: Revision
bit_offset: 16
bit_size: 16

0
data/registers/rcc_wl55.yaml → data/registers/rcc_wl5x.yaml
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0
data/registers/syscfg_wl55.yaml → data/registers/syscfg_wl5x.yaml
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7
parse.py
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@ -310,16 +310,17 @@ perimap = [
('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),
('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'),
('STM32WB55.*:SYS:.*', 'syscfg_wb55/SYSCFG'),
('STM32WL55.*:SYS:.*', 'syscfg_wl55/SYSCFG'),
('STM32WL.*:SYS:.*', 'syscfg_wl5x/SYSCFG'),
('STM32L0.*:RCC:.*', 'rcc_l0/RCC'),
('STM32L4.*:RCC:.*', 'rcc_l4/RCC'),
('STM32F4.*:RCC:.*', 'rcc_f4/RCC'),
('STM32WL.*:RCC:.*', 'rcc_wl55/RCC'),
('STM32WL.*:RCC:.*', 'rcc_wl5x/RCC'),
('.*:STM32H7AB_rcc_v1_0', ''), # rcc_h7ab/RCC
('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'),
('.*:STM32W_rcc_v1_0', 'rcc_wb55/RCC'),
('.*:STM32L0_dbgmcu_v1_0', 'dbg_l0/DBG'),
('.*:STM32L0_crs_v1_0', 'crs_l0/CRS'),
('.*:STM32WL_dbgmcu_v1_0', 'dbgmcu_wl5x/DBGMCU'),
('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'),
('.*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'),
('.*:STM32H7_flash_v1_0', 'flash_h7/FLASH'),
@ -334,7 +335,7 @@ rng_clock_map = [
('STM32F4.*:RNG:.*', 'AHB2'),
('STM32H7.*:RNG:.*', 'AHB2'),
('STM32WB55.*:RNG:.*', 'AHB3'),
('STM32WL55.*:RNG:.*', 'AHB3')
('STM32WL5.*:RNG:.*', 'AHB3')
]
def match_peri(peri):