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G0 SYSCFG: fix PA11/PA12 RMP definitions

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It looks like the G0 file here picked up the F0-style "one remapping bit
for both pins" field definition. The G0 series actually has C0-style
dual remapping bits.
This commit is contained in:
Cliff L. Biffle 2023-06-27 21:54:32 -07:00
parent 860255746d
commit 3d86ef6d30
1 changed files with 6 additions and 2 deletions
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8
data/registers/syscfg_g0.yaml
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@ -186,8 +186,12 @@ fieldset/CFGR1:
bit_offset: 0
bit_size: 2
enum: MEM_MODE
- name: PA11_PA12_RMP
description: PA11 and PA12 remapping bit.
- name: PA11_RMP
description: "PA11 pin remapping\r This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port."
bit_offset: 3
bit_size: 1
- name: PA12_RMP
description: "PA12 pin remapping\r This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port."
bit_offset: 4
bit_size: 1
- name: IR_POL