From 3cc1a1603e61881a6f0a1a47c12c16c57c245ba8 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Wed, 14 Feb 2024 17:23:30 +0100 Subject: [PATCH] rcc: fix wrong usart1 mux in f0, f3. --- data/registers/rcc_f0v1.yaml | 17 ++++++++++++++++- data/registers/rcc_f0v2.yaml | 17 ++++++++++++++++- data/registers/rcc_f0v3.yaml | 17 ++++++++++++++++- data/registers/rcc_f0v4.yaml | 17 ++++++++++++++++- data/registers/rcc_f3v1.yaml | 17 ++++++++++++++++- data/registers/rcc_f3v2.yaml | 17 ++++++++++++++++- data/registers/rcc_f3v3.yaml | 17 ++++++++++++++++- 7 files changed, 112 insertions(+), 7 deletions(-) diff --git a/data/registers/rcc_f0v1.yaml b/data/registers/rcc_f0v1.yaml index 1841c9f..ddff3ec 100644 --- a/data/registers/rcc_f0v1.yaml +++ b/data/registers/rcc_f0v1.yaml @@ -494,7 +494,7 @@ fieldset/CFGR3: description: USART1 clock source selection bit_offset: 0 bit_size: 2 - enum: USARTSW + enum: USART1SW - name: I2C1SW description: I2C1 clock source selection bit_offset: 4 @@ -972,6 +972,21 @@ enum/SW: - name: PLL1_P description: PLL used as system clock value: 2 +enum/USART1SW: + bit_size: 2 + variants: + - name: PCLK2 + description: PCLK selected as USART clock source + value: 0 + - name: SYS + description: SYSCLK selected as USART clock source + value: 1 + - name: LSE + description: LSE selected as USART clock source + value: 2 + - name: HSI + description: HSI selected as USART clock source + value: 3 enum/USARTSW: bit_size: 2 variants: diff --git a/data/registers/rcc_f0v2.yaml b/data/registers/rcc_f0v2.yaml index 077b05d..b6773ad 100644 --- a/data/registers/rcc_f0v2.yaml +++ b/data/registers/rcc_f0v2.yaml @@ -504,7 +504,7 @@ fieldset/CFGR3: description: USART1 clock source selection bit_offset: 0 bit_size: 2 - enum: USARTSW + enum: USART1SW - name: I2C1SW description: I2C1 clock source selection bit_offset: 4 @@ -1018,6 +1018,21 @@ enum/SW: - name: PLL1_P description: PLL used as system clock value: 2 +enum/USART1SW: + bit_size: 2 + variants: + - name: PCLK2 + description: PCLK selected as USART clock source + value: 0 + - name: SYS + description: SYSCLK selected as USART clock source + value: 1 + - name: LSE + description: LSE selected as USART clock source + value: 2 + - name: HSI + description: HSI selected as USART clock source + value: 3 enum/USARTSW: bit_size: 2 variants: diff --git a/data/registers/rcc_f0v3.yaml b/data/registers/rcc_f0v3.yaml index b7a2e79..61f3aa8 100644 --- a/data/registers/rcc_f0v3.yaml +++ b/data/registers/rcc_f0v3.yaml @@ -504,7 +504,7 @@ fieldset/CFGR3: description: USART1 clock source selection bit_offset: 0 bit_size: 2 - enum: USARTSW + enum: USART1SW - name: I2C1SW description: I2C1 clock source selection bit_offset: 4 @@ -1021,6 +1021,21 @@ enum/SW: - name: PLL1_P description: PLL used as system clock value: 2 +enum/USART1SW: + bit_size: 2 + variants: + - name: PCLK2 + description: PCLK selected as USART clock source + value: 0 + - name: SYS + description: SYSCLK selected as USART clock source + value: 1 + - name: LSE + description: LSE selected as USART clock source + value: 2 + - name: HSI + description: HSI selected as USART clock source + value: 3 enum/USARTSW: bit_size: 2 variants: diff --git a/data/registers/rcc_f0v4.yaml b/data/registers/rcc_f0v4.yaml index 802ee04..299c451 100644 --- a/data/registers/rcc_f0v4.yaml +++ b/data/registers/rcc_f0v4.yaml @@ -504,7 +504,7 @@ fieldset/CFGR3: description: USART1 clock source selection bit_offset: 0 bit_size: 2 - enum: USARTSW + enum: USART1SW - name: I2C1SW description: I2C1 clock source selection bit_offset: 4 @@ -1054,6 +1054,21 @@ enum/SW: - name: HSI48 description: HSI48 used as system clock value: 3 +enum/USART1SW: + bit_size: 2 + variants: + - name: PCLK2 + description: PCLK selected as USART clock source + value: 0 + - name: SYS + description: SYSCLK selected as USART clock source + value: 1 + - name: LSE + description: LSE selected as USART clock source + value: 2 + - name: HSI + description: HSI selected as USART clock source + value: 3 enum/USARTSW: bit_size: 2 variants: diff --git a/data/registers/rcc_f3v1.yaml b/data/registers/rcc_f3v1.yaml index 01dcdad..05884b4 100644 --- a/data/registers/rcc_f3v1.yaml +++ b/data/registers/rcc_f3v1.yaml @@ -581,7 +581,7 @@ fieldset/CFGR3: description: USART1 clock source selection bit_offset: 0 bit_size: 2 - enum: USARTSW + enum: USART1SW - name: I2C1SW description: I2C1 clock source selection bit_offset: 4 @@ -1149,6 +1149,21 @@ enum/TIMSW: - name: PLL1_P description: PLL vco output (running up to 144 MHz) value: 1 +enum/USART1SW: + bit_size: 2 + variants: + - name: PCLK2 + description: PCLK selected as USART clock source + value: 0 + - name: SYS + description: SYSCLK selected as USART clock source + value: 1 + - name: LSE + description: LSE selected as USART clock source + value: 2 + - name: HSI + description: HSI selected as USART clock source + value: 3 enum/USARTSW: bit_size: 2 variants: diff --git a/data/registers/rcc_f3v2.yaml b/data/registers/rcc_f3v2.yaml index 30367f3..a29aec4 100644 --- a/data/registers/rcc_f3v2.yaml +++ b/data/registers/rcc_f3v2.yaml @@ -587,7 +587,7 @@ fieldset/CFGR3: description: USART1 clock source selection bit_offset: 0 bit_size: 2 - enum: USARTSW + enum: USART1SW - name: I2C1SW description: I2C1 clock source selection bit_offset: 4 @@ -1191,6 +1191,21 @@ enum/TIMSW: - name: PLL1_P description: PLL vco output (running up to 144 MHz) value: 1 +enum/USART1SW: + bit_size: 2 + variants: + - name: PCLK2 + description: PCLK selected as USART clock source + value: 0 + - name: SYS + description: SYSCLK selected as USART clock source + value: 1 + - name: LSE + description: LSE selected as USART clock source + value: 2 + - name: HSI + description: HSI selected as USART clock source + value: 3 enum/USARTSW: bit_size: 2 variants: diff --git a/data/registers/rcc_f3v3.yaml b/data/registers/rcc_f3v3.yaml index 0514713..45af5db 100644 --- a/data/registers/rcc_f3v3.yaml +++ b/data/registers/rcc_f3v3.yaml @@ -587,7 +587,7 @@ fieldset/CFGR3: description: USART1 clock source selection bit_offset: 0 bit_size: 2 - enum: USARTSW + enum: USART1SW - name: I2C1SW description: I2C1 clock source selection bit_offset: 4 @@ -1194,6 +1194,21 @@ enum/TIMSW: - name: PLL1_P description: PLL vco output (running up to 144 MHz) value: 1 +enum/USART1SW: + bit_size: 2 + variants: + - name: PCLK2 + description: PCLK selected as USART clock source + value: 0 + - name: SYS + description: SYSCLK selected as USART clock source + value: 1 + - name: LSE + description: LSE selected as USART clock source + value: 2 + - name: HSI + description: HSI selected as USART clock source + value: 3 enum/USARTSW: bit_size: 2 variants: