From 3b6363dffba6403af92eda44d4de6e1f7eb9e16d Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Thu, 19 Aug 2021 22:37:07 +0200
Subject: [PATCH] wl rcc: rename SPI2S2 -> SPI2

---
 data/registers/rcc_wl5.yaml | 24 ++++++++++++------------
 data/registers/rcc_wle.yaml | 16 ++++++++--------
 2 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/data/registers/rcc_wl5.yaml b/data/registers/rcc_wl5.yaml
index 8537225..828c986 100644
--- a/data/registers/rcc_wl5.yaml
+++ b/data/registers/rcc_wl5.yaml
@@ -398,8 +398,8 @@ fieldset/APB1ENR1:
       description: CPU1 Window watchdog clock enable
       bit_offset: 11
       bit_size: 1
-    - name: SPI2S2EN
-      description: CPU1 SPI2S2 clock enable
+    - name: SPI2EN
+      description: CPU1 SPI2 clock enable
       bit_offset: 14
       bit_size: 1
     - name: USART2EN
@@ -448,8 +448,8 @@ fieldset/APB1RSTR1:
       description: TIM2 timer reset
       bit_offset: 0
       bit_size: 1
-    - name: SPI2S2RST
-      description: SPI2S2 reset
+    - name: SPI2RST
+      description: SPI2 reset
       bit_offset: 14
       bit_size: 1
     - name: USART2RST
@@ -506,8 +506,8 @@ fieldset/APB1SMENR1:
       description: Window watchdog clocks enable during CPU1 CSleep mode.
       bit_offset: 11
       bit_size: 1
-    - name: SPI2S2SMEN
-      description: SPI2S2 clock enable during CPU1 CSleep mode.
+    - name: SPI2SMEN
+      description: SPI2 clock enable during CPU1 CSleep mode.
       bit_offset: 14
       bit_size: 1
     - name: USART2SMEN
@@ -847,8 +847,8 @@ fieldset/C2APB1ENR1:
       description: CPU2 RTC APB clock enable
       bit_offset: 10
       bit_size: 1
-    - name: SPI2S2EN
-      description: CPU2 SPI2S2 clock enable
+    - name: SPI2EN
+      description: CPU2 SPI2 clock enable
       bit_offset: 14
       bit_size: 1
     - name: USART2EN
@@ -901,8 +901,8 @@ fieldset/C2APB1SMENR1:
       description: RTC bus clock enable during CPU2 CSleep mode.
       bit_offset: 10
       bit_size: 1
-    - name: SPI2S2SMEN
-      description: SPI2S2 clock enable during CPU2 CSleep mode.
+    - name: SPI2SMEN
+      description: SPI2 clock enable during CPU2 CSleep mode.
       bit_offset: 14
       bit_size: 1
     - name: USART2SMEN
@@ -1023,8 +1023,8 @@ fieldset/CCIPR:
       description: USART2 clock source selection
       bit_offset: 2
       bit_size: 2
-    - name: SPI2S2SEL
-      description: SPI2S2 I2S clock source selection
+    - name: SPI2SEL
+      description: SPI2 I2S clock source selection
       bit_offset: 8
       bit_size: 2
     - name: LPUART1SEL
diff --git a/data/registers/rcc_wle.yaml b/data/registers/rcc_wle.yaml
index ce21b21..c130d96 100644
--- a/data/registers/rcc_wle.yaml
+++ b/data/registers/rcc_wle.yaml
@@ -334,8 +334,8 @@ fieldset/APB1ENR1:
       description: CPU1 Window watchdog clock enable
       bit_offset: 11
       bit_size: 1
-    - name: SPI2S2EN
-      description: CPU1 SPI2S2 clock enable
+    - name: SPI2EN
+      description: CPU1 SPI2 clock enable
       bit_offset: 14
       bit_size: 1
     - name: USART2EN
@@ -384,8 +384,8 @@ fieldset/APB1RSTR1:
       description: TIM2 timer reset
       bit_offset: 0
       bit_size: 1
-    - name: SPI2S2RST
-      description: SPI2S2 reset
+    - name: SPI2RST
+      description: SPI2 reset
       bit_offset: 14
       bit_size: 1
     - name: USART2RST
@@ -442,8 +442,8 @@ fieldset/APB1SMENR1:
       description: Window watchdog clocks enable during CPU1 CSleep mode.
       bit_offset: 11
       bit_size: 1
-    - name: SPI2S2SMEN
-      description: SPI2S2 clock enable during CPU1 CSleep mode.
+    - name: SPI2SMEN
+      description: SPI2 clock enable during CPU1 CSleep mode.
       bit_offset: 14
       bit_size: 1
     - name: USART2SMEN
@@ -653,8 +653,8 @@ fieldset/CCIPR:
       description: USART2 clock source selection
       bit_offset: 2
       bit_size: 2
-    - name: SPI2S2SEL
-      description: SPI2S2 I2S clock source selection
+    - name: SPI2SEL
+      description: SPI2 I2S clock source selection
       bit_offset: 8
       bit_size: 2
     - name: LPUART1SEL