aaaaa

data/registers/rcc_f37.yaml

@@ -558,7 +558,7 @@ fieldset/CFGR3:
     description: USART1 clock source selection
     bit_offset: 0
     bit_size: 2
-    enum: USARTSW
+    enum: USART1SW
   - name: I2C1SW
     description: I2C1 clock source selection
     bit_offset: 4
@@ -1177,6 +1177,21 @@ enum/TIMSW:
   - name: PLL1_P
     description: PLL vco output (running up to 144 MHz)
     value: 1
+enum/USART1SW:
+  bit_size: 2
+  variants:
+  - name: PCLK2
+    description: PCLK selected as USART clock source
+    value: 0
+  - name: SYS
+    description: SYSCLK selected as USART clock source
+    value: 1
+  - name: LSE
+    description: LSE selected as USART clock source
+    value: 2
+  - name: HSI
+    description: HSI selected as USART clock source
+    value: 3
 enum/USARTSW:
   bit_size: 2
   variants: