diff --git a/data/extra/chip_name/STM32F303CB.yaml b/data/extra/chip_name/STM32F303CB.yaml new file mode 100644 index 0000000..981a349 --- /dev/null +++ b/data/extra/chip_name/STM32F303CB.yaml @@ -0,0 +1,8 @@ +--- +peripherals: + - name: ADC3_COMMON + address: 0x50000700 + registers: + kind: adccommon + version: f3 + block: ADCCOMMON diff --git a/data/extra/chip_name/STM32F303CC.yaml b/data/extra/chip_name/STM32F303CC.yaml new file mode 100644 index 0000000..981a349 --- /dev/null +++ b/data/extra/chip_name/STM32F303CC.yaml @@ -0,0 +1,8 @@ +--- +peripherals: + - name: ADC3_COMMON + address: 0x50000700 + registers: + kind: adccommon + version: f3 + block: ADCCOMMON diff --git a/data/extra/chip_name/STM32F303VC.yaml b/data/extra/chip_name/STM32F303VC.yaml new file mode 100644 index 0000000..981a349 --- /dev/null +++ b/data/extra/chip_name/STM32F303VC.yaml @@ -0,0 +1,8 @@ +--- +peripherals: + - name: ADC3_COMMON + address: 0x50000700 + registers: + kind: adccommon + version: f3 + block: ADCCOMMON diff --git a/data/registers/adccommon_f3.yaml b/data/registers/adccommon_f3.yaml new file mode 100644 index 0000000..6dded6d --- /dev/null +++ b/data/registers/adccommon_f3.yaml @@ -0,0 +1,375 @@ +--- +block/ADC_COMMON: + description: ADC common registers + items: + - name: CSR + description: ADC Common status register + byte_offset: 0 + access: Read + fieldset: CSR + - name: CCR + description: ADC common control register + byte_offset: 8 + fieldset: CCR + - name: CDR + description: ADC common regular data register for dual and triple modes + byte_offset: 12 + access: Read + fieldset: CDR +fieldset/CSR: + decsription: ADC common status register + fields: + - name: ADRDY_MST + description: Master ADC ready + bit_offset: 0 + bit_size: 1 + enum: ADRDY + - name: EOSMP_MST + description: End of sampling phase flag of the master ADC + bit_offset: 1 + bit_size: 1 + enum: EOSMP + - name: EOC_MST + description: End of regular conversion of the master ADC + bit_offset: 2 + bit_size: 1 + enum: EOC + - name: EOS_MST + description: End of regular sequence flag of the master ADC + bit_offset: 3 + bit_size: 1 + enum: EOS + - name: OVR_MST + description: Overrun flag of the master ADC + bit_offset: 4 + bit_size: 1 + enum: OVR + - name: JEOC_MST + description: End of injected conversion of the master ADC + bit_offset: 5 + bit_size: 1 + enum: JEOC + - name: JEOS + description: End of injected sequence flag of the master ADC + bit_offset: 6 + bit_size: 1 + enum: JEOS + - name: AWD1_MST + description: Analog watchdog 1 flag of the master ADC + bit_offset: 7 + bit_size: 1 + enum: AWD + - name: AWD2_MST + description: Analog watchdog 2 flag of the master ADC + bit_offset: 8 + bit_size: 1 + enum: AWD + - name: AWD3_MST + description: Analog watchdog 3 flag of the master ADC + bit_offset: 9 + bit_size: 1 + enum: AWD + - name: JQOVF_MST + description: Injected context queue overflow flag of the master ADC + bit_offset: 10 + bit_size: 1 + enum: JQOVF + - name: ADRDY_SLV + description: Slave ADC ready + bit_offset: 16 + bit_size: 1 + enum: ADRDY + - name: EOSMP_SLV + description: End of sampling phase flag of the slave ADC + bit_offset: 17 + bit_size: 1 + enum: EOSMP + - name: EOC_SLV + description: End of regular conversion of the slave ADC + bit_offset: 18 + bit_size: 1 + enum: EOC + - name: EOS_SLV + description: End of regular sequence flag of the slave ADC + bit_offset: 19 + bit_size: 1 + enum: EOS + - name: OVR_SLV + description: Overrun flag of the slave ADC + bit_offset: 20 + bit_size: 1 + enum: OVR + - name: JEOC_SLV + description: End of injected conversion of the slave ADC + bit_offset: 21 + bit_size: 1 + enum: JEOC + - name: JEOS_SLV + description: End of injected sequence flag of the slave ADC + bit_offset: 22 + bit_size: 1 + enum: JEOS + - name: AWD1_SLV + description: Analog watchdog 1 flag of the slave ADC + bit_offset: 23 + bit_size: 1 + enum: AWD + - name: AWD2_SLV + description: Analog watchdog 2 flag of the slave ADC + bit_offset: 24 + bit_size: 1 + enum: AWD + - name: AWD3_SLV + description: Analog watchdog 3 flag of the slave ADC + bit_offset: 25 + bit_size: 1 + enum: AWD + - name: JQOVF_SLV + description: Injected context queue overflow flag of the slave ADC + bit_offset: 26 + bit_size: 1 + enum: JQOVF +fieldset/CCR: + description: ADC common control register + fields: + - name: DUAL + description: Dual ADC mode selection + bit_offset: 0 + bit_size: 5 + enum: DUAL + - name: DELAY + description: Delay between 2 sampling phases + bit_offset: 8 + bit_size: 4 + - name: DMACFG + description: DMA configuration (for multi-ADC mode) + bit_offset: 13 + bit_size: 1 + enum: DMACFG + - name: MDMA + description: Direct memory access mode for multi ADC mode + bit_offset: 14 + bit_size: 2 + enum: MDMA + - name: CKMODE + description: ADC clock mode + bit_offset: 16 + bit_size: 2 + enum: CKMODE + - name: VREFEN + description: VREFINT enable + bit_offset: 22 + bit_size: 1 + enum: VREFEN + - name: TSEN + description: Temperature sensor enable + bit_offset: 23 + bit_size: 1 + enum: TSEN + - name: VBATEN + description: VBAT enable + bit_offset: 24 + bit_size: 1 + enum: VBATEN +fieldset/CDR: + description: ADC common regular data register for dual and triple modes + fields: + - name: RDATA_MST + description: Regular data of the master ADC + bit_offset: 0 + bit_size: 16 + - name: RDATA_SLV + description: Regular data of the master ADC + bit_offset: 16 + bit_size: 16 +enum/ADRDY: + description: ADC ready + bit_size: 1 + variants: + - name: NotReady + value: 0 + description: ADC is not ready to start conversion + - name: Ready + value: 1 + description: ADC is ready to start conversion +enum/EOSMP: + description: End of sampling flag + bit_size: 1 + variants: + - name: NotEnded + value: 0 + description: Conversion is not ended + - name: Ended + value: 1 + description: Conversion is ended +enum/EOC: + description: End of regular conversion + bit_size: 1 + variants: + - name: NotEnded + value: 0 + description: Regular conversion is not complete + - name: Ended + value: 1 + description: Regular conversion complete +enum/EOS: + description: End of regular sequence flag + bit_size: 1 + variants: + - name: NotEnded + value: 0 + description: Regular sequence is not complete + - name: Ended + value: 1 + description: Regular sequence complete +enum/OVR: + description: Overrun flag + bit_size: 1 + variants: + - name: NoOverrun + value: 0 + description: No overrun occurred + - name: Overrun + value: 1 + description: Overrun occurred +enum/JEOC: + description: End of injected conversion flag + bit_size: 1 + variants: + - name: NotEnded + value: 0 + description: Injected conversion is not complete + - name: Ended + value: 1 + description: Injected conversion complete +enum/JEOS: + description: End of injected sequence flag + bit_size: 1 + variants: + - name: NotEnded + value: 0 + description: Injected sequence is not complete + - name: Ended + value: 1 + description: Injected sequence complete +enum/AWD: + description: Analog watchdog flag + bit_size: 1 + variants: + - name: NoEvent + value: 0 + description: No analog watchdog event occurred + - name: Event + value: 1 + description: Analog watchdog event occurred +enum/JQOVF: + description: Injected context queue overflow flag + bit_size: 1 + variants: + - name: NoOverflow + value: 0 + description: No injected context queue overflow + - name: Overflow + value: 1 + description: Injected context queue overflow +enum/DUAL: + description: Dual ADC mode selection + bit_size: 5 + variants: + - name: Independent + value: 0 + description: Independent mode + - name: DualRJ + value: 1 + description: Dual, combined regular simultaneous + injected simultaneous mode + - name: DualRA + value: 2 + description: Dual, combined regular simultaneous + alternate trigger mode + - name: DualIJ + value: 3 + description: Dual, combined injected simultaneous + fast interleaved mode + - name: DualJ + value: 5 + description: Dual, injected simultaneous mode only + - name: DualR + value: 6 + description: Dual, regular simultaneous mode only + - name: DualI + value: 7 + description: dual, interleaved mode only + - name: DualA + value: 9 + description: Dual, alternate trigger mode only +enum/DMACFG: + description: DMA configuration (for multi-ADC mode) + bit_size: 1 + variants: + - name: OneShot + value: 0 + description: DMA one shot mode selected + - name: Circulator + value: 1 + description: DMA circular mode selected +enum/MDMA: + description: Direct memory access mode for multi ADC mode + bit_size: 2 + variants: + - name: Disabled + value: 0 + description: MDMA mode disabled + - name: Bits12_10 + value: 2 + description: MDMA mode enabled for 12 and 10-bit resolution + - name: Bit8_6 + value: 3 + description: MDMA mode enabled for 8 and 6-bit resolution +enum/CKMODE: + description: ADC clock mode + bit_size: 2 + variants: + - name: Asynchronous + value: 0 + description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous mode + - name: SyncDiv1 + value: 1 + description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck. + - name: SyncDiv2 + value: 2 + description: Use AHB clock rcc_hclk3 divided by 2. + - name: SyncDiv4 + value: 3 + description: Use AHB clock rcc_hclk3 divided by 4. +enum/VREFEN: + description: VREFINT enable + bit_size: 1 + variants: + - name: Disabled + value: 0 + description: VREFINT channel disabled + - name: Enabled + value: 1 + description: VREFINT channel enabled +enum/TSEN: + description: Temperature sensor enable + bit_size: 1 + variants: + - name: Disabled + value: 0 + description: Temperature sensor channel disabled + - name: Enabled + value: 1 + description: Temperature sensor channel enabled +enum/VBATEN: + description: VBAT enable + bit_size: 1 + variants: + - name: Disabled + value: 0 + description: VBAT channel disabled + - name: Enabled + value: 1 + description: VBAT channel enabled + + + + \ No newline at end of file diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 99a5582..c005481 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -183,6 +183,7 @@ impl PeriMatcher { (".*:ADC_COMMON:aditf5_v2_0", ("adccommon", "v3", "ADC_COMMON")), (".*:ADC_COMMON:aditf5_v2_2", ("adccommon", "v3", "ADC_COMMON")), (".*:ADC_COMMON:aditf4_v3_0_WL", ("adccommon", "v3", "ADC_COMMON")), + (".*:ADC_COMMON:aditf5_v1_1", ("adccommon", "f3", "ADC_COMMON")), ("STM32H7.*:ADC_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")), ("STM32H7.*:ADC3_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")), (".*:DCMI:.*", ("dcmi", "v1", "DCMI")), @@ -823,7 +824,7 @@ fn process_core( entry.insert(format!("ADC_COMMON:{}", ip.version.strip_suffix("_Cube").unwrap())); } } - if pname.starts_with("ADC3") && chip_name.starts_with("STM32H7") { + if pname.starts_with("ADC3") && (chip_name.starts_with("STM32H7")) { if let Entry::Vacant(entry) = peri_kinds.entry("ADC3_COMMON".to_string()) { entry.insert(format!("ADC3_COMMON:{}", ip.version.strip_suffix("_Cube").unwrap())); } @@ -1007,6 +1008,17 @@ fn process_core( peripherals.push(p); } } + if let Ok(extra_f) = std::fs::read(format!("data/extra/chip_name/{}.yaml", chip_name)) { + #[derive(serde::Deserialize)] + struct Extra { + peripherals: Vec, + } + + let extra: Extra = serde_yaml::from_slice(&extra_f).unwrap(); + for p in extra.peripherals { + peripherals.push(p); + } + } peripherals.sort_by_key(|x| x.name.clone()); let have_peris: HashSet<_> = peripherals.iter_mut().map(|p| p.name.clone()).collect(); // Collect DMA versions in the chip