Use normalize for SBS->SYSCFG rename.

data/registers/rcc_h5.yaml

@@ -1187,7 +1187,7 @@ fieldset/APB2RSTR:
 fieldset/APB3ENR:
   description: RCC APB3 peripheral clock register
   fields:
-  - name: SBSEN
+  - name: SYSCFGEN
     description: "SBS clock enable\r Set and reset by software."
     bit_offset: 1
     bit_size: 1
@@ -1238,7 +1238,7 @@ fieldset/APB3ENR:
 fieldset/APB3LPENR:
   description: RCC APB3 sleep clock register
   fields:
-  - name: SBSLPEN
+  - name: SYSCFGLPEN
     description: "SBS clock enable during sleep mode\r Set and reset by software."
     bit_offset: 1
     bit_size: 1
@@ -1289,7 +1289,7 @@ fieldset/APB3LPENR:
 fieldset/APB3RSTR:
   description: RCC APB3 peripheral reset register
   fields:
-  - name: SBSRST
+  - name: SYSCFGRST
     description: "SBS block reset\r Set and reset by software."
     bit_offset: 1
     bit_size: 1

data/registers/rcc_h50.yaml

@@ -658,7 +658,7 @@ fieldset/APB2RSTR:
 fieldset/APB3ENR:
   description: RCC APB3 peripheral clock register
   fields:
-  - name: SBSEN
+  - name: SYSCFGEN
     description: "SBS clock enable\r Set and reset by software."
     bit_offset: 1
     bit_size: 1
@@ -685,7 +685,7 @@ fieldset/APB3ENR:
 fieldset/APB3LPENR:
   description: RCC APB3 sleep clock register
   fields:
-  - name: SBSLPEN
+  - name: SYSCFGLPEN
     description: "SBS clock enable during sleep mode\r Set and reset by software."
     bit_offset: 1
     bit_size: 1
@@ -712,7 +712,7 @@ fieldset/APB3LPENR:
 fieldset/APB3RSTR:
   description: RCC APB3 peripheral reset register
   fields:
-  - name: SBSRST
+  - name: SYSCFGRST
     description: "SBS block reset\r Set and reset by software."
     bit_offset: 1
     bit_size: 1

stm32-data-gen/src/chips.rs

@@ -258,8 +258,8 @@ impl PeriMatcher {
             ("STM32WB.*:SYSCFG:.*", ("syscfg", "wb", "SYSCFG")),
             ("STM32WL5.*:SYSCFG:.*", ("syscfg", "wl5", "SYSCFG")),
             ("STM32WLE.*:SYSCFG:.*", ("syscfg", "wle", "SYSCFG")),
-            ("STM32H50.*:SBS:.*", ("syscfg", "h50", "SYSCFG")),
-            ("STM32H5.*:SBS:.*", ("syscfg", "h5", "SYSCFG")),
+            ("STM32H50.*:SYSCFG:.*", ("syscfg", "h50", "SYSCFG")),
+            ("STM32H5.*:SYSCFG:.*", ("syscfg", "h5", "SYSCFG")),
             (".*:IWDG:iwdg1_v1_1", ("iwdg", "v1", "IWDG")),
             (".*:IWDG:iwdg1_v2_0", ("iwdg", "v2", "IWDG")),
             (".*:IWDG:iwdg1_v3_0", ("iwdg", "v3", "IWDG")),
@@ -1182,11 +1182,7 @@ fn process_core(
         let Some(addr) = addr else { continue };
 
         let mut p = stm32_data_serde::chip::core::Peripheral {
-            name: if pname == "SBS" {
-                "SYSCFG".to_string()
-            } else {
-                pname.clone()
-            },
+            name: pname.clone(),
             address: addr,
             registers: None,
             rcc: None,

stm32-data-gen/src/header.rs

@@ -192,6 +192,7 @@ impl Defines {
             ("FDCANRAM", &["SRAMCAN_BASE", "SRAMCAN_BASE_NS"]),
             ("VREFINTCAL", &["VREFINT_CAL_ADDR_CMSIS"]),
             ("DSIHOST", &["DSI_BASE"]),
+            ("SYSCFG", &["SYSCFG_BASE", "SBS_BASE"]),
         ];
         let alt_peri_defines: HashMap<_, _> = ALT_PERI_DEFINES.iter().copied().collect();
 

stm32-data-gen/src/normalize_peris.rs

@@ -5,6 +5,7 @@ static NORMALIZE: &[(&str, &str)] = &[
     ("HDMI_CEC", "CEC"),
     ("SUBGHZ", "SUBGHZSPI"),
     ("USB_DRD_FS", "USB"),
+    ("SBS", "SYSCFG"),
 ];
 
 pub fn normalize_peri_name(name: &str) -> &str {