diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index ad247b0..f73cae8 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -321,24 +321,20 @@ fieldset/AHB1ENR: description: Ethernet Reception Clock Enable bit_offset: 17 bit_size: 1 - - name: USB2OTGHSULPIEN - description: Enable USB_PHY2 clocks - bit_offset: 18 - bit_size: 1 - - name: USB1OTGEN - description: USB1OTG Peripheral Clocks Enable + - name: USB_OTG_HSEN + description: USB_OTG_HS Peripheral Clocks Enable bit_offset: 25 bit_size: 1 - - name: USB1ULPIEN - description: USB_PHY1 Clocks Enable + - name: USB_OTG_HS_ULPIEN + description: USB_OTG_HS ULPI clock enable bit_offset: 26 bit_size: 1 - - name: USB2OTGEN - description: USB2OTG Peripheral Clocks Enable + - name: USB_OTG_FSEN + description: USB_OTG_FS Peripheral Clocks Enable bit_offset: 27 bit_size: 1 - - name: USB2ULPIEN - description: USB_PHY2 Clocks Enable + - name: USB_OTG_FS_ULPIEN + description: USB_OTG_FS ULPI clock enable bit_offset: 28 bit_size: 1 fieldset/AHB1LPENR: @@ -372,11 +368,11 @@ fieldset/AHB1LPENR: description: Ethernet Reception Clock Enable During CSleep Mode bit_offset: 17 bit_size: 1 - - name: USB1OTGLPEN - description: USB1OTG peripheral clock enable during CSleep mode + - name: USB_OTG_HSLPEN + description: USB_OTG_HS peripheral clock enable during CSleep mode bit_offset: 25 bit_size: 1 - - name: USB1OTGHSULPILPEN + - name: USB_OTG_HSHSULPILPEN description: USB_PHY1 clock enable during CSleep mode bit_offset: 26 bit_size: 1 @@ -384,11 +380,11 @@ fieldset/AHB1LPENR: description: USB_PHY1 clock enable during CSleep mode bit_offset: 26 bit_size: 1 - - name: USB2OTGLPEN - description: USB2OTG peripheral clock enable during CSleep mode + - name: USB_OTG_FSLPEN + description: USB_OTG_FS peripheral clock enable during CSleep mode bit_offset: 27 bit_size: 1 - - name: USB2OTGHSULPILPEN + - name: USB_OTG_FSHSULPILPEN description: USB_PHY2 clocks enable during CSleep mode bit_offset: 28 bit_size: 1 @@ -419,12 +415,12 @@ fieldset/AHB1RSTR: description: ETH1MAC block reset bit_offset: 15 bit_size: 1 - - name: USB1OTGRST - description: USB1OTG block reset + - name: USB_OTG_HSRST + description: USB_OTG_HS block reset bit_offset: 25 bit_size: 1 - - name: USB2OTGRST - description: USB2OTG block reset + - name: USB_OTG_FSRST + description: USB_OTG_FS block reset bit_offset: 27 bit_size: 1 fieldset/AHB2ENR: @@ -1811,16 +1807,16 @@ fieldset/C1_AHB1ENR: description: Ethernet Reception Clock Enable bit_offset: 17 bit_size: 1 - - name: USB1OTGEN - description: USB1OTG Peripheral Clocks Enable + - name: USB_OTG_HSEN + description: USB_OTG_HS Peripheral Clocks Enable bit_offset: 25 bit_size: 1 - name: USB1ULPIEN description: USB_PHY1 Clocks Enable bit_offset: 26 bit_size: 1 - - name: USB2OTGEN - description: USB2OTG Peripheral Clocks Enable + - name: USB_OTG_FSEN + description: USB_OTG_FS Peripheral Clocks Enable bit_offset: 27 bit_size: 1 - name: USB2ULPIEN @@ -1858,16 +1854,16 @@ fieldset/C1_AHB1LPENR: description: Ethernet Reception Clock Enable During CSleep Mode bit_offset: 17 bit_size: 1 - - name: USB1OTGLPEN - description: USB1OTG peripheral clock enable during CSleep mode + - name: USB_OTG_HSLPEN + description: USB_OTG_HS peripheral clock enable during CSleep mode bit_offset: 25 bit_size: 1 - name: USB1ULPILPEN description: USB_PHY1 clock enable during CSleep mode bit_offset: 26 bit_size: 1 - - name: USB2OTGLPEN - description: USB2OTG peripheral clock enable during CSleep mode + - name: USB_OTG_FSLPEN + description: USB_OTG_FS peripheral clock enable during CSleep mode bit_offset: 27 bit_size: 1 - name: USB2ULPILPEN diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml index 05d1795..e8fc1be 100644 --- a/data/registers/rcc_h7ab.yaml +++ b/data/registers/rcc_h7ab.yaml @@ -245,24 +245,20 @@ fieldset/AHB1ENR: description: Ethernet Reception Clock Enable bit_offset: 17 bit_size: 1 - - name: USB2OTGHSULPIEN - description: Enable USB_PHY2 clocks - bit_offset: 18 - bit_size: 1 - - name: USB1OTGEN - description: USB1OTG Peripheral Clocks Enable + - name: USB_OTG_HSEN + description: USB_OTG_HS Peripheral Clocks Enable bit_offset: 25 bit_size: 1 - - name: USB1ULPIEN - description: USB_PHY1 Clocks Enable + - name: USB_OTG_HS_ULPIEN + description: USB_OTG_HS ULPI clock enable bit_offset: 26 bit_size: 1 - - name: USB2OTGEN - description: USB2OTG Peripheral Clocks Enable + - name: USB_OTG_FSEN + description: USB_OTG_FS Peripheral Clocks Enable bit_offset: 27 bit_size: 1 - - name: USB2ULPIEN - description: USB_PHY2 Clocks Enable + - name: USB_OTG_FS_ULPIEN + description: USB_OTG_FS ULPI clock enable bit_offset: 28 bit_size: 1 fieldset/AHB1LPENR: @@ -296,11 +292,11 @@ fieldset/AHB1LPENR: description: Ethernet Reception Clock Enable During CSleep Mode bit_offset: 17 bit_size: 1 - - name: USB1OTGLPEN - description: USB1OTG peripheral clock enable during CSleep mode + - name: USB_OTG_HSLPEN + description: USB_OTG_HS peripheral clock enable during CSleep mode bit_offset: 25 bit_size: 1 - - name: USB1OTGHSULPILPEN + - name: USB_OTG_HSHSULPILPEN description: USB_PHY1 clock enable during CSleep mode bit_offset: 26 bit_size: 1 @@ -308,11 +304,11 @@ fieldset/AHB1LPENR: description: USB_PHY1 clock enable during CSleep mode bit_offset: 26 bit_size: 1 - - name: USB2OTGLPEN - description: USB2OTG peripheral clock enable during CSleep mode + - name: USB_OTG_FSLPEN + description: USB_OTG_FS peripheral clock enable during CSleep mode bit_offset: 27 bit_size: 1 - - name: USB2OTGHSULPILPEN + - name: USB_OTG_FSHSULPILPEN description: USB_PHY2 clocks enable during CSleep mode bit_offset: 28 bit_size: 1 @@ -343,12 +339,12 @@ fieldset/AHB1RSTR: description: ETH1MAC block reset bit_offset: 15 bit_size: 1 - - name: USB1OTGRST - description: USB1OTG block reset + - name: USB_OTG_HSRST + description: USB_OTG_HS block reset bit_offset: 25 bit_size: 1 - - name: USB2OTGRST - description: USB2OTG block reset + - name: USB_OTG_FSRST + description: USB_OTG_FS block reset bit_offset: 27 bit_size: 1 fieldset/AHB2ENR: