Add F1 RCC
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data/registers/rcc_f1.yaml
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1478
data/registers/rcc_f1.yaml
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1
parse.py
1
parse.py
@ -323,6 +323,7 @@ perimap = [
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('STM32WL.*:RCC:.*', 'rcc_wl5x/RCC'),
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('STM32F0.0.*:RCC:.*', 'rcc_f0x0/RCC'),
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('STM32F0.*:RCC:.*', 'rcc_f0/RCC'),
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('STM32F1.*:RCC:.*', 'rcc_f1/RCC'),
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('.*:STM32H7AB_rcc_v1_0', ''), # rcc_h7ab/RCC
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('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'),
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('.*:STM32W_rcc_v1_0', 'rcc_wb55/RCC'),
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