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Add DMA

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This commit is contained in:
Dario Nieuwenhuis 2021-05-10 01:19:37 +02:00
parent 1b18ea01f9
commit 36726eab2f
1 changed files with 18 additions and 6 deletions
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24
parse.py
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@ -211,8 +211,8 @@ perimap = [
('UART:sci2_v1_2', 'usart_v1/UART'), ('UART:sci2_v1_2', 'usart_v1/UART'),
('UART:sci2_v1_2_F1', 'usart_v1/UART'), ('UART:sci2_v1_2_F1', 'usart_v1/UART'),
('UART:sci2_v2_1', 'usart_v2/UART'), ('UART:sci2_v2_1', 'usart_v2/UART'),
#('UART:sci2_v3_0', 'usart_v3/UART'), # ('UART:sci2_v3_0', 'usart_v3/UART'),
#('UART:sci2_v3_1', 'usart_v3/UART'), # ('UART:sci2_v3_1', 'usart_v3/UART'),
('.*:USART:sci2_v1_1', 'usart_v1/USART'), ('.*:USART:sci2_v1_1', 'usart_v1/USART'),
('.*:USART:sci2_v1_2_F1', 'usart_v1/USART'), ('.*:USART:sci2_v1_2_F1', 'usart_v1/USART'),
@ -222,9 +222,9 @@ perimap = [
('.*:USART:sci2_v2_2', 'usart_v2/USART'), ('.*:USART:sci2_v2_2', 'usart_v2/USART'),
('.*:USART:sci3_v1_0', 'usart_v2/USART'), ('.*:USART:sci3_v1_0', 'usart_v2/USART'),
('.*:USART:sci3_v1_1', 'usart_v2/USART'), ('.*:USART:sci3_v1_1', 'usart_v2/USART'),
#('.*:USART:sci3_v1_2', 'usart_v3/USART'), # ('.*:USART:sci3_v1_2', 'usart_v3/USART'),
#('.*:USART:sci3_v2_0', 'usart_v3/USART'), # ('.*:USART:sci3_v2_0', 'usart_v3/USART'),
#('.*:USART:sci3_v2_1', 'usart_v3/USART'), # ('.*:USART:sci3_v2_1', 'usart_v3/USART'),
('.*:RNG:rng1_v1_1', 'rng_v1/RNG'), ('.*:RNG:rng1_v1_1', 'rng_v1/RNG'),
('.*:RNG:rng1_v2_0', 'rng_v1/RNG'), ('.*:RNG:rng1_v2_0', 'rng_v1/RNG'),
('.*:RNG:rng1_v2_1', 'rng_v1/RNG'), ('.*:RNG:rng1_v2_1', 'rng_v1/RNG'),
@ -371,7 +371,7 @@ def parse_chips():
port = 'GPIO' + chr(ord('A')+p) port = 'GPIO' + chr(ord('A')+p)
if addr := h['defines'].get(port + '_BASE'): if addr := h['defines'].get(port + '_BASE'):
block = 'gpio_v2/GPIO' block = 'gpio_v2/GPIO'
if 'STM32F1' in chip_name: if chip['family'] == 'STM32F1':
block = 'gpio_v1/GPIO' block = 'gpio_v1/GPIO'
p = OrderedDict({ p = OrderedDict({
@ -379,6 +379,18 @@ def parse_chips():
'block': block, 'block': block,
}) })
peris[port] = p peris[port] = p
# Handle DMA specially.
for dma in ('DMA1', "DMA2"):
if addr := h['defines'].get(dma + '_BASE'):
block = 'dma_v1/DMA'
if chip['family'] in ('STM32F4', 'STM32F7', 'STM32H7'):
block = 'dma_v2/DMA'
p = OrderedDict({
'address': addr,
'block': block,
})
peris[dma] = p
# EXTI is not in the cubedb XMLs # EXTI is not in the cubedb XMLs
if addr := h['defines'].get('EXTI_BASE'): if addr := h['defines'].get('EXTI_BASE'):