From 0de8be5be4aa112c8de428d2bf8e44b69d821487 Mon Sep 17 00:00:00 2001 From: Bob McWhirter Date: Fri, 7 May 2021 11:27:36 -0400 Subject: [PATCH 1/2] SPI v2 first draft. --- data/registers/spi_v2.yaml | 329 +++++++++++++++++++++++++++++++++++++ 1 file changed, 329 insertions(+) create mode 100644 data/registers/spi_v2.yaml diff --git a/data/registers/spi_v2.yaml b/data/registers/spi_v2.yaml new file mode 100644 index 0000000..89b8fc2 --- /dev/null +++ b/data/registers/spi_v2.yaml @@ -0,0 +1,329 @@ +--- +block/SPI: + description: Serial peripheral interface/Inter-IC sound + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: SR + description: status register + byte_offset: 8 + fieldset: SR + - name: DR + description: data register + byte_offset: 12 + fieldset: DR + - name: CRCPR + description: CRC polynomial register + byte_offset: 16 + fieldset: CRCPR + - name: RXCRCR + description: RX CRC register + byte_offset: 20 + access: Read + fieldset: RXCRCR + - name: TXCRCR + description: TX CRC register + byte_offset: 24 + access: Read + fieldset: TXCRCR +fieldset/CR1: + description: control register 1 + fields: + - name: CPHA + description: Clock phase + bit_offset: 0 + bit_size: 1 + enum: CPHA + - name: CPOL + description: Clock polarity + bit_offset: 1 + bit_size: 1 + enum: CPOL + - name: MSTR + description: Master selection + bit_offset: 2 + bit_size: 1 + enum: MSTR + - name: BR + description: Baud rate control + bit_offset: 3 + bit_size: 3 + enum: BR + - name: SPE + description: SPI enable + bit_offset: 6 + bit_size: 1 + - name: LSBFIRST + description: Frame format + bit_offset: 7 + bit_size: 1 + enum: LSBFIRST + - name: SSI + description: Internal slave select + bit_offset: 8 + bit_size: 1 + - name: SSM + description: Software slave management + bit_offset: 9 + bit_size: 1 + - name: RXONLY + description: Receive only + bit_offset: 10 + bit_size: 1 + enum: RXONLY + - name: CRCL + description: CRC length + bit_offset: 11 + bit_size: 1 + - name: CRCNEXT + description: CRC transfer next + bit_offset: 12 + bit_size: 1 + enum: CRCNEXT + - name: CRCEN + description: Hardware CRC calculation enable + bit_offset: 13 + bit_size: 1 + - name: BIDIOE + description: Output enable in bidirectional mode + bit_offset: 14 + bit_size: 1 + enum: BIDIOE + - name: BIDIMODE + description: Bidirectional data mode enable + bit_offset: 15 + bit_size: 1 + enum: BIDIMODE +fieldset/CR2: + description: control register 2 + fields: + - name: RXDMAEN + description: Rx buffer DMA enable + bit_offset: 0 + bit_size: 1 + - name: TXDMAEN + description: Tx buffer DMA enable + bit_offset: 1 + bit_size: 1 + - name: SSOE + description: SS output enable + bit_offset: 2 + bit_size: 1 + - name: NSSP + description: NSS pulse management + bit_offset: 3 + bit_size: 1 + - name: FRF + description: Frame format + bit_offset: 4 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 5 + bit_size: 1 + - name: RXNEIE + description: RX buffer not empty interrupt enable + bit_offset: 6 + bit_size: 1 + - name: TXEIE + description: Tx buffer empty interrupt enable + bit_offset: 7 + bit_size: 1 + - name: DS + description: Data size + bit_offset: 8 + bit_size: 4 + - name: FRXTH + description: FIFO reception threshold + bit_offset: 12 + bit_size: 1 + - name: LDMA_RX + description: Last DMA transfer for reception + bit_offset: 13 + bit_size: 1 + - name: LDMA_TX + description: Last DMA transfer for transmission + bit_offset: 14 + bit_size: 1 +fieldset/CRCPR: + description: CRC polynomial register + fields: + - name: CRCPOLY + description: CRC polynomial register + bit_offset: 0 + bit_size: 16 +fieldset/DR: + description: data register + fields: + - name: DR + description: Data register + bit_offset: 0 + bit_size: 16 +fieldset/RXCRCR: + description: RX CRC register + fields: + - name: RxCRC + description: Rx CRC register + bit_offset: 0 + bit_size: 16 +fieldset/SR: + description: status register + fields: + - name: RXNE + description: Receive buffer not empty + bit_offset: 0 + bit_size: 1 + - name: TXE + description: Transmit buffer empty + bit_offset: 1 + bit_size: 1 + - name: CRCERR + description: CRC error flag + bit_offset: 4 + bit_size: 1 + - name: MODF + description: Mode fault + bit_offset: 5 + bit_size: 1 + - name: OVR + description: Overrun flag + bit_offset: 6 + bit_size: 1 + - name: BSY + description: Busy flag + bit_offset: 7 + bit_size: 1 + enum_read: BSYR + - name: FRE + description: Frame format error + bit_offset: 8 + bit_size: 1 + - name: FRLVL + description: FIFO reception level + bit_offset: 9 + bit_size: 2 + - name: FTLVL + description: FIFO transmission level + bit_offset: 11 + bit_size: 2 +fieldset/TXCRCR: + description: TX CRC register + fields: + - name: TxCRC + description: Tx CRC register + bit_offset: 0 + bit_size: 16 +enum/BIDIMODE: + bit_size: 1 + variants: + - name: Unidirectional + description: 2-line unidirectional data mode selected + value: 0 + - name: Bidirectional + description: 1-line bidirectional data mode selected + value: 1 +enum/BIDIOE: + bit_size: 1 + variants: + - name: OutputDisabled + description: Output disabled (receive-only mode) + value: 0 + - name: OutputEnabled + description: Output enabled (transmit-only mode) + value: 1 +enum/BR: + bit_size: 3 + variants: + - name: Div2 + description: f_PCLK / 2 + value: 0 + - name: Div4 + description: f_PCLK / 4 + value: 1 + - name: Div8 + description: f_PCLK / 8 + value: 2 + - name: Div16 + description: f_PCLK / 16 + value: 3 + - name: Div32 + description: f_PCLK / 32 + value: 4 + - name: Div64 + description: f_PCLK / 64 + value: 5 + - name: Div128 + description: f_PCLK / 128 + value: 6 + - name: Div256 + description: f_PCLK / 256 + value: 7 +enum/BSYR: + bit_size: 1 + variants: + - name: NotBusy + description: SPI not busy + value: 0 + - name: Busy + description: SPI busy + value: 1 +enum/CPHA: + bit_size: 1 + variants: + - name: FirstEdge + description: The first clock transition is the first data capture edge + value: 0 + - name: SecondEdge + description: The second clock transition is the first data capture edge + value: 1 +enum/CPOL: + bit_size: 1 + variants: + - name: IdleLow + description: CK to 0 when idle + value: 0 + - name: IdleHigh + description: CK to 1 when idle + value: 1 +enum/CRCNEXT: + bit_size: 1 + variants: + - name: TxBuffer + description: Next transmit value is from Tx buffer + value: 0 + - name: CRC + description: Next transmit value is from Tx CRC register + value: 1 +enum/LSBFIRST: + bit_size: 1 + variants: + - name: MSBFirst + description: Data is transmitted/received with the MSB first + value: 0 + - name: LSBFirst + description: Data is transmitted/received with the LSB first + value: 1 +enum/MSTR: + bit_size: 1 + variants: + - name: Slave + description: Slave configuration + value: 0 + - name: Master + description: Master configuration + value: 1 +enum/RXONLY: + bit_size: 1 + variants: + - name: FullDuplex + description: Full duplex (Transmit and receive) + value: 0 + - name: OutputDisabled + description: Output disabled (Receive-only mode) + value: 1 From 1a7fde6868adebe2d340473efcdd9625c71203bb Mon Sep 17 00:00:00 2001 From: Bob McWhirter Date: Fri, 7 May 2021 13:43:48 -0400 Subject: [PATCH 2/2] Better SPI v2. --- data/registers/spi_v2.yaml | 151 +++++++++++++++++++++++++++++++++---- 1 file changed, 138 insertions(+), 13 deletions(-) diff --git a/data/registers/spi_v2.yaml b/data/registers/spi_v2.yaml index 89b8fc2..f309658 100644 --- a/data/registers/spi_v2.yaml +++ b/data/registers/spi_v2.yaml @@ -1,6 +1,6 @@ --- -block/SPI: - description: Serial peripheral interface/Inter-IC sound +block/SPI1: + description: Serial peripheral interface items: - name: CR1 description: control register 1 @@ -81,6 +81,7 @@ fieldset/CR1: description: CRC length bit_offset: 11 bit_size: 1 + enum: CRCL - name: CRCNEXT description: CRC transfer next bit_offset: 12 @@ -123,6 +124,7 @@ fieldset/CR2: description: Frame format bit_offset: 4 bit_size: 1 + enum: FRF - name: ERRIE description: Error interrupt enable bit_offset: 5 @@ -139,18 +141,22 @@ fieldset/CR2: description: Data size bit_offset: 8 bit_size: 4 + enum: DS - name: FRXTH description: FIFO reception threshold bit_offset: 12 bit_size: 1 + enum: FRXTH - name: LDMA_RX description: Last DMA transfer for reception bit_offset: 13 bit_size: 1 + enum: LDMA_RX - name: LDMA_TX description: Last DMA transfer for transmission bit_offset: 14 bit_size: 1 + enum: LDMA_TX fieldset/CRCPR: description: CRC polynomial register fields: @@ -199,19 +205,21 @@ fieldset/SR: description: Busy flag bit_offset: 7 bit_size: 1 - enum_read: BSYR - name: FRE description: Frame format error bit_offset: 8 bit_size: 1 + enum_read: FRER - name: FRLVL description: FIFO reception level bit_offset: 9 bit_size: 2 + enum_read: FRLVLR - name: FTLVL - description: FIFO transmission level + description: FIFO Transmission Level bit_offset: 11 bit_size: 2 + enum_read: FTLVLR fieldset/TXCRCR: description: TX CRC register fields: @@ -264,15 +272,6 @@ enum/BR: - name: Div256 description: f_PCLK / 256 value: 7 -enum/BSYR: - bit_size: 1 - variants: - - name: NotBusy - description: SPI not busy - value: 0 - - name: Busy - description: SPI busy - value: 1 enum/CPHA: bit_size: 1 variants: @@ -291,6 +290,15 @@ enum/CPOL: - name: IdleHigh description: CK to 1 when idle value: 1 +enum/CRCL: + bit_size: 1 + variants: + - name: EightBit + description: 8-bit CRC length + value: 0 + - name: SixteenBit + description: 16-bit CRC length + value: 1 enum/CRCNEXT: bit_size: 1 variants: @@ -300,6 +308,123 @@ enum/CRCNEXT: - name: CRC description: Next transmit value is from Tx CRC register value: 1 +enum/DS: + bit_size: 4 + variants: + - name: FourBit + description: 4-bit + value: 3 + - name: FiveBit + description: 5-bit + value: 4 + - name: SixBit + description: 6-bit + value: 5 + - name: SevenBit + description: 7-bit + value: 6 + - name: EightBit + description: 8-bit + value: 7 + - name: NineBit + description: 9-bit + value: 8 + - name: TenBit + description: 10-bit + value: 9 + - name: ElevenBit + description: 11-bit + value: 10 + - name: TwelveBit + description: 12-bit + value: 11 + - name: ThirteenBit + description: 13-bit + value: 12 + - name: FourteenBit + description: 14-bit + value: 13 + - name: FifteenBit + description: 15-bit + value: 14 + - name: SixteenBit + description: 16-bit + value: 15 +enum/FRER: + bit_size: 1 + variants: + - name: NoError + description: No frame format error + value: 0 + - name: Error + description: A frame format error occurred + value: 1 +enum/FRF: + bit_size: 1 + variants: + - name: Motorola + description: SPI Motorola mode + value: 0 + - name: TI + description: SPI TI mode + value: 1 +enum/FRLVLR: + bit_size: 2 + variants: + - name: Empty + description: Rx FIFO Empty + value: 0 + - name: Quarter + description: Rx 1/4 FIFO + value: 1 + - name: Half + description: Rx 1/2 FIFO + value: 2 + - name: Full + description: Rx FIFO full + value: 3 +enum/FRXTH: + bit_size: 1 + variants: + - name: Half + description: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) + value: 0 + - name: Quarter + description: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + value: 1 +enum/FTLVLR: + bit_size: 2 + variants: + - name: Empty + description: Tx FIFO Empty + value: 0 + - name: Quarter + description: Tx 1/4 FIFO + value: 1 + - name: Half + description: Tx 1/2 FIFO + value: 2 + - name: Full + description: Tx FIFO full + value: 3 +enum/LDMA_RX: + bit_size: 1 + variants: + - name: Even + description: Number of data to transfer for receive is even + value: 0 + - name: Odd + description: Number of data to transfer for receive is odd + value: 1 +enum/LDMA_TX: + bit_size: 1 + variants: + - name: Even + description: Number of data to transfer for transmit is even + value: 0 + - name: Odd + description: Number of data to transfer for transmit is odd + value: 1 enum/LSBFIRST: bit_size: 1 variants: