diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index 91a0d03..e66ac16 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -1,4498 +1,2179 @@ - block/RCC: description: Reset and clock control items: - - name: CR - description: clock control register - byte_offset: 0 - fieldset: CR - - name: HSICFGR - description: RCC HSI configuration register - byte_offset: 4 - fieldset: HSICFGR - - name: ICSCR - description: RCC Internal Clock Source Calibration Register - byte_offset: 4 - fieldset: ICSCR - - name: CRRCR - description: RCC Clock Recovery RC Register - byte_offset: 8 - access: Read - fieldset: CRRCR - - name: CSICFGR - description: RCC CSI configuration register - byte_offset: 12 - fieldset: CSICFGR - - name: CFGR - description: RCC Clock Configuration Register - byte_offset: 16 - fieldset: CFGR - - name: D1CFGR - description: RCC Domain 1 Clock Configuration Register - byte_offset: 24 - fieldset: D1CFGR - - name: D2CFGR - description: RCC Domain 2 Clock Configuration Register - byte_offset: 28 - fieldset: D2CFGR - - name: D3CFGR - description: RCC Domain 3 Clock Configuration Register - byte_offset: 32 - fieldset: D3CFGR - - name: PLLCKSELR - description: RCC PLLs Clock Source Selection Register - byte_offset: 40 - fieldset: PLLCKSELR - - name: PLLCFGR - description: RCC PLLs Configuration Register - byte_offset: 44 - fieldset: PLLCFGR - - name: PLLDIVR - description: RCC PLL1 Dividers Configuration Register - array: - len: 3 - stride: 8 - byte_offset: 48 - fieldset: PLL1DIVR - - name: PLLFRACR - description: RCC PLL1 Fractional Divider Register - array: - len: 3 - stride: 8 - byte_offset: 52 - fieldset: PLL1FRACR - - name: D1CCIPR - description: RCC Domain 1 Kernel Clock Configuration Register - byte_offset: 76 - fieldset: D1CCIPR - - name: D2CCIP1R - description: RCC Domain 2 Kernel Clock Configuration Register - byte_offset: 80 - fieldset: D2CCIP1R - - name: D2CCIP2R - description: RCC Domain 2 Kernel Clock Configuration Register - byte_offset: 84 - fieldset: D2CCIP2R - - name: D3CCIPR - description: RCC Domain 3 Kernel Clock Configuration Register - byte_offset: 88 - fieldset: D3CCIPR - - name: CIER - description: RCC Clock Source Interrupt Enable Register - byte_offset: 96 - fieldset: CIER - - name: CIFR - description: RCC Clock Source Interrupt Flag Register - byte_offset: 100 - access: Read - fieldset: CIFR - - name: CICR - description: RCC Clock Source Interrupt Clear Register - byte_offset: 104 - fieldset: CICR - - name: BDCR - description: RCC Backup Domain Control Register - byte_offset: 112 - fieldset: BDCR - - name: CSR - description: RCC Clock Control and Status Register - byte_offset: 116 - fieldset: CSR - - name: AHB3RSTR - description: RCC AHB3 Reset Register - byte_offset: 124 - fieldset: AHB3RSTR - - name: AHB1RSTR - description: RCC AHB1 Peripheral Reset Register - byte_offset: 128 - fieldset: AHB1RSTR - - name: AHB2RSTR - description: RCC AHB2 Peripheral Reset Register - byte_offset: 132 - fieldset: AHB2RSTR - - name: AHB4RSTR - description: RCC AHB4 Peripheral Reset Register - byte_offset: 136 - fieldset: AHB4RSTR - - name: APB3RSTR - description: RCC APB3 Peripheral Reset Register - byte_offset: 140 - fieldset: APB3RSTR - - name: APB1LRSTR - description: RCC APB1 Peripheral Reset Register - byte_offset: 144 - fieldset: APB1LRSTR - - name: APB1HRSTR - description: RCC APB1 Peripheral Reset Register - byte_offset: 148 - fieldset: APB1HRSTR - - name: APB2RSTR - description: RCC APB2 Peripheral Reset Register - byte_offset: 152 - fieldset: APB2RSTR - - name: APB4RSTR - description: RCC APB4 Peripheral Reset Register - byte_offset: 156 - fieldset: APB4RSTR - - name: GCR - description: RCC Global Control Register - byte_offset: 160 - fieldset: GCR - - name: D3AMR - description: RCC D3 Autonomous mode Register - byte_offset: 168 - fieldset: D3AMR - - name: RSR - description: RCC Reset Status Register - byte_offset: 208 - fieldset: RSR - - name: AHB3ENR - description: RCC AHB3 Clock Register - byte_offset: 212 - fieldset: AHB3ENR - - name: AHB1ENR - description: RCC AHB1 Clock Register - byte_offset: 216 - fieldset: AHB1ENR - - name: AHB2ENR - description: RCC AHB2 Clock Register - byte_offset: 220 - fieldset: AHB2ENR - - name: AHB4ENR - description: RCC AHB4 Clock Register - byte_offset: 224 - fieldset: AHB4ENR - - name: APB3ENR - description: RCC APB3 Clock Register - byte_offset: 228 - fieldset: APB3ENR - - name: APB1LENR - description: RCC APB1 Clock Register - byte_offset: 232 - fieldset: APB1LENR - - name: APB1HENR - description: RCC APB1 Clock Register - byte_offset: 236 - fieldset: APB1HENR - - name: APB2ENR - description: RCC APB2 Clock Register - byte_offset: 240 - fieldset: APB2ENR - - name: APB4ENR - description: RCC APB4 Clock Register - byte_offset: 244 - fieldset: APB4ENR - - name: AHB3LPENR - description: RCC AHB3 Sleep Clock Register - byte_offset: 252 - fieldset: AHB3LPENR - - name: AHB1LPENR - description: RCC AHB1 Sleep Clock Register - byte_offset: 256 - fieldset: AHB1LPENR - - name: AHB2LPENR - description: RCC AHB2 Sleep Clock Register - byte_offset: 260 - fieldset: AHB2LPENR - - name: AHB4LPENR - description: RCC AHB4 Sleep Clock Register - byte_offset: 264 - fieldset: AHB4LPENR - - name: APB3LPENR - description: RCC APB3 Sleep Clock Register - byte_offset: 268 - fieldset: APB3LPENR - - name: APB1LLPENR - description: RCC APB1 Low Sleep Clock Register - byte_offset: 272 - fieldset: APB1LLPENR - - name: APB1HLPENR - description: RCC APB1 High Sleep Clock Register - byte_offset: 276 - fieldset: APB1HLPENR - - name: APB2LPENR - description: RCC APB2 Sleep Clock Register - byte_offset: 280 - fieldset: APB2LPENR - - name: APB4LPENR - description: RCC APB4 Sleep Clock Register - byte_offset: 284 - fieldset: APB4LPENR - - name: C1_RSR - description: RCC Reset Status Register - byte_offset: 304 - fieldset: C1_RSR - - name: C1_AHB3ENR - description: RCC AHB3 Clock Register - byte_offset: 308 - fieldset: C1_AHB3ENR - - name: C1_AHB1ENR - description: RCC AHB1 Clock Register - byte_offset: 312 - fieldset: C1_AHB1ENR - - name: C1_AHB2ENR - description: RCC AHB2 Clock Register - byte_offset: 316 - fieldset: C1_AHB2ENR - - name: C1_AHB4ENR - description: RCC AHB4 Clock Register - byte_offset: 320 - fieldset: C1_AHB4ENR - - name: C1_APB3ENR - description: RCC APB3 Clock Register - byte_offset: 324 - fieldset: C1_APB3ENR - - name: C1_APB1LENR - description: RCC APB1 Clock Register - byte_offset: 328 - fieldset: C1_APB1LENR - - name: C1_APB1HENR - description: RCC APB1 Clock Register - byte_offset: 332 - fieldset: C1_APB1HENR - - name: C1_APB2ENR - description: RCC APB2 Clock Register - byte_offset: 336 - fieldset: C1_APB2ENR - - name: C1_APB4ENR - description: RCC APB4 Clock Register - byte_offset: 340 - fieldset: C1_APB4ENR - - name: C1_AHB3LPENR - description: RCC AHB3 Sleep Clock Register - byte_offset: 348 - fieldset: C1_AHB3LPENR - - name: C1_AHB1LPENR - description: RCC AHB1 Sleep Clock Register - byte_offset: 352 - fieldset: C1_AHB1LPENR - - name: C1_AHB2LPENR - description: RCC AHB2 Sleep Clock Register - byte_offset: 356 - fieldset: C1_AHB2LPENR - - name: C1_AHB4LPENR - description: RCC AHB4 Sleep Clock Register - byte_offset: 360 - fieldset: C1_AHB4LPENR - - name: C1_APB3LPENR - description: RCC APB3 Sleep Clock Register - byte_offset: 364 - fieldset: C1_APB3LPENR - - name: C1_APB1LLPENR - description: RCC APB1 Low Sleep Clock Register - byte_offset: 368 - fieldset: C1_APB1LLPENR - - name: C1_APB1HLPENR - description: RCC APB1 High Sleep Clock Register - byte_offset: 372 - fieldset: C1_APB1HLPENR - - name: C1_APB2LPENR - description: RCC APB2 Sleep Clock Register - byte_offset: 376 - fieldset: C1_APB2LPENR - - name: C1_APB4LPENR - description: RCC APB4 Sleep Clock Register - byte_offset: 380 - fieldset: C1_APB4LPENR + - byte_offset: 0 + description: clock control register + fieldset: CR + name: CR + - access: Read + byte_offset: 8 + description: RCC Clock Recovery RC Register + fieldset: CRRCR + name: CRRCR + - byte_offset: 16 + description: RCC Clock Configuration Register + fieldset: CFGR + name: CFGR + - byte_offset: 24 + description: RCC Domain 1 Clock Configuration Register + fieldset: D1CFGR + name: D1CFGR + - byte_offset: 28 + description: RCC Domain 2 Clock Configuration Register + fieldset: D2CFGR + name: D2CFGR + - byte_offset: 32 + description: RCC Domain 3 Clock Configuration Register + fieldset: D3CFGR + name: D3CFGR + - byte_offset: 40 + description: RCC PLLs Clock Source Selection Register + fieldset: PLLCKSELR + name: PLLCKSELR + - byte_offset: 44 + description: RCC PLLs Configuration Register + fieldset: PLLCFGR + name: PLLCFGR + - byte_offset: 48 + description: RCC PLL1 Dividers Configuration Register + fieldset: PLL1DIVR + name: PLL1DIVR + - byte_offset: 52 + description: RCC PLL1 Fractional Divider Register + fieldset: PLL1FRACR + name: PLL1FRACR + - byte_offset: 56 + description: RCC PLL2 Dividers Configuration Register + fieldset: PLL2DIVR + name: PLL2DIVR + - byte_offset: 60 + description: RCC PLL2 Fractional Divider Register + fieldset: PLL2FRACR + name: PLL2FRACR + - byte_offset: 64 + description: RCC PLL3 Dividers Configuration Register + fieldset: PLL3DIVR + name: PLL3DIVR + - byte_offset: 68 + description: RCC PLL3 Fractional Divider Register + fieldset: PLL3FRACR + name: PLL3FRACR + - byte_offset: 96 + description: RCC Clock Source Interrupt Enable Register + fieldset: CIER + name: CIER + - access: Read + byte_offset: 100 + description: RCC Clock Source Interrupt Flag Register + fieldset: CIFR + name: CIFR + - byte_offset: 104 + description: RCC Clock Source Interrupt Clear Register + fieldset: CICR + name: CICR + - byte_offset: 112 + description: RCC Backup Domain Control Register + fieldset: BDCR + name: BDCR + - byte_offset: 116 + description: RCC Clock Control and Status Register + fieldset: CSR + name: CSR + - byte_offset: 124 + description: RCC AHB3 Reset Register + fieldset: AHB3RSTR + name: AHB3RSTR + - byte_offset: 128 + description: RCC AHB1 Peripheral Reset Register + fieldset: AHB1RSTR + name: AHB1RSTR + - byte_offset: 132 + description: RCC AHB2 Peripheral Reset Register + fieldset: AHB2RSTR + name: AHB2RSTR + - byte_offset: 136 + description: RCC AHB4 Peripheral Reset Register + fieldset: AHB4RSTR + name: AHB4RSTR + - byte_offset: 140 + description: RCC APB3 Peripheral Reset Register + fieldset: APB3RSTR + name: APB3RSTR + - byte_offset: 144 + description: RCC APB1 Peripheral Reset Register + fieldset: APB1LRSTR + name: APB1LRSTR + - byte_offset: 148 + description: RCC APB1 Peripheral Reset Register + fieldset: APB1HRSTR + name: APB1HRSTR + - byte_offset: 152 + description: RCC APB2 Peripheral Reset Register + fieldset: APB2RSTR + name: APB2RSTR + - byte_offset: 156 + description: RCC APB4 Peripheral Reset Register + fieldset: APB4RSTR + name: APB4RSTR + - byte_offset: 160 + description: Global Control Register + fieldset: GCR + name: GCR + - byte_offset: 168 + description: RCC D3 Autonomous mode Register + fieldset: D3AMR + name: D3AMR + - byte_offset: 304 + description: RCC Reset Status Register + fieldset: C1_RSR + name: C1_RSR +enum/ADCSEL: + bit_size: 2 +enum/CECSEL: + bit_size: 2 +enum/CKPERSEL: + bit_size: 2 +enum/DFSDMSEL: + bit_size: 1 +enum/DIVP: + bit_size: 7 +enum/DPPRE: + bit_size: 3 +enum/FDCANSEL: + bit_size: 2 +enum/FMCSEL: + bit_size: 2 +enum/HPRE: + bit_size: 4 +enum/HRTIMSEL: + bit_size: 1 +enum/HSEBYP: + bit_size: 1 +enum/HSIDIV: + bit_size: 2 +enum/HSIDIVFR: + bit_size: 1 +enum/HSION: + bit_size: 1 +enum/HSIRDYR: + bit_size: 1 +enum/I2C123SEL: + bit_size: 2 +enum/I2C4SEL: + bit_size: 2 +enum/LPTIM1SEL: + bit_size: 3 +enum/LPTIM2SEL: + bit_size: 3 +enum/LPUARTSEL: + bit_size: 3 +enum/LSEBYP: + bit_size: 1 +enum/LSECSSDR: + bit_size: 1 +enum/LSECSSON: + bit_size: 1 +enum/LSEDRV: + bit_size: 2 +enum/LSEON: + bit_size: 1 +enum/LSERDYR: + bit_size: 1 +enum/LSION: + bit_size: 1 +enum/LSIRDYC: + bit_size: 1 +enum/LSIRDYIE: + bit_size: 1 +enum/LSIRDYR: + bit_size: 1 +enum/MCO1: + bit_size: 3 +enum/MCO2: + bit_size: 3 +enum/PLLRGE: + bit_size: 2 +enum/PLLSRC: + bit_size: 2 +enum/PLLVCOSEL: + bit_size: 1 +enum/RNGSEL: + bit_size: 2 +enum/RTCSEL: + bit_size: 2 +enum/SAIASEL: + bit_size: 3 +enum/SAISEL: + bit_size: 3 +enum/SDMMCSEL: + bit_size: 1 +enum/SPI45SEL: + bit_size: 3 +enum/SPI6SEL: + bit_size: 3 +enum/STOPWUCK: + bit_size: 1 +enum/SW: + bit_size: 3 +enum/SWPSEL: + bit_size: 1 +enum/SWSR: + bit_size: 3 +enum/TIMPRE: + bit_size: 1 +enum/USART234578SEL: + bit_size: 3 +enum/USBSEL: + bit_size: 2 +enum/WWRSC: + bit_size: 1 fieldset/AHB1ENR: description: RCC AHB1 Clock Register fields: - - name: DMA1EN - description: DMA1 Clock Enable - bit_offset: 0 - bit_size: 1 - - name: DMA2EN - description: DMA2 Clock Enable - bit_offset: 1 - bit_size: 1 - - name: ADC12EN - description: ADC1/2 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - - name: ETH1MACEN - description: Ethernet MAC bus interface Clock Enable - bit_offset: 15 - bit_size: 1 - - name: ETH1TXEN - description: Ethernet Transmission Clock Enable - bit_offset: 16 - bit_size: 1 - - name: ETH1RXEN - description: Ethernet Reception Clock Enable - bit_offset: 17 - bit_size: 1 - - name: USB2OTGHSULPIEN - description: " Enable USB_PHY2 clocks " - bit_offset: 18 - bit_size: 1 - - name: USB1OTGEN - description: USB1OTG Peripheral Clocks Enable - bit_offset: 25 - bit_size: 1 - - name: USB1ULPIEN - description: USB_PHY1 Clocks Enable - bit_offset: 26 - bit_size: 1 - - name: USB2OTGEN - description: USB2OTG Peripheral Clocks Enable - bit_offset: 27 - bit_size: 1 - - name: USB2ULPIEN - description: USB_PHY2 Clocks Enable - bit_offset: 28 - bit_size: 1 + - bit_offset: 0 + bit_size: 1 + description: DMA1 Clock Enable + name: DMA1EN + - bit_offset: 1 + bit_size: 1 + description: DMA2 Clock Enable + name: DMA2EN + - bit_offset: 5 + bit_size: 1 + description: ADC1/2 Peripheral Clocks Enable + name: ADC12EN + - bit_offset: 15 + bit_size: 1 + description: Ethernet MAC bus interface Clock Enable + name: ETH1MACEN + - bit_offset: 16 + bit_size: 1 + description: Ethernet Transmission Clock Enable + name: ETH1TXEN + - bit_offset: 17 + bit_size: 1 + description: Ethernet Reception Clock Enable + name: ETH1RXEN + - bit_offset: 25 + bit_size: 1 + description: USB1OTG Peripheral Clocks Enable + name: USB1OTGEN + - bit_offset: 26 + bit_size: 1 + description: USB_PHY1 Clocks Enable + name: USB1ULPIEN fieldset/AHB1LPENR: description: RCC AHB1 Sleep Clock Register fields: - - name: DMA1LPEN - description: DMA1 Clock Enable During CSleep Mode - bit_offset: 0 - bit_size: 1 - - name: DMA2LPEN - description: DMA2 Clock Enable During CSleep Mode - bit_offset: 1 - bit_size: 1 - - name: ADC12LPEN - description: ADC1/2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - name: ETH1MACLPEN - description: Ethernet MAC bus interface Clock Enable During CSleep Mode - bit_offset: 15 - bit_size: 1 - - name: ETH1TXLPEN - description: Ethernet Transmission Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: ETH1RXLPEN - description: Ethernet Reception Clock Enable During CSleep Mode - bit_offset: 17 - bit_size: 1 - - name: USB1OTGLPEN - description: USB1OTG peripheral clock enable during CSleep mode - bit_offset: 25 - bit_size: 1 - - name: USB1OTGHSULPILPEN - description: USB_PHY1 clock enable during CSleep mode - bit_offset: 26 - bit_size: 1 - - name: USB2OTGLPEN - description: USB2OTG peripheral clock enable during CSleep mode - bit_offset: 27 - bit_size: 1 - - name: USB2OTGHSULPILPEN - description: USB_PHY2 clocks enable during CSleep mode - bit_offset: 28 - bit_size: 1 + - bit_offset: 0 + bit_size: 1 + description: DMA1 Clock Enable During CSleep Mode + name: DMA1LPEN + - bit_offset: 1 + bit_size: 1 + description: DMA2 Clock Enable During CSleep Mode + name: DMA2LPEN + - bit_offset: 5 + bit_size: 1 + description: ADC1/2 Peripheral Clocks Enable During CSleep Mode + name: ADC12LPEN + - bit_offset: 15 + bit_size: 1 + description: Ethernet MAC bus interface Clock Enable During CSleep Mode + name: ETH1MACLPEN + - bit_offset: 16 + bit_size: 1 + description: Ethernet Transmission Clock Enable During CSleep Mode + name: ETH1TXLPEN + - bit_offset: 17 + bit_size: 1 + description: Ethernet Reception Clock Enable During CSleep Mode + name: ETH1RXLPEN + - bit_offset: 25 + bit_size: 1 + description: USB1OTG peripheral clock enable during CSleep mode + name: USB1OTGLPEN fieldset/AHB1RSTR: description: RCC AHB1 Peripheral Reset Register fields: - - name: DMA1RST - description: DMA1 block reset - bit_offset: 0 - bit_size: 1 - - name: DMA2RST - description: DMA2 block reset - bit_offset: 1 - bit_size: 1 - - name: ADC12RST - description: ADC1&2 block reset - bit_offset: 5 - bit_size: 1 - - name: ETH1MACRST - description: ETH1MAC block reset - bit_offset: 15 - bit_size: 1 - - name: USB1OTGRST - description: USB1OTG block reset - bit_offset: 25 - bit_size: 1 - - name: USB2OTGRST - description: USB2OTG block reset - bit_offset: 27 - bit_size: 1 + - bit_offset: 0 + bit_size: 1 + description: DMA1 block reset + name: DMA1RST + - bit_offset: 1 + bit_size: 1 + description: DMA2 block reset + name: DMA2RST + - bit_offset: 5 + bit_size: 1 + description: ADC1&2 block reset + name: ADC12RST + - bit_offset: 15 + bit_size: 1 + description: ETH1MAC block reset + name: ETH1MACRST + - bit_offset: 25 + bit_size: 1 + description: USB1OTG block reset + name: USB1OTGRST + - bit_offset: 27 + bit_size: 1 + description: USB2OTG block reset + name: USB2OTGRST fieldset/AHB2ENR: description: RCC AHB2 Clock Register fields: - - name: DCMIEN - description: DCMI peripheral clock - bit_offset: 0 - bit_size: 1 - - name: CRYPTEN - description: CRYPT peripheral clock enable - bit_offset: 4 - bit_size: 1 - - name: HASHEN - description: HASH peripheral clock enable - bit_offset: 5 - bit_size: 1 - - name: RNGEN - description: RNG peripheral clocks enable - bit_offset: 6 - bit_size: 1 - - name: SDMMC2EN - description: SDMMC2 and SDMMC2 delay clock enable - bit_offset: 9 - bit_size: 1 - - name: SRAM1EN - description: SRAM1 block enable - bit_offset: 29 - bit_size: 1 - - name: SRAM2EN - description: SRAM2 block enable - bit_offset: 30 - bit_size: 1 - - name: SRAM3EN - description: SRAM3 block enable - bit_offset: 31 - bit_size: 1 + - bit_offset: 0 + bit_size: 1 + description: DCMI peripheral clock + name: DCMIEN + - bit_offset: 4 + bit_size: 1 + description: CRYPT peripheral clock enable + name: CRYPTEN + - bit_offset: 5 + bit_size: 1 + description: HASH peripheral clock enable + name: HASHEN + - bit_offset: 6 + bit_size: 1 + description: RNG peripheral clocks enable + name: RNGEN + - bit_offset: 9 + bit_size: 1 + description: SDMMC2 and SDMMC2 delay clock enable + name: SDMMC2EN + - bit_offset: 29 + bit_size: 1 + description: SRAM1 block enable + name: SRAM1EN + - bit_offset: 30 + bit_size: 1 + description: SRAM2 block enable + name: SRAM2EN + - bit_offset: 31 + bit_size: 1 + description: SRAM3 block enable + name: SRAM3EN fieldset/AHB2LPENR: description: RCC AHB2 Sleep Clock Register fields: - - name: DCMILPEN - description: DCMI peripheral clock enable during csleep mode - bit_offset: 0 - bit_size: 1 - - name: CRYPTLPEN - description: CRYPT peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - name: HASHLPEN - description: HASH peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - name: RNGLPEN - description: RNG peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - - name: SDMMC2LPEN - description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - - name: SRAM1LPEN - description: SRAM1 Clock Enable During CSleep Mode - bit_offset: 29 - bit_size: 1 - - name: SRAM2LPEN - description: SRAM2 Clock Enable During CSleep Mode - bit_offset: 30 - bit_size: 1 - - name: SRAM3LPEN - description: SRAM3 Clock Enable During CSleep Mode - bit_offset: 31 - bit_size: 1 + - bit_offset: 0 + bit_size: 1 + description: DCMI peripheral clock enable during csleep mode + name: DCMILPEN + - bit_offset: 4 + bit_size: 1 + description: CRYPT peripheral clock enable during CSleep mode + name: CRYPTLPEN + - bit_offset: 5 + bit_size: 1 + description: HASH peripheral clock enable during CSleep mode + name: HASHLPEN + - bit_offset: 6 + bit_size: 1 + description: RNG peripheral clock enable during CSleep mode + name: RNGLPEN + - bit_offset: 9 + bit_size: 1 + description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode + name: SDMMC2LPEN + - bit_offset: 29 + bit_size: 1 + description: SRAM1 Clock Enable During CSleep Mode + name: SRAM1LPEN + - bit_offset: 30 + bit_size: 1 + description: SRAM2 Clock Enable During CSleep Mode + name: SRAM2LPEN + - bit_offset: 31 + bit_size: 1 + description: SRAM3 Clock Enable During CSleep Mode + name: SRAM3LPEN fieldset/AHB2RSTR: description: RCC AHB2 Peripheral Reset Register fields: - - name: CAMITFRST - description: CAMITF block reset - bit_offset: 0 - bit_size: 1 - - name: CRYPTRST - description: Cryptography block reset - bit_offset: 4 - bit_size: 1 - - name: HASHRST - description: Hash block reset - bit_offset: 5 - bit_size: 1 - - name: RNGRST - description: Random Number Generator block reset - bit_offset: 6 - bit_size: 1 - - name: SDMMC2RST - description: SDMMC2 and SDMMC2 Delay block reset - bit_offset: 9 - bit_size: 1 + - bit_offset: 0 + bit_size: 1 + description: CAMITF block reset + name: CAMITFRST + - bit_offset: 4 + bit_size: 1 + description: Cryptography block reset + name: CRYPTRST + - bit_offset: 5 + bit_size: 1 + description: Hash block reset + name: HASHRST + - bit_offset: 6 + bit_size: 1 + description: Random Number Generator block reset + name: RNGRST + - bit_offset: 9 + bit_size: 1 + description: SDMMC2 and SDMMC2 Delay block reset + name: SDMMC2RST fieldset/AHB3ENR: description: RCC AHB3 Clock Register fields: - - name: MDMAEN - description: MDMA Peripheral Clock Enable - bit_offset: 0 - bit_size: 1 - - name: DMA2DEN - description: DMA2D Peripheral Clock Enable - bit_offset: 4 - bit_size: 1 - - name: JPGDECEN - description: JPGDEC Peripheral Clock Enable - bit_offset: 5 - bit_size: 1 - - name: FMCEN - description: FMC Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - - name: QSPIEN - description: QUADSPI and QUADSPI Delay Clock Enable - bit_offset: 14 - bit_size: 1 - - name: SDMMC1EN - description: SDMMC1 and SDMMC1 Delay Clock Enable - bit_offset: 16 - bit_size: 1 + - bit_offset: 0 + bit_size: 1 + description: MDMA Peripheral Clock Enable + name: MDMAEN + - bit_offset: 4 + bit_size: 1 + description: DMA2D Peripheral Clock Enable + name: DMA2DEN + - bit_offset: 5 + bit_size: 1 + description: JPGDEC Peripheral Clock Enable + name: JPGDECEN + - bit_offset: 12 + bit_size: 1 + description: FMC Peripheral Clocks Enable + name: FMCEN + - bit_offset: 14 + bit_size: 1 + description: QUADSPI and QUADSPI Delay Clock Enable + name: QSPIEN + - bit_offset: 16 + bit_size: 1 + description: SDMMC1 and SDMMC1 Delay Clock Enable + name: SDMMC1EN fieldset/AHB3LPENR: description: RCC AHB3 Sleep Clock Register fields: - - name: MDMALPEN - description: MDMA Clock Enable During CSleep Mode - bit_offset: 0 - bit_size: 1 - - name: DMA2DLPEN - description: DMA2D Clock Enable During CSleep Mode - bit_offset: 4 - bit_size: 1 - - name: JPGDECLPEN - description: JPGDEC Clock Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - name: FLASHLPEN - description: FLITF Clock Enable During CSleep Mode - bit_offset: 8 - bit_size: 1 - - name: FMCLPEN - description: FMC Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - - name: QSPILPEN - description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode - bit_offset: 14 - bit_size: 1 - - name: SDMMC1LPEN - description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: D1DTCM1LPEN - description: D1DTCM1 Block Clock Enable During CSleep mode - bit_offset: 28 - bit_size: 1 - - name: DTCM2LPEN - description: D1 DTCM2 Block Clock Enable During CSleep mode - bit_offset: 29 - bit_size: 1 - - name: ITCMLPEN - description: D1ITCM Block Clock Enable During CSleep mode - bit_offset: 30 - bit_size: 1 - - name: AXISRAMLPEN - description: AXISRAM Block Clock Enable During CSleep mode - bit_offset: 31 - bit_size: 1 + - bit_offset: 0 + bit_size: 1 + description: MDMA Clock Enable During CSleep Mode + name: MDMALPEN + - bit_offset: 4 + bit_size: 1 + description: DMA2D Clock Enable During CSleep Mode + name: DMA2DLPEN + - bit_offset: 5 + bit_size: 1 + description: JPGDEC Clock Enable During CSleep Mode + name: JPGDECLPEN + - bit_offset: 12 + bit_size: 1 + description: FMC Peripheral Clocks Enable During CSleep Mode + name: FMCLPEN + - bit_offset: 14 + bit_size: 1 + description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode + name: QSPILPEN + - bit_offset: 16 + bit_size: 1 + description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode + name: SDMMC1LPEN + - bit_offset: 28 + bit_size: 1 + description: D1DTCM1 Block Clock Enable During CSleep mode + name: D1DTCM1LPEN + - bit_offset: 29 + bit_size: 1 + description: D1 DTCM2 Block Clock Enable During CSleep mode + name: DTCM2LPEN + - bit_offset: 30 + bit_size: 1 + description: D1ITCM Block Clock Enable During CSleep mode + name: ITCMLPEN + - bit_offset: 31 + bit_size: 1 + description: AXISRAM Block Clock Enable During CSleep mode + name: AXISRAMLPEN fieldset/AHB3RSTR: description: RCC AHB3 Reset Register fields: - - name: MDMARST - description: MDMA block reset - bit_offset: 0 - bit_size: 1 - - name: DMA2DRST - description: DMA2D block reset - bit_offset: 4 - bit_size: 1 - - name: JPGDECRST - description: JPGDEC block reset - bit_offset: 5 - bit_size: 1 - - name: FMCRST - description: FMC block reset - bit_offset: 12 - bit_size: 1 - - name: QSPIRST - description: QUADSPI and QUADSPI delay block reset - bit_offset: 14 - bit_size: 1 - - name: SDMMC1RST - description: SDMMC1 and SDMMC1 delay block reset - bit_offset: 16 - bit_size: 1 - - name: CPURST - description: CPU reset - bit_offset: 31 - bit_size: 1 + - bit_offset: 0 + bit_size: 1 + description: MDMA block reset + name: MDMARST + - bit_offset: 4 + bit_size: 1 + description: DMA2D block reset + name: DMA2DRST + - bit_offset: 5 + bit_size: 1 + description: JPGDEC block reset + name: JPGDECRST + - bit_offset: 12 + bit_size: 1 + description: FMC block reset + name: FMCRST + - bit_offset: 14 + bit_size: 1 + description: QUADSPI and QUADSPI delay block reset + name: QSPIRST + - bit_offset: 16 + bit_size: 1 + description: SDMMC1 and SDMMC1 delay block reset + name: SDMMC1RST + - bit_offset: 31 + bit_size: 1 + description: CPU reset + name: CPURST fieldset/AHB4ENR: description: RCC AHB4 Clock Register fields: - - name: GPIOAEN - description: 0GPIO peripheral clock enable - bit_offset: 0 - bit_size: 1 - - name: GPIOBEN - description: 0GPIO peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: GPIOCEN - description: 0GPIO peripheral clock enable - bit_offset: 2 - bit_size: 1 - - name: GPIODEN - description: 0GPIO peripheral clock enable - bit_offset: 3 - bit_size: 1 - - name: GPIOEEN - description: 0GPIO peripheral clock enable - bit_offset: 4 - bit_size: 1 - - name: GPIOFEN - description: 0GPIO peripheral clock enable - bit_offset: 5 - bit_size: 1 - - name: GPIOGEN - description: 0GPIO peripheral clock enable - bit_offset: 6 - bit_size: 1 - - name: GPIOHEN - description: 0GPIO peripheral clock enable - bit_offset: 7 - bit_size: 1 - - name: GPIOIEN - description: 0GPIO peripheral clock enable - bit_offset: 8 - bit_size: 1 - - name: GPIOJEN - description: 0GPIO peripheral clock enable - bit_offset: 9 - bit_size: 1 - - name: GPIOKEN - description: 0GPIO peripheral clock enable - bit_offset: 10 - bit_size: 1 - - name: CRCEN - description: CRC peripheral clock enable - bit_offset: 19 - bit_size: 1 - - name: BDMAEN - description: BDMA and DMAMUX2 Clock Enable - bit_offset: 21 - bit_size: 1 - - name: ADC3EN - description: ADC3 Peripheral Clocks Enable - bit_offset: 24 - bit_size: 1 - - name: HSEMEN - description: HSEM peripheral clock enable - bit_offset: 25 - bit_size: 1 - - name: BKPRAMEN - description: Backup RAM Clock Enable - bit_offset: 28 - bit_size: 1 + - bit_offset: 0 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOAEN + - bit_offset: 1 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOBEN + - bit_offset: 2 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOCEN + - bit_offset: 3 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIODEN + - bit_offset: 4 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOEEN + - bit_offset: 5 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOFEN + - bit_offset: 6 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOGEN + - bit_offset: 7 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOHEN + - bit_offset: 8 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOIEN + - bit_offset: 9 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOJEN + - bit_offset: 10 + bit_size: 1 + description: 0GPIO peripheral clock enable + name: GPIOKEN + - bit_offset: 19 + bit_size: 1 + description: CRC peripheral clock enable + name: CRCEN + - bit_offset: 21 + bit_size: 1 + description: BDMA and DMAMUX2 Clock Enable + name: BDMAEN + - bit_offset: 24 + bit_size: 1 + description: ADC3 Peripheral Clocks Enable + name: ADC3EN + - bit_offset: 25 + bit_size: 1 + description: HSEM peripheral clock enable + name: HSEMEN + - bit_offset: 28 + bit_size: 1 + description: Backup RAM Clock Enable + name: BKPRAMEN fieldset/AHB4LPENR: description: RCC AHB4 Sleep Clock Register fields: - - name: GPIOALPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - - name: GPIOBLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: GPIOCLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 2 - bit_size: 1 - - name: GPIODLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - - name: GPIOELPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - name: GPIOFLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - name: GPIOGLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - - name: GPIOHLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 7 - bit_size: 1 - - name: GPIOILPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 8 - bit_size: 1 - - name: GPIOJLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 9 - bit_size: 1 - - name: GPIOKLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 10 - bit_size: 1 - - name: CRCLPEN - description: CRC peripheral clock enable during CSleep mode - bit_offset: 19 - bit_size: 1 - - name: BDMALPEN - description: BDMA Clock Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - - name: ADC3LPEN - description: ADC3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 24 - bit_size: 1 - - name: BKPRAMLPEN - description: Backup RAM Clock Enable During CSleep Mode - bit_offset: 28 - bit_size: 1 - - name: SRAM4LPEN - description: SRAM4 Clock Enable During CSleep Mode - bit_offset: 29 - bit_size: 1 + - bit_offset: 0 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOALPEN + - bit_offset: 1 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOBLPEN + - bit_offset: 2 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOCLPEN + - bit_offset: 3 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIODLPEN + - bit_offset: 4 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOELPEN + - bit_offset: 5 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOFLPEN + - bit_offset: 6 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOGLPEN + - bit_offset: 7 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOHLPEN + - bit_offset: 8 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOILPEN + - bit_offset: 9 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOJLPEN + - bit_offset: 10 + bit_size: 1 + description: GPIO peripheral clock enable during CSleep mode + name: GPIOKLPEN + - bit_offset: 19 + bit_size: 1 + description: CRC peripheral clock enable during CSleep mode + name: CRCLPEN + - bit_offset: 21 + bit_size: 1 + description: BDMA Clock Enable During CSleep Mode + name: BDMALPEN + - bit_offset: 24 + bit_size: 1 + description: ADC3 Peripheral Clocks Enable During CSleep Mode + name: ADC3LPEN + - bit_offset: 28 + bit_size: 1 + description: Backup RAM Clock Enable During CSleep Mode + name: BKPRAMLPEN + - bit_offset: 29 + bit_size: 1 + description: SRAM4 Clock Enable During CSleep Mode + name: SRAM4LPEN fieldset/AHB4RSTR: description: RCC AHB4 Peripheral Reset Register fields: - - name: GPIOARST - description: GPIO block reset - bit_offset: 0 - bit_size: 1 - - name: GPIOBRST - description: GPIO block reset - bit_offset: 1 - bit_size: 1 - - name: GPIOCRST - description: GPIO block reset - bit_offset: 2 - bit_size: 1 - - name: GPIODRST - description: GPIO block reset - bit_offset: 3 - bit_size: 1 - - name: GPIOERST - description: GPIO block reset - bit_offset: 4 - bit_size: 1 - - name: GPIOFRST - description: GPIO block reset - bit_offset: 5 - bit_size: 1 - - name: GPIOGRST - description: GPIO block reset - bit_offset: 6 - bit_size: 1 - - name: GPIOHRST - description: GPIO block reset - bit_offset: 7 - bit_size: 1 - - name: GPIOIRST - description: GPIO block reset - bit_offset: 8 - bit_size: 1 - - name: GPIOJRST - description: GPIO block reset - bit_offset: 9 - bit_size: 1 - - name: GPIOKRST - description: GPIO block reset - bit_offset: 10 - bit_size: 1 - - name: CRCRST - description: CRC block reset - bit_offset: 19 - bit_size: 1 - - name: BDMARST - description: BDMA block reset - bit_offset: 21 - bit_size: 1 - - name: ADC3RST - description: ADC3 block reset - bit_offset: 24 - bit_size: 1 - - name: HSEMRST - description: HSEM block reset - bit_offset: 25 - bit_size: 1 + - bit_offset: 0 + bit_size: 1 + description: GPIO block reset + name: GPIOARST + - bit_offset: 1 + bit_size: 1 + description: GPIO block reset + name: GPIOBRST + - bit_offset: 2 + bit_size: 1 + description: GPIO block reset + name: GPIOCRST + - bit_offset: 3 + bit_size: 1 + description: GPIO block reset + name: GPIODRST + - bit_offset: 4 + bit_size: 1 + description: GPIO block reset + name: GPIOERST + - bit_offset: 5 + bit_size: 1 + description: GPIO block reset + name: GPIOFRST + - bit_offset: 6 + bit_size: 1 + description: GPIO block reset + name: GPIOGRST + - bit_offset: 7 + bit_size: 1 + description: GPIO block reset + name: GPIOHRST + - bit_offset: 8 + bit_size: 1 + description: GPIO block reset + name: GPIOIRST + - bit_offset: 9 + bit_size: 1 + description: GPIO block reset + name: GPIOJRST + - bit_offset: 10 + bit_size: 1 + description: GPIO block reset + name: GPIOKRST + - bit_offset: 19 + bit_size: 1 + description: CRC block reset + name: CRCRST + - bit_offset: 21 + bit_size: 1 + description: BDMA block reset + name: BDMARST + - bit_offset: 24 + bit_size: 1 + description: ADC3 block reset + name: ADC3RST + - bit_offset: 25 + bit_size: 1 + description: HSEM block reset + name: HSEMRST fieldset/APB1HENR: description: RCC APB1 Clock Register fields: - - name: CRSEN - description: Clock Recovery System peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: SWPEN - description: SWPMI Peripheral Clocks Enable - bit_offset: 2 - bit_size: 1 - - name: OPAMPEN - description: OPAMP peripheral clock enable - bit_offset: 4 - bit_size: 1 - - name: MDIOSEN - description: MDIOS peripheral clock enable - bit_offset: 5 - bit_size: 1 - - name: FDCANEN - description: FDCAN Peripheral Clocks Enable - bit_offset: 8 - bit_size: 1 + - bit_offset: 1 + bit_size: 1 + description: Clock Recovery System peripheral clock enable + name: CRSEN + - bit_offset: 2 + bit_size: 1 + description: SWPMI Peripheral Clocks Enable + name: SWPEN + - bit_offset: 4 + bit_size: 1 + description: OPAMP peripheral clock enable + name: OPAMPEN + - bit_offset: 5 + bit_size: 1 + description: MDIOS peripheral clock enable + name: MDIOSEN + - bit_offset: 8 + bit_size: 1 + description: FDCAN Peripheral Clocks Enable + name: FDCANEN fieldset/APB1HLPENR: description: RCC APB1 High Sleep Clock Register fields: - - name: CRSLPEN - description: Clock Recovery System peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: SWPLPEN - description: SWPMI Peripheral Clocks Enable During CSleep Mode - bit_offset: 2 - bit_size: 1 - - name: OPAMPLPEN - description: OPAMP peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - name: MDIOSLPEN - description: MDIOS peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - name: FDCANLPEN - description: FDCAN Peripheral Clocks Enable During CSleep Mode - bit_offset: 8 - bit_size: 1 + - bit_offset: 1 + bit_size: 1 + description: Clock Recovery System peripheral clock enable during CSleep mode + name: CRSLPEN + - bit_offset: 2 + bit_size: 1 + description: SWPMI Peripheral Clocks Enable During CSleep Mode + name: SWPLPEN + - bit_offset: 4 + bit_size: 1 + description: OPAMP peripheral clock enable during CSleep mode + name: OPAMPLPEN + - bit_offset: 5 + bit_size: 1 + description: MDIOS peripheral clock enable during CSleep mode + name: MDIOSLPEN + - bit_offset: 8 + bit_size: 1 + description: FDCAN Peripheral Clocks Enable During CSleep Mode + name: FDCANLPEN fieldset/APB1HRSTR: description: RCC APB1 Peripheral Reset Register fields: - - name: CRSRST - description: Clock Recovery System reset - bit_offset: 1 - bit_size: 1 - - name: SWPRST - description: SWPMI block reset - bit_offset: 2 - bit_size: 1 - - name: OPAMPRST - description: OPAMP block reset - bit_offset: 4 - bit_size: 1 - - name: MDIOSRST - description: MDIOS block reset - bit_offset: 5 - bit_size: 1 - - name: FDCANRST - description: FDCAN block reset - bit_offset: 8 - bit_size: 1 + - bit_offset: 1 + bit_size: 1 + description: Clock Recovery System reset + name: CRSRST + - bit_offset: 2 + bit_size: 1 + description: SWPMI block reset + name: SWPRST + - bit_offset: 4 + bit_size: 1 + description: OPAMP block reset + name: OPAMPRST + - bit_offset: 5 + bit_size: 1 + description: MDIOS block reset + name: MDIOSRST + - bit_offset: 8 + bit_size: 1 + description: FDCAN block reset + name: FDCANRST fieldset/APB1LENR: description: RCC APB1 Clock Register fields: - - name: TIM2EN - description: TIM peripheral clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM3EN - description: TIM peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: TIM4EN - description: TIM peripheral clock enable - bit_offset: 2 - bit_size: 1 - - name: TIM5EN - description: TIM peripheral clock enable - bit_offset: 3 - bit_size: 1 - - name: TIM6EN - description: TIM peripheral clock enable - bit_offset: 4 - bit_size: 1 - - name: TIM7EN - description: TIM peripheral clock enable - bit_offset: 5 - bit_size: 1 - - name: TIM12EN - description: TIM peripheral clock enable - bit_offset: 6 - bit_size: 1 - - name: TIM13EN - description: TIM peripheral clock enable - bit_offset: 7 - bit_size: 1 - - name: TIM14EN - description: TIM peripheral clock enable - bit_offset: 8 - bit_size: 1 - - name: LPTIM1EN - description: LPTIM1 Peripheral Clocks Enable - bit_offset: 9 - bit_size: 1 - - name: SPI2EN - description: SPI2 Peripheral Clocks Enable - bit_offset: 14 - bit_size: 1 - - name: SPI3EN - description: SPI3 Peripheral Clocks Enable - bit_offset: 15 - bit_size: 1 - - name: SPDIFRXEN - description: SPDIFRX Peripheral Clocks Enable - bit_offset: 16 - bit_size: 1 - - name: USART2EN - description: USART2 Peripheral Clocks Enable - bit_offset: 17 - bit_size: 1 - - name: USART3EN - description: USART3 Peripheral Clocks Enable - bit_offset: 18 - bit_size: 1 - - name: UART4EN - description: UART4 Peripheral Clocks Enable - bit_offset: 19 - bit_size: 1 - - name: UART5EN - description: UART5 Peripheral Clocks Enable - bit_offset: 20 - bit_size: 1 - - name: I2C1EN - description: I2C1 Peripheral Clocks Enable - bit_offset: 21 - bit_size: 1 - - name: I2C2EN - description: I2C2 Peripheral Clocks Enable - bit_offset: 22 - bit_size: 1 - - name: I2C3EN - description: I2C3 Peripheral Clocks Enable - bit_offset: 23 - bit_size: 1 - - name: CECEN - description: HDMI-CEC peripheral clock enable - bit_offset: 27 - bit_size: 1 - - name: DAC12EN - description: DAC1&2 peripheral clock enable - bit_offset: 29 - bit_size: 1 - - name: UART7EN - description: UART7 Peripheral Clocks Enable - bit_offset: 30 - bit_size: 1 - - name: UART8EN - description: UART8 Peripheral Clocks Enable - bit_offset: 31 - bit_size: 1 + - bit_offset: 0 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM2EN + - bit_offset: 1 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM3EN + - bit_offset: 2 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM4EN + - bit_offset: 3 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM5EN + - bit_offset: 4 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM6EN + - bit_offset: 5 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM7EN + - bit_offset: 6 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM12EN + - bit_offset: 7 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM13EN + - bit_offset: 8 + bit_size: 1 + description: TIM peripheral clock enable + name: TIM14EN + - bit_offset: 9 + bit_size: 1 + description: LPTIM1 Peripheral Clocks Enable + name: LPTIM1EN + - bit_offset: 14 + bit_size: 1 + description: SPI2 Peripheral Clocks Enable + name: SPI2EN + - bit_offset: 15 + bit_size: 1 + description: SPI3 Peripheral Clocks Enable + name: SPI3EN + - bit_offset: 16 + bit_size: 1 + description: SPDIFRX Peripheral Clocks Enable + name: SPDIFRXEN + - bit_offset: 17 + bit_size: 1 + description: USART2 Peripheral Clocks Enable + name: USART2EN + - bit_offset: 18 + bit_size: 1 + description: USART3 Peripheral Clocks Enable + name: USART3EN + - bit_offset: 19 + bit_size: 1 + description: UART4 Peripheral Clocks Enable + name: UART4EN + - bit_offset: 20 + bit_size: 1 + description: UART5 Peripheral Clocks Enable + name: UART5EN + - bit_offset: 21 + bit_size: 1 + description: I2C1 Peripheral Clocks Enable + name: I2C1EN + - bit_offset: 22 + bit_size: 1 + description: I2C2 Peripheral Clocks Enable + name: I2C2EN + - bit_offset: 23 + bit_size: 1 + description: I2C3 Peripheral Clocks Enable + name: I2C3EN + - bit_offset: 27 + bit_size: 1 + description: HDMI-CEC peripheral clock enable + name: CECEN + - bit_offset: 30 + bit_size: 1 + description: UART7 Peripheral Clocks Enable + name: UART7EN + - bit_offset: 31 + bit_size: 1 + description: UART8 Peripheral Clocks Enable + name: UART8EN fieldset/APB1LLPENR: description: RCC APB1 Low Sleep Clock Register fields: - - name: TIM2LPEN - description: TIM2 peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM3LPEN - description: TIM3 peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: TIM4LPEN - description: TIM4 peripheral clock enable during CSleep mode - bit_offset: 2 - bit_size: 1 - - name: TIM5LPEN - description: TIM5 peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - - name: TIM6LPEN - description: TIM6 peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - name: TIM7LPEN - description: TIM7 peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - name: TIM12LPEN - description: TIM12 peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - - name: TIM13LPEN - description: TIM13 peripheral clock enable during CSleep mode - bit_offset: 7 - bit_size: 1 - - name: TIM14LPEN - description: TIM14 peripheral clock enable during CSleep mode - bit_offset: 8 - bit_size: 1 - - name: LPTIM1LPEN - description: LPTIM1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - - name: SPI2LPEN - description: SPI2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 14 - bit_size: 1 - - name: SPI3LPEN - description: SPI3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 15 - bit_size: 1 - - name: SPDIFRXLPEN - description: SPDIFRX Peripheral Clocks Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: USART2LPEN - description: USART2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 17 - bit_size: 1 - - name: USART3LPEN - description: USART3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 18 - bit_size: 1 - - name: UART4LPEN - description: UART4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 19 - bit_size: 1 - - name: UART5LPEN - description: UART5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 20 - bit_size: 1 - - name: I2C1LPEN - description: I2C1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - - name: I2C2LPEN - description: I2C2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 22 - bit_size: 1 - - name: I2C3LPEN - description: I2C3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 23 - bit_size: 1 - - name: CECLPEN - description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode - bit_offset: 27 - bit_size: 1 - - name: DAC12LPEN - description: DAC1/2 peripheral clock enable during CSleep mode - bit_offset: 29 - bit_size: 1 - - name: UART7LPEN - description: UART7 Peripheral Clocks Enable During CSleep Mode - bit_offset: 30 - bit_size: 1 - - name: UART8LPEN - description: UART8 Peripheral Clocks Enable During CSleep Mode - bit_offset: 31 - bit_size: 1 + - bit_offset: 0 + bit_size: 1 + description: TIM2 peripheral clock enable during CSleep mode + name: TIM2LPEN + - bit_offset: 1 + bit_size: 1 + description: TIM3 peripheral clock enable during CSleep mode + name: TIM3LPEN + - bit_offset: 2 + bit_size: 1 + description: TIM4 peripheral clock enable during CSleep mode + name: TIM4LPEN + - bit_offset: 3 + bit_size: 1 + description: TIM5 peripheral clock enable during CSleep mode + name: TIM5LPEN + - bit_offset: 4 + bit_size: 1 + description: TIM6 peripheral clock enable during CSleep mode + name: TIM6LPEN + - bit_offset: 5 + bit_size: 1 + description: TIM7 peripheral clock enable during CSleep mode + name: TIM7LPEN + - bit_offset: 6 + bit_size: 1 + description: TIM12 peripheral clock enable during CSleep mode + name: TIM12LPEN + - bit_offset: 7 + bit_size: 1 + description: TIM13 peripheral clock enable during CSleep mode + name: TIM13LPEN + - bit_offset: 8 + bit_size: 1 + description: TIM14 peripheral clock enable during CSleep mode + name: TIM14LPEN + - bit_offset: 9 + bit_size: 1 + description: LPTIM1 Peripheral Clocks Enable During CSleep Mode + name: LPTIM1LPEN + - bit_offset: 14 + bit_size: 1 + description: SPI2 Peripheral Clocks Enable During CSleep Mode + name: SPI2LPEN + - bit_offset: 15 + bit_size: 1 + description: SPI3 Peripheral Clocks Enable During CSleep Mode + name: SPI3LPEN + - bit_offset: 16 + bit_size: 1 + description: SPDIFRX Peripheral Clocks Enable During CSleep Mode + name: SPDIFRXLPEN + - bit_offset: 17 + bit_size: 1 + description: USART2 Peripheral Clocks Enable During CSleep Mode + name: USART2LPEN + - bit_offset: 18 + bit_size: 1 + description: USART3 Peripheral Clocks Enable During CSleep Mode + name: USART3LPEN + - bit_offset: 19 + bit_size: 1 + description: UART4 Peripheral Clocks Enable During CSleep Mode + name: UART4LPEN + - bit_offset: 20 + bit_size: 1 + description: UART5 Peripheral Clocks Enable During CSleep Mode + name: UART5LPEN + - bit_offset: 21 + bit_size: 1 + description: I2C1 Peripheral Clocks Enable During CSleep Mode + name: I2C1LPEN + - bit_offset: 22 + bit_size: 1 + description: I2C2 Peripheral Clocks Enable During CSleep Mode + name: I2C2LPEN + - bit_offset: 23 + bit_size: 1 + description: I2C3 Peripheral Clocks Enable During CSleep Mode + name: I2C3LPEN + - bit_offset: 27 + bit_size: 1 + description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode + name: CECLPEN + - bit_offset: 30 + bit_size: 1 + description: UART7 Peripheral Clocks Enable During CSleep Mode + name: UART7LPEN + - bit_offset: 31 + bit_size: 1 + description: UART8 Peripheral Clocks Enable During CSleep Mode + name: UART8LPEN fieldset/APB1LRSTR: description: RCC APB1 Peripheral Reset Register fields: - - name: TIM2RST - description: TIM block reset - bit_offset: 0 - bit_size: 1 - - name: TIM3RST - description: TIM block reset - bit_offset: 1 - bit_size: 1 - - name: TIM4RST - description: TIM block reset - bit_offset: 2 - bit_size: 1 - - name: TIM5RST - description: TIM block reset - bit_offset: 3 - bit_size: 1 - - name: TIM6RST - description: TIM block reset - bit_offset: 4 - bit_size: 1 - - name: TIM7RST - description: TIM block reset - bit_offset: 5 - bit_size: 1 - - name: TIM12RST - description: TIM block reset - bit_offset: 6 - bit_size: 1 - - name: TIM13RST - description: TIM block reset - bit_offset: 7 - bit_size: 1 - - name: TIM14RST - description: TIM block reset - bit_offset: 8 - bit_size: 1 - - name: LPTIM1RST - description: TIM block reset - bit_offset: 9 - bit_size: 1 - - name: SPI2RST - description: SPI2 block reset - bit_offset: 14 - bit_size: 1 - - name: SPI3RST - description: SPI3 block reset - bit_offset: 15 - bit_size: 1 - - name: SPDIFRXRST - description: SPDIFRX block reset - bit_offset: 16 - bit_size: 1 - - name: USART2RST - description: USART2 block reset - bit_offset: 17 - bit_size: 1 - - name: USART3RST - description: USART3 block reset - bit_offset: 18 - bit_size: 1 - - name: UART4RST - description: UART4 block reset - bit_offset: 19 - bit_size: 1 - - name: UART5RST - description: UART5 block reset - bit_offset: 20 - bit_size: 1 - - name: I2C1RST - description: I2C1 block reset - bit_offset: 21 - bit_size: 1 - - name: I2C2RST - description: I2C2 block reset - bit_offset: 22 - bit_size: 1 - - name: I2C3RST - description: I2C3 block reset - bit_offset: 23 - bit_size: 1 - - name: CECRST - description: HDMI-CEC block reset - bit_offset: 27 - bit_size: 1 - - name: DAC12RST - description: DAC1 and 2 Blocks Reset - bit_offset: 29 - bit_size: 1 - - name: UART7RST - description: UART7 block reset - bit_offset: 30 - bit_size: 1 - - name: UART8RST - description: UART8 block reset - bit_offset: 31 - bit_size: 1 + - bit_offset: 0 + bit_size: 1 + description: TIM block reset + name: TIM2RST + - bit_offset: 1 + bit_size: 1 + description: TIM block reset + name: TIM3RST + - bit_offset: 2 + bit_size: 1 + description: TIM block reset + name: TIM4RST + - bit_offset: 3 + bit_size: 1 + description: TIM block reset + name: TIM5RST + - bit_offset: 4 + bit_size: 1 + description: TIM block reset + name: TIM6RST + - bit_offset: 5 + bit_size: 1 + description: TIM block reset + name: TIM7RST + - bit_offset: 6 + bit_size: 1 + description: TIM block reset + name: TIM12RST + - bit_offset: 7 + bit_size: 1 + description: TIM block reset + name: TIM13RST + - bit_offset: 8 + bit_size: 1 + description: TIM block reset + name: TIM14RST + - bit_offset: 9 + bit_size: 1 + description: TIM block reset + name: LPTIM1RST + - bit_offset: 14 + bit_size: 1 + description: SPI2 block reset + name: SPI2RST + - bit_offset: 15 + bit_size: 1 + description: SPI3 block reset + name: SPI3RST + - bit_offset: 16 + bit_size: 1 + description: SPDIFRX block reset + name: SPDIFRXRST + - bit_offset: 17 + bit_size: 1 + description: USART2 block reset + name: USART2RST + - bit_offset: 18 + bit_size: 1 + description: USART3 block reset + name: USART3RST + - bit_offset: 19 + bit_size: 1 + description: UART4 block reset + name: UART4RST + - bit_offset: 20 + bit_size: 1 + description: UART5 block reset + name: UART5RST + - bit_offset: 21 + bit_size: 1 + description: I2C1 block reset + name: I2C1RST + - bit_offset: 22 + bit_size: 1 + description: I2C2 block reset + name: I2C2RST + - bit_offset: 23 + bit_size: 1 + description: I2C3 block reset + name: I2C3RST + - bit_offset: 27 + bit_size: 1 + description: HDMI-CEC block reset + name: CECRST + - bit_offset: 30 + bit_size: 1 + description: UART7 block reset + name: UART7RST + - bit_offset: 31 + bit_size: 1 + description: UART8 block reset + name: UART8RST fieldset/APB2ENR: description: RCC APB2 Clock Register fields: - - name: TIM1EN - description: TIM1 peripheral clock enable - bit_offset: 0 - bit_size: 1 - - name: TIM8EN - description: TIM8 peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: USART1EN - description: USART1 Peripheral Clocks Enable - bit_offset: 4 - bit_size: 1 - - name: USART6EN - description: USART6 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - - name: SPI1EN - description: SPI1 Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - - name: SPI4EN - description: SPI4 Peripheral Clocks Enable - bit_offset: 13 - bit_size: 1 - - name: TIM15EN - description: TIM15 peripheral clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM16EN - description: TIM16 peripheral clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: TIM17 peripheral clock enable - bit_offset: 18 - bit_size: 1 - - name: SPI5EN - description: SPI5 Peripheral Clocks Enable - bit_offset: 20 - bit_size: 1 - - name: SAI1EN - description: SAI1 Peripheral Clocks Enable - bit_offset: 22 - bit_size: 1 - - name: SAI2EN - description: SAI2 Peripheral Clocks Enable - bit_offset: 23 - bit_size: 1 - - name: SAI3EN - description: SAI3 Peripheral Clocks Enable - bit_offset: 24 - bit_size: 1 - - name: DFSDM1EN - description: DFSDM1 Peripheral Clocks Enable - bit_offset: 28 - bit_size: 1 - - name: HRTIMEN - description: HRTIM peripheral clock enable - bit_offset: 29 - bit_size: 1 + - bit_offset: 0 + bit_size: 1 + description: TIM1 peripheral clock enable + name: TIM1EN + - bit_offset: 1 + bit_size: 1 + description: TIM8 peripheral clock enable + name: TIM8EN + - bit_offset: 4 + bit_size: 1 + description: USART1 Peripheral Clocks Enable + name: USART1EN + - bit_offset: 5 + bit_size: 1 + description: USART6 Peripheral Clocks Enable + name: USART6EN + - bit_offset: 12 + bit_size: 1 + description: SPI1 Peripheral Clocks Enable + name: SPI1EN + - bit_offset: 13 + bit_size: 1 + description: SPI4 Peripheral Clocks Enable + name: SPI4EN + - bit_offset: 16 + bit_size: 1 + description: TIM15 peripheral clock enable + name: TIM15EN + - bit_offset: 17 + bit_size: 1 + description: TIM16 peripheral clock enable + name: TIM16EN + - bit_offset: 18 + bit_size: 1 + description: TIM17 peripheral clock enable + name: TIM17EN + - bit_offset: 20 + bit_size: 1 + description: SPI5 Peripheral Clocks Enable + name: SPI5EN + - bit_offset: 22 + bit_size: 1 + description: SAI1 Peripheral Clocks Enable + name: SAI1EN + - bit_offset: 23 + bit_size: 1 + description: SAI2 Peripheral Clocks Enable + name: SAI2EN + - bit_offset: 24 + bit_size: 1 + description: SAI3 Peripheral Clocks Enable + name: SAI3EN + - bit_offset: 28 + bit_size: 1 + description: DFSDM1 Peripheral Clocks Enable + name: DFSDM1EN + - bit_offset: 29 + bit_size: 1 + description: HRTIM peripheral clock enable + name: HRTIMEN fieldset/APB2LPENR: description: RCC APB2 Sleep Clock Register fields: - - name: TIM1LPEN - description: TIM1 peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - - name: TIM8LPEN - description: TIM8 peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: USART1LPEN - description: USART1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 4 - bit_size: 1 - - name: USART6LPEN - description: USART6 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - name: SPI1LPEN - description: SPI1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - - name: SPI4LPEN - description: SPI4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 13 - bit_size: 1 - - name: TIM15LPEN - description: TIM15 peripheral clock enable during CSleep mode - bit_offset: 16 - bit_size: 1 - - name: TIM16LPEN - description: TIM16 peripheral clock enable during CSleep mode - bit_offset: 17 - bit_size: 1 - - name: TIM17LPEN - description: TIM17 peripheral clock enable during CSleep mode - bit_offset: 18 - bit_size: 1 - - name: SPI5LPEN - description: SPI5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 20 - bit_size: 1 - - name: SAI1LPEN - description: SAI1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 22 - bit_size: 1 - - name: SAI2LPEN - description: SAI2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 23 - bit_size: 1 - - name: SAI3LPEN - description: SAI3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 24 - bit_size: 1 - - name: DFSDM1LPEN - description: DFSDM1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 28 - bit_size: 1 - - name: HRTIMLPEN - description: HRTIM peripheral clock enable during CSleep mode - bit_offset: 29 - bit_size: 1 + - bit_offset: 0 + bit_size: 1 + description: TIM1 peripheral clock enable during CSleep mode + name: TIM1LPEN + - bit_offset: 1 + bit_size: 1 + description: TIM8 peripheral clock enable during CSleep mode + name: TIM8LPEN + - bit_offset: 4 + bit_size: 1 + description: USART1 Peripheral Clocks Enable During CSleep Mode + name: USART1LPEN + - bit_offset: 5 + bit_size: 1 + description: USART6 Peripheral Clocks Enable During CSleep Mode + name: USART6LPEN + - bit_offset: 12 + bit_size: 1 + description: SPI1 Peripheral Clocks Enable During CSleep Mode + name: SPI1LPEN + - bit_offset: 13 + bit_size: 1 + description: SPI4 Peripheral Clocks Enable During CSleep Mode + name: SPI4LPEN + - bit_offset: 16 + bit_size: 1 + description: TIM15 peripheral clock enable during CSleep mode + name: TIM15LPEN + - bit_offset: 17 + bit_size: 1 + description: TIM16 peripheral clock enable during CSleep mode + name: TIM16LPEN + - bit_offset: 18 + bit_size: 1 + description: TIM17 peripheral clock enable during CSleep mode + name: TIM17LPEN + - bit_offset: 20 + bit_size: 1 + description: SPI5 Peripheral Clocks Enable During CSleep Mode + name: SPI5LPEN + - bit_offset: 22 + bit_size: 1 + description: SAI1 Peripheral Clocks Enable During CSleep Mode + name: SAI1LPEN + - bit_offset: 23 + bit_size: 1 + description: SAI2 Peripheral Clocks Enable During CSleep Mode + name: SAI2LPEN + - bit_offset: 24 + bit_size: 1 + description: SAI3 Peripheral Clocks Enable During CSleep Mode + name: SAI3LPEN + - bit_offset: 28 + bit_size: 1 + description: DFSDM1 Peripheral Clocks Enable During CSleep Mode + name: DFSDM1LPEN + - bit_offset: 29 + bit_size: 1 + description: HRTIM peripheral clock enable during CSleep mode + name: HRTIMLPEN fieldset/APB2RSTR: description: RCC APB2 Peripheral Reset Register fields: - - name: TIM1RST - description: TIM1 block reset - bit_offset: 0 - bit_size: 1 - - name: TIM8RST - description: TIM8 block reset - bit_offset: 1 - bit_size: 1 - - name: USART1RST - description: USART1 block reset - bit_offset: 4 - bit_size: 1 - - name: USART6RST - description: USART6 block reset - bit_offset: 5 - bit_size: 1 - - name: SPI1RST - description: SPI1 block reset - bit_offset: 12 - bit_size: 1 - - name: SPI4RST - description: SPI4 block reset - bit_offset: 13 - bit_size: 1 - - name: TIM15RST - description: TIM15 block reset - bit_offset: 16 - bit_size: 1 - - name: TIM16RST - description: TIM16 block reset - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: TIM17 block reset - bit_offset: 18 - bit_size: 1 - - name: SPI5RST - description: SPI5 block reset - bit_offset: 20 - bit_size: 1 - - name: SAI1RST - description: SAI1 block reset - bit_offset: 22 - bit_size: 1 - - name: SAI2RST - description: SAI2 block reset - bit_offset: 23 - bit_size: 1 - - name: SAI3RST - description: SAI3 block reset - bit_offset: 24 - bit_size: 1 - - name: DFSDM1RST - description: DFSDM1 block reset - bit_offset: 28 - bit_size: 1 - - name: HRTIMRST - description: HRTIM block reset - bit_offset: 29 - bit_size: 1 + - bit_offset: 0 + bit_size: 1 + description: TIM1 block reset + name: TIM1RST + - bit_offset: 1 + bit_size: 1 + description: TIM8 block reset + name: TIM8RST + - bit_offset: 4 + bit_size: 1 + description: USART1 block reset + name: USART1RST + - bit_offset: 5 + bit_size: 1 + description: USART6 block reset + name: USART6RST + - bit_offset: 12 + bit_size: 1 + description: SPI1 block reset + name: SPI1RST + - bit_offset: 13 + bit_size: 1 + description: SPI4 block reset + name: SPI4RST + - bit_offset: 16 + bit_size: 1 + description: TIM15 block reset + name: TIM15RST + - bit_offset: 17 + bit_size: 1 + description: TIM16 block reset + name: TIM16RST + - bit_offset: 18 + bit_size: 1 + description: TIM17 block reset + name: TIM17RST + - bit_offset: 20 + bit_size: 1 + description: SPI5 block reset + name: SPI5RST + - bit_offset: 22 + bit_size: 1 + description: SAI1 block reset + name: SAI1RST + - bit_offset: 23 + bit_size: 1 + description: SAI2 block reset + name: SAI2RST + - bit_offset: 24 + bit_size: 1 + description: SAI3 block reset + name: SAI3RST + - bit_offset: 28 + bit_size: 1 + description: DFSDM1 block reset + name: DFSDM1RST + - bit_offset: 29 + bit_size: 1 + description: HRTIM block reset + name: HRTIMRST fieldset/APB3ENR: description: RCC APB3 Clock Register fields: - - name: LTDCEN - description: LTDC peripheral clock enable - bit_offset: 3 - bit_size: 1 - - name: WWDG1EN - description: WWDG1 Clock Enable - bit_offset: 6 - bit_size: 1 + - bit_offset: 3 + bit_size: 1 + description: LTDC peripheral clock enable + name: LTDCEN + - bit_offset: 6 + bit_size: 1 + description: WWDG1 Clock Enable + name: WWDG1EN fieldset/APB3LPENR: description: RCC APB3 Sleep Clock Register fields: - - name: LTDCLPEN - description: LTDC peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - - name: WWDG1LPEN - description: WWDG1 Clock Enable During CSleep Mode - bit_offset: 6 - bit_size: 1 + - bit_offset: 3 + bit_size: 1 + description: LTDC peripheral clock enable during CSleep mode + name: LTDCLPEN + - bit_offset: 6 + bit_size: 1 + description: WWDG1 Clock Enable During CSleep Mode + name: WWDG1LPEN fieldset/APB3RSTR: description: RCC APB3 Peripheral Reset Register fields: - - name: LTDCRST - description: LTDC block reset - bit_offset: 3 - bit_size: 1 + - bit_offset: 3 + bit_size: 1 + description: LTDC block reset + name: LTDCRST fieldset/APB4ENR: description: RCC APB4 Clock Register fields: - - name: SYSCFGEN - description: SYSCFG peripheral clock enable - bit_offset: 1 - bit_size: 1 - - name: LPUART1EN - description: LPUART1 Peripheral Clocks Enable - bit_offset: 3 - bit_size: 1 - - name: SPI6EN - description: SPI6 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - - name: I2C4EN - description: I2C4 Peripheral Clocks Enable - bit_offset: 7 - bit_size: 1 - - name: LPTIM2EN - description: LPTIM2 Peripheral Clocks Enable - bit_offset: 9 - bit_size: 1 - - name: LPTIM3EN - description: LPTIM3 Peripheral Clocks Enable - bit_offset: 10 - bit_size: 1 - - name: LPTIM4EN - description: LPTIM4 Peripheral Clocks Enable - bit_offset: 11 - bit_size: 1 - - name: LPTIM5EN - description: LPTIM5 Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - - name: COMP12EN - description: COMP1/2 peripheral clock enable - bit_offset: 14 - bit_size: 1 - - name: VREFEN - description: VREF peripheral clock enable - bit_offset: 15 - bit_size: 1 - - name: RTCAPBEN - description: RTC APB Clock Enable - bit_offset: 16 - bit_size: 1 - - name: SAI4EN - description: SAI4 Peripheral Clocks Enable - bit_offset: 21 - bit_size: 1 + - bit_offset: 1 + bit_size: 1 + description: SYSCFG peripheral clock enable + name: SYSCFGEN + - bit_offset: 3 + bit_size: 1 + description: LPUART1 Peripheral Clocks Enable + name: LPUART1EN + - bit_offset: 5 + bit_size: 1 + description: SPI6 Peripheral Clocks Enable + name: SPI6EN + - bit_offset: 7 + bit_size: 1 + description: I2C4 Peripheral Clocks Enable + name: I2C4EN + - bit_offset: 9 + bit_size: 1 + description: LPTIM2 Peripheral Clocks Enable + name: LPTIM2EN + - bit_offset: 10 + bit_size: 1 + description: LPTIM3 Peripheral Clocks Enable + name: LPTIM3EN + - bit_offset: 14 + bit_size: 1 + description: COMP1/2 peripheral clock enable + name: COMP12EN + - bit_offset: 15 + bit_size: 1 + description: VREF peripheral clock enable + name: VREFEN + - bit_offset: 16 + bit_size: 1 + description: RTC APB Clock Enable + name: RTCAPBEN + - bit_offset: 21 + bit_size: 1 + description: SAI4 Peripheral Clocks Enable + name: SAI4EN fieldset/APB4LPENR: description: RCC APB4 Sleep Clock Register fields: - - name: SYSCFGLPEN - description: SYSCFG peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - name: LPUART1LPEN - description: LPUART1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 3 - bit_size: 1 - - name: SPI6LPEN - description: SPI6 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - name: I2C4LPEN - description: I2C4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 7 - bit_size: 1 - - name: LPTIM2LPEN - description: LPTIM2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - - name: LPTIM3LPEN - description: LPTIM3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 10 - bit_size: 1 - - name: LPTIM4LPEN - description: LPTIM4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 11 - bit_size: 1 - - name: LPTIM5LPEN - description: LPTIM5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - - name: COMP12LPEN - description: COMP1/2 peripheral clock enable during CSleep mode - bit_offset: 14 - bit_size: 1 - - name: VREFLPEN - description: VREF peripheral clock enable during CSleep mode - bit_offset: 15 - bit_size: 1 - - name: RTCAPBLPEN - description: RTC APB Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: SAI4LPEN - description: SAI4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 + - bit_offset: 1 + bit_size: 1 + description: SYSCFG peripheral clock enable during CSleep mode + name: SYSCFGLPEN + - bit_offset: 3 + bit_size: 1 + description: LPUART1 Peripheral Clocks Enable During CSleep Mode + name: LPUART1LPEN + - bit_offset: 5 + bit_size: 1 + description: SPI6 Peripheral Clocks Enable During CSleep Mode + name: SPI6LPEN + - bit_offset: 7 + bit_size: 1 + description: I2C4 Peripheral Clocks Enable During CSleep Mode + name: I2C4LPEN + - bit_offset: 9 + bit_size: 1 + description: LPTIM2 Peripheral Clocks Enable During CSleep Mode + name: LPTIM2LPEN + - bit_offset: 10 + bit_size: 1 + description: LPTIM3 Peripheral Clocks Enable During CSleep Mode + name: LPTIM3LPEN + - bit_offset: 14 + bit_size: 1 + description: COMP1/2 peripheral clock enable during CSleep mode + name: COMP12LPEN + - bit_offset: 15 + bit_size: 1 + description: VREF peripheral clock enable during CSleep mode + name: VREFLPEN + - bit_offset: 16 + bit_size: 1 + description: RTC APB Clock Enable During CSleep Mode + name: RTCAPBLPEN + - bit_offset: 21 + bit_size: 1 + description: SAI4 Peripheral Clocks Enable During CSleep Mode + name: SAI4LPEN fieldset/APB4RSTR: description: RCC APB4 Peripheral Reset Register fields: - - name: SYSCFGRST - description: SYSCFG block reset - bit_offset: 1 - bit_size: 1 - - name: LPUART1RST - description: LPUART1 block reset - bit_offset: 3 - bit_size: 1 - - name: SPI6RST - description: SPI6 block reset - bit_offset: 5 - bit_size: 1 - - name: I2C4RST - description: I2C4 block reset - bit_offset: 7 - bit_size: 1 - - name: LPTIM2RST - description: LPTIM2 block reset - bit_offset: 9 - bit_size: 1 - - name: LPTIM3RST - description: LPTIM3 block reset - bit_offset: 10 - bit_size: 1 - - name: LPTIM4RST - description: LPTIM4 block reset - bit_offset: 11 - bit_size: 1 - - name: LPTIM5RST - description: LPTIM5 block reset - bit_offset: 12 - bit_size: 1 - - name: COMP12RST - description: COMP12 Blocks Reset - bit_offset: 14 - bit_size: 1 - - name: VREFRST - description: VREF block reset - bit_offset: 15 - bit_size: 1 - - name: SAI4RST - description: SAI4 block reset - bit_offset: 21 - bit_size: 1 + - bit_offset: 1 + bit_size: 1 + description: SYSCFG block reset + name: SYSCFGRST + - bit_offset: 3 + bit_size: 1 + description: LPUART1 block reset + name: LPUART1RST + - bit_offset: 5 + bit_size: 1 + description: SPI6 block reset + name: SPI6RST + - bit_offset: 7 + bit_size: 1 + description: I2C4 block reset + name: I2C4RST + - bit_offset: 9 + bit_size: 1 + description: LPTIM2 block reset + name: LPTIM2RST + - bit_offset: 10 + bit_size: 1 + description: LPTIM3 block reset + name: LPTIM3RST + - bit_offset: 14 + bit_size: 1 + description: COMP12 Blocks Reset + name: COMP12RST + - bit_offset: 15 + bit_size: 1 + description: VREF block reset + name: VREFRST + - bit_offset: 21 + bit_size: 1 + description: SAI4 block reset + name: SAI4RST fieldset/BDCR: description: RCC Backup Domain Control Register fields: - - name: LSEON - description: LSE oscillator enabled - bit_offset: 0 - bit_size: 1 - enum: LSEON - - name: LSERDY - description: LSE oscillator ready - bit_offset: 1 - bit_size: 1 - enum_read: LSERDYR - - name: LSEBYP - description: LSE oscillator bypass - bit_offset: 2 - bit_size: 1 - enum: LSEBYP - - name: LSEDRV - description: LSE oscillator driving capability - bit_offset: 3 - bit_size: 2 - enum: LSEDRV - - name: LSECSSON - description: LSE clock security system enable - bit_offset: 5 - bit_size: 1 - enum: LSECSSON - - name: LSECSSD - description: LSE clock security system failure detection - bit_offset: 6 - bit_size: 1 - enum_read: LSECSSDR - - name: RTCSEL - description: RTC clock source selection - bit_offset: 8 - bit_size: 2 - enum: RTCSEL - - name: RTCEN - description: RTC clock enable - bit_offset: 15 - bit_size: 1 - - name: BDRST - description: VSwitch domain software reset - bit_offset: 16 - bit_size: 1 -fieldset/C1_AHB1ENR: - description: RCC AHB1 Clock Register - fields: - - name: DMA1EN - description: DMA1 Clock Enable - bit_offset: 0 - bit_size: 1 - - name: DMA2EN - description: DMA2 Clock Enable - bit_offset: 1 - bit_size: 1 - - name: ADC12EN - description: ADC1/2 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - - name: ETH1MACEN - description: Ethernet MAC bus interface Clock Enable - bit_offset: 15 - bit_size: 1 - - name: ETH1TXEN - description: Ethernet Transmission Clock Enable - bit_offset: 16 - bit_size: 1 - - name: ETH1RXEN - description: Ethernet Reception Clock Enable - bit_offset: 17 - bit_size: 1 - - name: USB1OTGEN - description: USB1OTG Peripheral Clocks Enable - bit_offset: 25 - bit_size: 1 - - name: USB1ULPIEN - description: USB_PHY1 Clocks Enable - bit_offset: 26 - bit_size: 1 - - name: USB2OTGEN - description: USB2OTG Peripheral Clocks Enable - bit_offset: 27 - bit_size: 1 - - name: USB2ULPIEN - description: USB_PHY2 Clocks Enable - bit_offset: 28 - bit_size: 1 -fieldset/C1_AHB1LPENR: - description: RCC AHB1 Sleep Clock Register - fields: - - name: DMA1LPEN - description: DMA1 Clock Enable During CSleep Mode - bit_offset: 0 - bit_size: 1 - - name: DMA2LPEN - description: DMA2 Clock Enable During CSleep Mode - bit_offset: 1 - bit_size: 1 - - name: ADC12LPEN - description: ADC1/2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - name: ETH1MACLPEN - description: Ethernet MAC bus interface Clock Enable During CSleep Mode - bit_offset: 15 - bit_size: 1 - - name: ETH1TXLPEN - description: Ethernet Transmission Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - name: ETH1RXLPEN - description: Ethernet Reception Clock Enable During CSleep Mode - bit_offset: 17 - bit_size: 1 - - name: USB1OTGLPEN - description: USB1OTG peripheral clock enable during CSleep mode - bit_offset: 25 - bit_size: 1 - - name: USB1ULPILPEN - description: USB_PHY1 clock enable during CSleep mode - bit_offset: 26 - bit_size: 1 - - name: USB2OTGLPEN - description: USB2OTG peripheral clock enable during CSleep mode - bit_offset: 27 - bit_size: 1 - - name: USB2ULPILPEN - description: USB_PHY2 clocks enable during CSleep mode - bit_offset: 28 - bit_size: 1 -fieldset/C1_AHB2ENR: - description: RCC AHB2 Clock Register - fields: - - name: DCMIEN - description: DCMI peripheral clock - bit_offset: 0 - bit_size: 1 - - name: CRYPTEN - description: CRYPT peripheral clock enable - bit_offset: 4 - bit_size: 1 - - - name: HASHEN - description: HASH peripheral clock enable - bit_offset: 5 - bit_size: 1 - - - name: RNGEN - description: RNG peripheral clocks enable - bit_offset: 6 - bit_size: 1 - - - name: SDMMC2EN - description: SDMMC2 and SDMMC2 delay clock enable - bit_offset: 9 - bit_size: 1 - - - name: SRAM1EN - description: SRAM1 block enable - bit_offset: 29 - bit_size: 1 - - - name: SRAM2EN - description: SRAM2 block enable - bit_offset: 30 - bit_size: 1 - - - name: SRAM3EN - description: SRAM3 block enable - bit_offset: 31 - bit_size: 1 - -fieldset/C1_AHB2LPENR: - description: RCC AHB2 Sleep Clock Register - fields: - - name: DCMILPEN - description: DCMI peripheral clock enable during csleep mode - bit_offset: 0 - bit_size: 1 - - - name: CRYPTLPEN - description: CRYPT peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - - name: HASHLPEN - description: HASH peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - - name: RNGLPEN - description: RNG peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - - - name: SDMMC2LPEN - description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - - - name: SRAM1LPEN - description: SRAM1 Clock Enable During CSleep Mode - bit_offset: 29 - bit_size: 1 - - - name: SRAM2LPEN - description: SRAM2 Clock Enable During CSleep Mode - bit_offset: 30 - bit_size: 1 - - - name: SRAM3LPEN - description: SRAM3 Clock Enable During CSleep Mode - bit_offset: 31 - bit_size: 1 - -fieldset/C1_AHB3ENR: - description: RCC AHB3 Clock Register - fields: - - name: MDMAEN - description: MDMA Peripheral Clock Enable - bit_offset: 0 - bit_size: 1 - - - name: DMA2DEN - description: DMA2D Peripheral Clock Enable - bit_offset: 4 - bit_size: 1 - - - name: JPGDECEN - description: JPGDEC Peripheral Clock Enable - bit_offset: 5 - bit_size: 1 - - - name: FMCEN - description: FMC Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - - - name: QSPIEN - description: QUADSPI and QUADSPI Delay Clock Enable - bit_offset: 14 - bit_size: 1 - - - name: SDMMC1EN - description: SDMMC1 and SDMMC1 Delay Clock Enable - bit_offset: 16 - bit_size: 1 - -fieldset/C1_AHB3LPENR: - description: RCC AHB3 Sleep Clock Register - fields: - - name: MDMALPEN - description: MDMA Clock Enable During CSleep Mode - bit_offset: 0 - bit_size: 1 - - - name: DMA2DLPEN - description: DMA2D Clock Enable During CSleep Mode - bit_offset: 4 - bit_size: 1 - - - name: JPGDECLPEN - description: JPGDEC Clock Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - - name: FLASHPREN - description: Flash interface clock enable during csleep mode - bit_offset: 8 - bit_size: 1 - - name: FMCLPEN - description: FMC Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - - - name: QSPILPEN - description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode - bit_offset: 14 - bit_size: 1 - - - name: SDMMC1LPEN - description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - - name: D1DTCM1LPEN - description: D1DTCM1 Block Clock Enable During CSleep mode - bit_offset: 28 - bit_size: 1 - - - name: DTCM2LPEN - description: D1 DTCM2 Block Clock Enable During CSleep mode - bit_offset: 29 - bit_size: 1 - - - name: ITCMLPEN - description: D1ITCM Block Clock Enable During CSleep mode - bit_offset: 30 - bit_size: 1 - - - name: AXISRAMLPEN - description: AXISRAM Block Clock Enable During CSleep mode - bit_offset: 31 - bit_size: 1 - -fieldset/C1_AHB4ENR: - description: RCC AHB4 Clock Register - fields: - - name: GPIOAEN - description: 0GPIO peripheral clock enable - bit_offset: 0 - bit_size: 1 - - - name: GPIOBEN - description: 0GPIO peripheral clock enable - bit_offset: 1 - bit_size: 1 - - - name: GPIOCEN - description: 0GPIO peripheral clock enable - bit_offset: 2 - bit_size: 1 - - - name: GPIODEN - description: 0GPIO peripheral clock enable - bit_offset: 3 - bit_size: 1 - - - name: GPIOEEN - description: 0GPIO peripheral clock enable - bit_offset: 4 - bit_size: 1 - - - name: GPIOFEN - description: 0GPIO peripheral clock enable - bit_offset: 5 - bit_size: 1 - - - name: GPIOGEN - description: 0GPIO peripheral clock enable - bit_offset: 6 - bit_size: 1 - - - name: GPIOHEN - description: 0GPIO peripheral clock enable - bit_offset: 7 - bit_size: 1 - - - name: GPIOIEN - description: 0GPIO peripheral clock enable - bit_offset: 8 - bit_size: 1 - - - name: GPIOJEN - description: 0GPIO peripheral clock enable - bit_offset: 9 - bit_size: 1 - - - name: GPIOKEN - description: 0GPIO peripheral clock enable - bit_offset: 10 - bit_size: 1 - - - name: CRCEN - description: CRC peripheral clock enable - bit_offset: 19 - bit_size: 1 - - - name: BDMAEN - description: BDMA and DMAMUX2 Clock Enable - bit_offset: 21 - bit_size: 1 - - - name: ADC3EN - description: ADC3 Peripheral Clocks Enable - bit_offset: 24 - bit_size: 1 - - - name: HSEMEN - description: HSEM peripheral clock enable - bit_offset: 25 - bit_size: 1 - - - name: BKPRAMEN - description: Backup RAM Clock Enable - bit_offset: 28 - bit_size: 1 - -fieldset/C1_AHB4LPENR: - description: RCC AHB4 Sleep Clock Register - fields: - - name: GPIOALPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - - - name: GPIOBLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - - name: GPIOCLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 2 - bit_size: 1 - - - name: GPIODLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - - - name: GPIOELPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - - name: GPIOFLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - - name: GPIOGLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - - - name: GPIOHLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 7 - bit_size: 1 - - - name: GPIOILPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 8 - bit_size: 1 - - - name: GPIOJLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 9 - bit_size: 1 - - - name: GPIOKLPEN - description: GPIO peripheral clock enable during CSleep mode - bit_offset: 10 - bit_size: 1 - - - name: CRCLPEN - description: CRC peripheral clock enable during CSleep mode - bit_offset: 19 - bit_size: 1 - - - name: BDMALPEN - description: BDMA Clock Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - - - name: ADC3LPEN - description: ADC3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 24 - bit_size: 1 - - - name: BKPRAMLPEN - description: Backup RAM Clock Enable During CSleep Mode - bit_offset: 28 - bit_size: 1 - - - name: SRAM4LPEN - description: SRAM4 Clock Enable During CSleep Mode - bit_offset: 29 - bit_size: 1 - -fieldset/C1_APB1HENR: - description: RCC APB1 Clock Register - fields: - - name: CRSEN - description: Clock Recovery System peripheral clock enable - bit_offset: 1 - bit_size: 1 - - - name: SWPEN - description: SWPMI Peripheral Clocks Enable - bit_offset: 2 - bit_size: 1 - - - name: OPAMPEN - description: OPAMP peripheral clock enable - bit_offset: 4 - bit_size: 1 - - - name: MDIOSEN - description: MDIOS peripheral clock enable - bit_offset: 5 - bit_size: 1 - - - name: FDCANEN - description: FDCAN Peripheral Clocks Enable - bit_offset: 8 - bit_size: 1 - -fieldset/C1_APB1HLPENR: - description: RCC APB1 High Sleep Clock Register - fields: - - name: CRSLPEN - description: Clock Recovery System peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - - name: SWPLPEN - description: SWPMI Peripheral Clocks Enable During CSleep Mode - bit_offset: 2 - bit_size: 1 - - - name: OPAMPLPEN - description: OPAMP peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - - name: MDIOSLPEN - description: MDIOS peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - - name: FDCANLPEN - description: FDCAN Peripheral Clocks Enable During CSleep Mode - bit_offset: 8 - bit_size: 1 - -fieldset/C1_APB1LENR: - description: RCC APB1 Clock Register - fields: - - name: TIM2EN - description: TIM peripheral clock enable - bit_offset: 0 - bit_size: 1 - - - name: TIM3EN - description: TIM peripheral clock enable - bit_offset: 1 - bit_size: 1 - - - name: TIM4EN - description: TIM peripheral clock enable - bit_offset: 2 - bit_size: 1 - - - name: TIM5EN - description: TIM peripheral clock enable - bit_offset: 3 - bit_size: 1 - - - name: TIM6EN - description: TIM peripheral clock enable - bit_offset: 4 - bit_size: 1 - - - name: TIM7EN - description: TIM peripheral clock enable - bit_offset: 5 - bit_size: 1 - - - name: TIM12EN - description: TIM peripheral clock enable - bit_offset: 6 - bit_size: 1 - - - name: TIM13EN - description: TIM peripheral clock enable - bit_offset: 7 - bit_size: 1 - - - name: TIM14EN - description: TIM peripheral clock enable - bit_offset: 8 - bit_size: 1 - - - name: LPTIM1EN - description: LPTIM1 Peripheral Clocks Enable - bit_offset: 9 - bit_size: 1 - - - name: SPI2EN - description: SPI2 Peripheral Clocks Enable - bit_offset: 14 - bit_size: 1 - - - name: SPI3EN - description: SPI3 Peripheral Clocks Enable - bit_offset: 15 - bit_size: 1 - - - name: SPDIFRXEN - description: SPDIFRX Peripheral Clocks Enable - bit_offset: 16 - bit_size: 1 - - - name: USART2EN - description: USART2 Peripheral Clocks Enable - bit_offset: 17 - bit_size: 1 - - - name: USART3EN - description: USART3 Peripheral Clocks Enable - bit_offset: 18 - bit_size: 1 - - - name: UART4EN - description: UART4 Peripheral Clocks Enable - bit_offset: 19 - bit_size: 1 - - - name: UART5EN - description: UART5 Peripheral Clocks Enable - bit_offset: 20 - bit_size: 1 - - - name: I2C1EN - description: I2C1 Peripheral Clocks Enable - bit_offset: 21 - bit_size: 1 - - - name: I2C2EN - description: I2C2 Peripheral Clocks Enable - bit_offset: 22 - bit_size: 1 - - - name: I2C3EN - description: I2C3 Peripheral Clocks Enable - bit_offset: 23 - bit_size: 1 - - - name: CECEN - description: HDMI-CEC peripheral clock enable - bit_offset: 27 - bit_size: 1 - - - name: DAC12EN - description: DAC1&2 peripheral clock enable - bit_offset: 29 - bit_size: 1 - - - name: UART7EN - description: UART7 Peripheral Clocks Enable - bit_offset: 30 - bit_size: 1 - - - name: UART8EN - description: UART8 Peripheral Clocks Enable - bit_offset: 31 - bit_size: 1 - -fieldset/C1_APB1LLPENR: - description: RCC APB1 Low Sleep Clock Register - fields: - - name: TIM2LPEN - description: TIM2 peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - - - name: TIM3LPEN - description: TIM3 peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - - name: TIM4LPEN - description: TIM4 peripheral clock enable during CSleep mode - bit_offset: 2 - bit_size: 1 - - - name: TIM5LPEN - description: TIM5 peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - - - name: TIM6LPEN - description: TIM6 peripheral clock enable during CSleep mode - bit_offset: 4 - bit_size: 1 - - - name: TIM7LPEN - description: TIM7 peripheral clock enable during CSleep mode - bit_offset: 5 - bit_size: 1 - - - name: TIM12LPEN - description: TIM12 peripheral clock enable during CSleep mode - bit_offset: 6 - bit_size: 1 - - - name: TIM13LPEN - description: TIM13 peripheral clock enable during CSleep mode - bit_offset: 7 - bit_size: 1 - - - name: TIM14LPEN - description: TIM14 peripheral clock enable during CSleep mode - bit_offset: 8 - bit_size: 1 - - - name: LPTIM1LPEN - description: LPTIM1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - - - name: SPI2LPEN - description: SPI2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 14 - bit_size: 1 - - - name: SPI3LPEN - description: SPI3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 15 - bit_size: 1 - - - name: SPDIFRXLPEN - description: SPDIFRX Peripheral Clocks Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - - name: USART2LPEN - description: USART2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 17 - bit_size: 1 - - - name: USART3LPEN - description: USART3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 18 - bit_size: 1 - - - name: UART4LPEN - description: UART4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 19 - bit_size: 1 - - - name: UART5LPEN - description: UART5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 20 - bit_size: 1 - - - name: I2C1LPEN - description: I2C1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - - - name: I2C2LPEN - description: I2C2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 22 - bit_size: 1 - - - name: I2C3LPEN - description: I2C3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 23 - bit_size: 1 - - - name: CECLPEN - description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode - bit_offset: 27 - bit_size: 1 - - - name: DAC12LPEN - description: DAC1/2 peripheral clock enable during CSleep mode - bit_offset: 29 - bit_size: 1 - - - name: UART7LPEN - description: UART7 Peripheral Clocks Enable During CSleep Mode - bit_offset: 30 - bit_size: 1 - - - name: UART8LPEN - description: UART8 Peripheral Clocks Enable During CSleep Mode - bit_offset: 31 - bit_size: 1 - -fieldset/C1_APB2ENR: - description: RCC APB2 Clock Register - fields: - - name: TIM1EN - description: TIM1 peripheral clock enable - bit_offset: 0 - bit_size: 1 - - - name: TIM8EN - description: TIM8 peripheral clock enable - bit_offset: 1 - bit_size: 1 - - - name: USART1EN - description: USART1 Peripheral Clocks Enable - bit_offset: 4 - bit_size: 1 - - - name: USART6EN - description: USART6 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - - - name: SPI1EN - description: SPI1 Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - - - name: SPI4EN - description: SPI4 Peripheral Clocks Enable - bit_offset: 13 - bit_size: 1 - - - name: TIM15EN - description: TIM15 peripheral clock enable - bit_offset: 16 - bit_size: 1 - - - name: TIM16EN - description: TIM16 peripheral clock enable - bit_offset: 17 - bit_size: 1 - - - name: TIM17EN - description: TIM17 peripheral clock enable - bit_offset: 18 - bit_size: 1 - - - name: SPI5EN - description: SPI5 Peripheral Clocks Enable - bit_offset: 20 - bit_size: 1 - - - name: SAI1EN - description: SAI1 Peripheral Clocks Enable - bit_offset: 22 - bit_size: 1 - - - name: SAI2EN - description: SAI2 Peripheral Clocks Enable - bit_offset: 23 - bit_size: 1 - - - name: SAI3EN - description: SAI3 Peripheral Clocks Enable - bit_offset: 24 - bit_size: 1 - - - name: DFSDM1EN - description: DFSDM1 Peripheral Clocks Enable - bit_offset: 28 - bit_size: 1 - - - name: HRTIMEN - description: HRTIM peripheral clock enable - bit_offset: 29 - bit_size: 1 - -fieldset/C1_APB2LPENR: - description: RCC APB2 Sleep Clock Register - fields: - - name: TIM1LPEN - description: TIM1 peripheral clock enable during CSleep mode - bit_offset: 0 - bit_size: 1 - - - name: TIM8LPEN - description: TIM8 peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - - name: USART1LPEN - description: USART1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 4 - bit_size: 1 - - - name: USART6LPEN - description: USART6 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - - name: SPI1LPEN - description: SPI1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - - - name: SPI4LPEN - description: SPI4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 13 - bit_size: 1 - - - name: TIM15LPEN - description: TIM15 peripheral clock enable during CSleep mode - bit_offset: 16 - bit_size: 1 - - - name: TIM16LPEN - description: TIM16 peripheral clock enable during CSleep mode - bit_offset: 17 - bit_size: 1 - - - name: TIM17LPEN - description: TIM17 peripheral clock enable during CSleep mode - bit_offset: 18 - bit_size: 1 - - - name: SPI5LPEN - description: SPI5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 20 - bit_size: 1 - - - name: SAI1LPEN - description: SAI1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 22 - bit_size: 1 - - - name: SAI2LPEN - description: SAI2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 23 - bit_size: 1 - - - name: SAI3LPEN - description: SAI3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 24 - bit_size: 1 - - - name: DFSDM1LPEN - description: DFSDM1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 28 - bit_size: 1 - - - name: HRTIMLPEN - description: HRTIM peripheral clock enable during CSleep mode - bit_offset: 29 - bit_size: 1 - -fieldset/C1_APB3ENR: - description: RCC APB3 Clock Register - fields: - - name: LTDCEN - description: LTDC peripheral clock enable - bit_offset: 3 - bit_size: 1 - - - name: WWDG1EN - description: WWDG1 Clock Enable - bit_offset: 6 - bit_size: 1 - -fieldset/C1_APB3LPENR: - description: RCC APB3 Sleep Clock Register - fields: - - name: LTDCLPEN - description: LTDC peripheral clock enable during CSleep mode - bit_offset: 3 - bit_size: 1 - - - name: WWDG1LPEN - description: WWDG1 Clock Enable During CSleep Mode - bit_offset: 6 - bit_size: 1 - -fieldset/C1_APB4ENR: - description: RCC APB4 Clock Register - fields: - - name: SYSCFGEN - description: SYSCFG peripheral clock enable - bit_offset: 1 - bit_size: 1 - - - name: LPUART1EN - description: LPUART1 Peripheral Clocks Enable - bit_offset: 3 - bit_size: 1 - - - name: SPI6EN - description: SPI6 Peripheral Clocks Enable - bit_offset: 5 - bit_size: 1 - - - name: I2C4EN - description: I2C4 Peripheral Clocks Enable - bit_offset: 7 - bit_size: 1 - - - name: LPTIM2EN - description: LPTIM2 Peripheral Clocks Enable - bit_offset: 9 - bit_size: 1 - - - name: LPTIM3EN - description: LPTIM3 Peripheral Clocks Enable - bit_offset: 10 - bit_size: 1 - - - name: LPTIM4EN - description: LPTIM4 Peripheral Clocks Enable - bit_offset: 11 - bit_size: 1 - - - name: LPTIM5EN - description: LPTIM5 Peripheral Clocks Enable - bit_offset: 12 - bit_size: 1 - - - name: COMP12EN - description: COMP1/2 peripheral clock enable - bit_offset: 14 - bit_size: 1 - - - name: VREFEN - description: VREF peripheral clock enable - bit_offset: 15 - bit_size: 1 - - - name: RTCAPBEN - description: RTC APB Clock Enable - bit_offset: 16 - bit_size: 1 - - - name: SAI4EN - description: SAI4 Peripheral Clocks Enable - bit_offset: 21 - bit_size: 1 - -fieldset/C1_APB4LPENR: - description: RCC APB4 Sleep Clock Register - fields: - - name: SYSCFGLPEN - description: SYSCFG peripheral clock enable during CSleep mode - bit_offset: 1 - bit_size: 1 - - - name: LPUART1LPEN - description: LPUART1 Peripheral Clocks Enable During CSleep Mode - bit_offset: 3 - bit_size: 1 - - - name: SPI6LPEN - description: SPI6 Peripheral Clocks Enable During CSleep Mode - bit_offset: 5 - bit_size: 1 - - - name: I2C4LPEN - description: I2C4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 7 - bit_size: 1 - - - name: LPTIM2LPEN - description: LPTIM2 Peripheral Clocks Enable During CSleep Mode - bit_offset: 9 - bit_size: 1 - - - name: LPTIM3LPEN - description: LPTIM3 Peripheral Clocks Enable During CSleep Mode - bit_offset: 10 - bit_size: 1 - - - name: LPTIM4LPEN - description: LPTIM4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 11 - bit_size: 1 - - - name: LPTIM5LPEN - description: LPTIM5 Peripheral Clocks Enable During CSleep Mode - bit_offset: 12 - bit_size: 1 - - - name: COMP12LPEN - description: COMP1/2 peripheral clock enable during CSleep mode - bit_offset: 14 - bit_size: 1 - - - name: VREFLPEN - description: VREF peripheral clock enable during CSleep mode - bit_offset: 15 - bit_size: 1 - - - name: RTCAPBLPEN - description: RTC APB Clock Enable During CSleep Mode - bit_offset: 16 - bit_size: 1 - - - name: SAI4LPEN - description: SAI4 Peripheral Clocks Enable During CSleep Mode - bit_offset: 21 - bit_size: 1 - + - bit_offset: 0 + bit_size: 1 + description: LSE oscillator enabled + enum: LSEON + name: LSEON + - bit_offset: 1 + bit_size: 1 + description: LSE oscillator ready + enum_read: LSERDYR + name: LSERDY + - bit_offset: 2 + bit_size: 1 + description: LSE oscillator bypass + enum: LSEBYP + name: LSEBYP + - bit_offset: 3 + bit_size: 2 + description: LSE oscillator driving capability + enum: LSEDRV + name: LSEDRV + - bit_offset: 5 + bit_size: 1 + description: LSE clock security system enable + enum: LSECSSON + name: LSECSSON + - bit_offset: 6 + bit_size: 1 + description: LSE clock security system failure detection + enum_read: LSECSSDR + name: LSECSSD + - bit_offset: 8 + bit_size: 2 + description: RTC clock source selection + enum: RTCSEL + name: RTCSEL + - bit_offset: 15 + bit_size: 1 + description: RTC clock enable + name: RTCEN + - bit_offset: 16 + bit_size: 1 + description: VSwitch domain software reset + name: BDRST fieldset/C1_RSR: description: RCC Reset Status Register fields: - - name: RMVF - description: Remove reset flag - bit_offset: 16 - bit_size: 1 - enum: C1_RSR_RMVF - - name: CPURSTF - description: CPU reset flag - bit_offset: 17 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR - - name: D1RSTF - description: D1 domain power switch reset flag - bit_offset: 19 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR - - name: D2RSTF - description: D2 domain power switch reset flag - bit_offset: 20 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR - - name: BORRSTF - description: BOR reset flag - bit_offset: 21 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR - - name: PINRSTF - description: Pin reset flag (NRST) - bit_offset: 22 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 23 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR - - name: SFTRSTF - description: System reset from CPU reset flag - bit_offset: 24 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR - - name: IWDG1RSTF - description: Independent Watchdog reset flag - bit_offset: 26 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR - - name: WWDG1RSTF - description: Window Watchdog reset flag - bit_offset: 28 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR - - name: LPWRRSTF - description: Reset due to illegal D1 DStandby or CPU CStop flag - bit_offset: 30 - bit_size: 1 - enum_read: C1_RSR_CPURSTFR + - bit_offset: 16 + bit_size: 1 + description: Remove reset flag + enum: RMVF + name: RMVF + - bit_offset: 17 + bit_size: 1 + description: CPU reset flag + enum_read: CPURSTFR + name: CPURSTF + - bit_offset: 19 + bit_size: 1 + description: D1 domain power switch reset flag + enum_read: CPURSTFR + name: D1RSTF + - bit_offset: 20 + bit_size: 1 + description: D2 domain power switch reset flag + enum_read: CPURSTFR + name: D2RSTF + - bit_offset: 21 + bit_size: 1 + description: BOR reset flag + enum_read: CPURSTFR + name: BORRSTF + - bit_offset: 22 + bit_size: 1 + description: Pin reset flag (NRST) + enum_read: CPURSTFR + name: PINRSTF + - bit_offset: 23 + bit_size: 1 + description: POR/PDR reset flag + enum_read: CPURSTFR + name: PORRSTF + - bit_offset: 24 + bit_size: 1 + description: System reset from CPU reset flag + enum_read: CPURSTFR + name: SFTRSTF + - bit_offset: 26 + bit_size: 1 + description: Independent Watchdog reset flag + enum_read: CPURSTFR + name: IWDG1RSTF + - bit_offset: 28 + bit_size: 1 + description: Window Watchdog reset flag + enum_read: CPURSTFR + name: WWDG1RSTF + - bit_offset: 30 + bit_size: 1 + description: Reset due to illegal D1 DStandby or CPU CStop flag + enum_read: CPURSTFR + name: LPWRRSTF fieldset/CFGR: description: RCC Clock Configuration Register fields: - - name: SW - description: System clock switch - bit_offset: 0 - bit_size: 3 - enum: SW - - name: SWS - description: System clock switch status - bit_offset: 3 - bit_size: 3 - enum_read: SWSR - - name: STOPWUCK - description: System clock selection after a wake up from system Stop - bit_offset: 6 - bit_size: 1 - enum: STOPWUCK - - name: STOPKERWUCK - description: Kernel clock selection after a wake up from system Stop - bit_offset: 7 - bit_size: 1 - enum: STOPWUCK - - name: RTCPRE - description: HSE division factor for RTC clock - bit_offset: 8 - bit_size: 6 - - name: HRTIMSEL - description: High Resolution Timer clock prescaler selection - bit_offset: 14 - bit_size: 1 - enum: HRTIMSEL - - name: TIMPRE - description: Timers clocks prescaler selection - bit_offset: 15 - bit_size: 1 - enum: TIMPRE - - name: MCO1PRE - description: MCO1 prescaler - bit_offset: 18 - bit_size: 4 - - name: MCO1 - description: Micro-controller clock output 1 - bit_offset: 22 - bit_size: 3 - enum: MCO1 - - name: MCO2PRE - description: MCO2 prescaler - bit_offset: 25 - bit_size: 4 - - name: MCO2 - description: Micro-controller clock output 2 - bit_offset: 29 - bit_size: 3 - enum: MCO2 + - bit_offset: 0 + bit_size: 3 + description: System clock switch + enum: SW + name: SW + - bit_offset: 3 + bit_size: 3 + description: System clock switch status + enum_read: SWSR + name: SWS + - bit_offset: 6 + bit_size: 1 + description: System clock selection after a wake up from system Stop + enum: STOPWUCK + name: STOPWUCK + - bit_offset: 7 + bit_size: 1 + description: Kernel clock selection after a wake up from system Stop + enum: STOPWUCK + name: STOPKERWUCK + - bit_offset: 8 + bit_size: 6 + description: HSE division factor for RTC clock + name: RTCPRE + - bit_offset: 14 + bit_size: 1 + description: High Resolution Timer clock prescaler selection + enum: HRTIMSEL + name: HRTIMSEL + - bit_offset: 15 + bit_size: 1 + description: Timers clocks prescaler selection + enum: TIMPRE + name: TIMPRE + - bit_offset: 18 + bit_size: 4 + description: MCO1 prescaler + name: MCO1PRE + - array: + len: 2 + stride: 7 + bit_offset: 22 + bit_size: 3 + description: Micro-controller clock output 1 + enum: MCO1 + name: MCO + - bit_offset: 25 + bit_size: 4 + description: MCO2 prescaler + name: MCO2PRE fieldset/CICR: description: RCC Clock Source Interrupt Clear Register fields: - - name: LSIRDYC - description: LSI ready Interrupt Clear - bit_offset: 0 - bit_size: 1 - enum: LSIRDYC - - name: LSERDYC - description: LSE ready Interrupt Clear - bit_offset: 1 - bit_size: 1 - enum: LSIRDYC - - name: HSIRDYC - description: HSI ready Interrupt Clear - bit_offset: 2 - bit_size: 1 - enum: LSIRDYC - - name: HSERDYC - description: HSE ready Interrupt Clear - bit_offset: 3 - bit_size: 1 - enum: LSIRDYC - - name: HSE_ready_Interrupt_Clear - description: CSI ready Interrupt Clear - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYC - description: RC48 ready Interrupt Clear - bit_offset: 5 - bit_size: 1 - enum: LSIRDYC - - name: PLLRDYC - description: PLL1 ready Interrupt Clear - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - enum: LSIRDYC - - name: LSECSSC - description: LSE clock security system Interrupt Clear - bit_offset: 9 - bit_size: 1 - enum: LSIRDYC - - name: HSECSSC - description: HSE clock security system Interrupt Clear - bit_offset: 10 - bit_size: 1 - enum: LSIRDYC + - bit_offset: 0 + bit_size: 1 + description: LSI ready Interrupt Clear + enum: LSIRDYC + name: LSIRDYC + - bit_offset: 1 + bit_size: 1 + description: LSE ready Interrupt Clear + enum: LSIRDYC + name: LSERDYC + - bit_offset: 2 + bit_size: 1 + description: HSI ready Interrupt Clear + enum: LSIRDYC + name: HSIRDYC + - bit_offset: 3 + bit_size: 1 + description: HSE ready Interrupt Clear + enum: LSIRDYC + name: HSERDYC + - bit_offset: 4 + bit_size: 1 + description: CSI ready Interrupt Clear + name: HSE_ready_Interrupt_Clear + - bit_offset: 5 + bit_size: 1 + description: RC48 ready Interrupt Clear + enum: LSIRDYC + name: HSI48RDYC + - bit_offset: 6 + bit_size: 1 + description: PLL1 ready Interrupt Clear + enum: LSIRDYC + name: PLL1RDYC + - bit_offset: 7 + bit_size: 1 + description: PLL2 ready Interrupt Clear + enum: LSIRDYC + name: PLL2RDYC + - bit_offset: 8 + bit_size: 1 + description: PLL3 ready Interrupt Clear + enum: LSIRDYC + name: PLL3RDYC + - bit_offset: 9 + bit_size: 1 + description: LSE clock security system Interrupt Clear + enum: LSIRDYC + name: LSECSSC + - bit_offset: 10 + bit_size: 1 + description: HSE clock security system Interrupt Clear + enum: LSIRDYC + name: HSECSSC fieldset/CIER: description: RCC Clock Source Interrupt Enable Register fields: - - name: LSIRDYIE - description: LSI ready Interrupt Enable - bit_offset: 0 - bit_size: 1 - enum: LSIRDYIE - - name: LSERDYIE - description: LSE ready Interrupt Enable - bit_offset: 1 - bit_size: 1 - enum: LSIRDYIE - - name: HSIRDYIE - description: HSI ready Interrupt Enable - bit_offset: 2 - bit_size: 1 - enum: LSIRDYIE - - name: HSERDYIE - description: HSE ready Interrupt Enable - bit_offset: 3 - bit_size: 1 - enum: LSIRDYIE - - name: CSIRDYIE - description: CSI ready Interrupt Enable - bit_offset: 4 - bit_size: 1 - enum: LSIRDYIE - - name: HSI48RDYIE - description: RC48 ready Interrupt Enable - bit_offset: 5 - bit_size: 1 - enum: LSIRDYIE - - name: PLLRDYIE - description: PLL1 ready Interrupt Enable - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - enum: LSIRDYIE - - name: LSECSSIE - description: LSE clock security system Interrupt Enable - bit_offset: 9 - bit_size: 1 - enum: LSIRDYIE + - bit_offset: 0 + bit_size: 1 + description: LSI ready Interrupt Enable + enum: LSIRDYIE + name: LSIRDYIE + - bit_offset: 1 + bit_size: 1 + description: LSE ready Interrupt Enable + enum: LSIRDYIE + name: LSERDYIE + - bit_offset: 2 + bit_size: 1 + description: HSI ready Interrupt Enable + enum: LSIRDYIE + name: HSIRDYIE + - bit_offset: 3 + bit_size: 1 + description: HSE ready Interrupt Enable + enum: LSIRDYIE + name: HSERDYIE + - bit_offset: 4 + bit_size: 1 + description: CSI ready Interrupt Enable + enum: LSIRDYIE + name: CSIRDYIE + - bit_offset: 5 + bit_size: 1 + description: RC48 ready Interrupt Enable + enum: LSIRDYIE + name: HSI48RDYIE + - bit_offset: 6 + bit_size: 1 + description: PLL1 ready Interrupt Enable + enum: LSIRDYIE + name: PLL1RDYIE + - bit_offset: 7 + bit_size: 1 + description: PLL2 ready Interrupt Enable + enum: LSIRDYIE + name: PLL2RDYIE + - bit_offset: 8 + bit_size: 1 + description: PLL3 ready Interrupt Enable + enum: LSIRDYIE + name: PLL3RDYIE + - bit_offset: 9 + bit_size: 1 + description: LSE clock security system Interrupt Enable + enum: LSIRDYIE + name: LSECSSIE fieldset/CIFR: description: RCC Clock Source Interrupt Flag Register fields: - - name: LSIRDYF - description: LSI ready Interrupt Flag - bit_offset: 0 - bit_size: 1 - - name: LSERDYF - description: LSE ready Interrupt Flag - bit_offset: 1 - bit_size: 1 - - name: HSIRDYF - description: HSI ready Interrupt Flag - bit_offset: 2 - bit_size: 1 - - name: HSERDYF - description: HSE ready Interrupt Flag - bit_offset: 3 - bit_size: 1 - - name: CSIRDY - description: CSI ready Interrupt Flag - bit_offset: 4 - bit_size: 1 - - name: HSI48RDYF - description: RC48 ready Interrupt Flag - bit_offset: 5 - bit_size: 1 - - name: PLLRDYF - description: PLL1 ready Interrupt Flag - bit_offset: 6 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: LSECSSF - description: LSE clock security system Interrupt Flag - bit_offset: 9 - bit_size: 1 - - name: HSECSSF - description: HSE clock security system Interrupt Flag - bit_offset: 10 - bit_size: 1 + - bit_offset: 0 + bit_size: 1 + description: LSI ready Interrupt Flag + name: LSIRDYF + - bit_offset: 1 + bit_size: 1 + description: LSE ready Interrupt Flag + name: LSERDYF + - bit_offset: 2 + bit_size: 1 + description: HSI ready Interrupt Flag + name: HSIRDYF + - bit_offset: 3 + bit_size: 1 + description: HSE ready Interrupt Flag + name: HSERDYF + - bit_offset: 4 + bit_size: 1 + description: CSI ready Interrupt Flag + name: CSIRDY + - bit_offset: 5 + bit_size: 1 + description: RC48 ready Interrupt Flag + name: HSI48RDYF + - bit_offset: 6 + bit_size: 1 + description: PLL1 ready Interrupt Flag + name: PLL1RDYF + - bit_offset: 7 + bit_size: 1 + description: PLL2 ready Interrupt Flag + name: PLL2RDYF + - bit_offset: 8 + bit_size: 1 + description: PLL3 ready Interrupt Flag + name: PLL3RDYF + - bit_offset: 9 + bit_size: 1 + description: LSE clock security system Interrupt Flag + name: LSECSSF + - bit_offset: 10 + bit_size: 1 + description: HSE clock security system Interrupt Flag + name: HSECSSF fieldset/CR: description: clock control register fields: - - name: HSION - description: Internal high-speed clock enable - bit_offset: 0 - bit_size: 1 - enum: HSION - - name: HSIKERON - description: High Speed Internal clock enable in Stop mode - bit_offset: 1 - bit_size: 1 - enum: HSION - - name: HSIRDY - description: HSI clock ready flag - bit_offset: 2 - bit_size: 1 - enum_read: HSIRDYR - - name: HSIDIV - description: HSI clock divider - bit_offset: 3 - bit_size: 2 - enum: HSIDIV - - name: HSIDIVF - description: HSI divider flag - bit_offset: 5 - bit_size: 1 - enum_read: HSIDIVFR - - name: CSION - description: CSI clock enable - bit_offset: 7 - bit_size: 1 - enum: HSION - - name: CSIRDY - description: CSI clock ready flag - bit_offset: 8 - bit_size: 1 - enum_read: HSIRDYR - - name: CSIKERON - description: CSI clock enable in Stop mode - bit_offset: 9 - bit_size: 1 - enum: HSION - - name: HSI48ON - description: RC48 clock enable - bit_offset: 12 - bit_size: 1 - enum: HSION - - name: HSI48RDY - description: RC48 clock ready flag - bit_offset: 13 - bit_size: 1 - enum_read: HSIRDYR - - name: D1CKRDY - description: D1 domain clocks ready flag - bit_offset: 14 - bit_size: 1 - enum_read: HSIRDYR - - name: D2CKRDY - description: D2 domain clocks ready flag - bit_offset: 15 - bit_size: 1 - enum_read: HSIRDYR - - name: HSEON - description: HSE clock enable - bit_offset: 16 - bit_size: 1 - enum: HSION - - name: HSERDY - description: HSE clock ready flag - bit_offset: 17 - bit_size: 1 - enum_read: HSIRDYR - - name: HSEBYP - description: HSE clock bypass - bit_offset: 18 - bit_size: 1 - enum: HSEBYP - - name: HSECSSON - description: HSE Clock Security System enable - bit_offset: 19 - bit_size: 1 - enum: HSION - - name: PLL1ON - description: PLL1 enable - bit_offset: 24 - bit_size: 1 - enum: HSION - - name: PLL1RDY - description: PLL1 clock ready flag - bit_offset: 25 - bit_size: 1 - enum_read: HSIRDYR - - name: PLL2ON - description: PLL2 enable - bit_offset: 26 - bit_size: 1 - enum: HSION - - name: PLL2RDY - description: PLL2 clock ready flag - bit_offset: 27 - bit_size: 1 - enum_read: HSIRDYR - - name: PLL3ON - description: PLL3 enable - bit_offset: 28 - bit_size: 1 - enum: HSION - - name: PLL3RDY - description: PLL3 clock ready flag - bit_offset: 29 - bit_size: 1 - enum_read: HSIRDYR + - bit_offset: 0 + bit_size: 1 + description: Internal high-speed clock enable + enum: HSION + name: HSION + - bit_offset: 1 + bit_size: 1 + description: High Speed Internal clock enable in Stop mode + enum: HSION + name: HSIKERON + - bit_offset: 2 + bit_size: 1 + description: HSI clock ready flag + enum_read: HSIRDYR + name: HSIRDY + - bit_offset: 3 + bit_size: 2 + description: HSI clock divider + enum: HSIDIV + name: HSIDIV + - bit_offset: 5 + bit_size: 1 + description: HSI divider flag + enum_read: HSIDIVFR + name: HSIDIVF + - bit_offset: 7 + bit_size: 1 + description: CSI clock enable + enum: HSION + name: CSION + - bit_offset: 8 + bit_size: 1 + description: CSI clock ready flag + enum_read: HSIRDYR + name: CSIRDY + - bit_offset: 9 + bit_size: 1 + description: CSI clock enable in Stop mode + enum: HSION + name: CSIKERON + - bit_offset: 12 + bit_size: 1 + description: RC48 clock enable + enum: HSION + name: HSI48ON + - bit_offset: 13 + bit_size: 1 + description: RC48 clock ready flag + enum_read: HSIRDYR + name: HSI48RDY + - bit_offset: 14 + bit_size: 1 + description: D1 domain clocks ready flag + enum_read: HSIRDYR + name: D1CKRDY + - bit_offset: 15 + bit_size: 1 + description: D2 domain clocks ready flag + enum_read: HSIRDYR + name: D2CKRDY + - bit_offset: 16 + bit_size: 1 + description: HSE clock enable + enum: HSION + name: HSEON + - bit_offset: 17 + bit_size: 1 + description: HSE clock ready flag + enum_read: HSIRDYR + name: HSERDY + - bit_offset: 18 + bit_size: 1 + description: HSE clock bypass + enum: HSEBYP + name: HSEBYP + - bit_offset: 19 + bit_size: 1 + description: HSE Clock Security System enable + enum: HSION + name: HSECSSON + - bit_offset: 24 + bit_size: 1 + description: PLL1 enable + enum: HSION + name: PLL1ON + - bit_offset: 25 + bit_size: 1 + description: PLL1 clock ready flag + enum_read: HSIRDYR + name: PLL1RDY + - bit_offset: 26 + bit_size: 1 + description: PLL2 enable + enum: HSION + name: PLL2ON + - bit_offset: 27 + bit_size: 1 + description: PLL2 clock ready flag + enum_read: HSIRDYR + name: PLL2RDY + - bit_offset: 28 + bit_size: 1 + description: PLL3 enable + enum: HSION + name: PLL3ON + - bit_offset: 29 + bit_size: 1 + description: PLL3 clock ready flag + enum_read: HSIRDYR + name: PLL3RDY fieldset/CRRCR: description: RCC Clock Recovery RC Register fields: - - name: HSI48CAL - description: Internal RC 48 MHz clock calibration - bit_offset: 0 - bit_size: 10 -fieldset/CSICFGR: - description: RCC CSI configuration register - fields: - - name: CSICAL - description: CSI clock calibration - bit_offset: 0 - bit_size: 9 - - name: CSITRIM - description: CSI clock trimming - bit_offset: 24 - bit_size: 6 + - bit_offset: 0 + bit_size: 10 + description: Internal RC 48 MHz clock calibration + name: HSI48CAL fieldset/CSR: description: RCC Clock Control and Status Register fields: - - name: LSION - description: LSI oscillator enable - bit_offset: 0 - bit_size: 1 - enum: LSION - - name: LSIRDY - description: LSI oscillator ready - bit_offset: 1 - bit_size: 1 - enum_read: LSIRDYR -fieldset/D1CCIPR: - description: RCC Domain 1 Kernel Clock Configuration Register - fields: - - name: FMCSEL - description: FMC kernel clock source selection - bit_offset: 0 - bit_size: 2 - enum: FMCSEL - - name: QSPISEL - description: QUADSPI kernel clock source selection - bit_offset: 4 - bit_size: 2 - enum: FMCSEL - - name: SDMMCSEL - description: SDMMC kernel clock source selection - bit_offset: 16 - bit_size: 1 - enum: SDMMCSEL - - name: CKPERSEL - description: per_ck clock source selection - bit_offset: 28 - bit_size: 2 - enum: CKPERSEL + - bit_offset: 0 + bit_size: 1 + description: LSI oscillator enable + enum: LSION + name: LSION + - bit_offset: 1 + bit_size: 1 + description: LSI oscillator ready + enum_read: LSIRDYR + name: LSIRDY fieldset/D1CFGR: description: RCC Domain 1 Clock Configuration Register fields: - - name: HPRE - description: D1 domain AHB prescaler - bit_offset: 0 - bit_size: 4 - enum: HPRE - - name: D1PPRE - description: D1 domain APB3 prescaler - bit_offset: 4 - bit_size: 3 - enum: D1PPRE - - name: D1CPRE - description: D1 domain Core prescaler - bit_offset: 8 - bit_size: 4 - enum: HPRE -fieldset/D2CCIP1R: - description: RCC Domain 2 Kernel Clock Configuration Register - fields: - - name: SAI1SEL - description: SAI1 and DFSDM1 kernel Aclk clock source selection - bit_offset: 0 - bit_size: 3 - enum: SAI1SEL - - name: SAI23SEL - description: SAI2 and SAI3 kernel clock source selection - bit_offset: 6 - bit_size: 3 - enum: SAI1SEL - - name: SPI123SEL - description: "SPI/I2S1,2 and 3 kernel clock source selection" - bit_offset: 12 - bit_size: 3 - enum: SAI1SEL - - name: SPI45SEL - description: SPI4 and 5 kernel clock source selection - bit_offset: 16 - bit_size: 3 - enum: SPI45SEL - - name: SPDIFSEL - description: SPDIFRX kernel clock source selection - bit_offset: 20 - bit_size: 2 - enum: SPDIFSEL - - name: DFSDM1SEL - description: DFSDM1 kernel Clk clock source selection - bit_offset: 24 - bit_size: 1 - enum: DFSDM1SEL - - name: FDCANSEL - description: FDCAN kernel clock source selection - bit_offset: 28 - bit_size: 2 - enum: FDCANSEL - - name: SWPSEL - description: SWPMI kernel clock source selection - bit_offset: 31 - bit_size: 1 - enum: SWPSEL -fieldset/D2CCIP2R: - description: RCC Domain 2 Kernel Clock Configuration Register - fields: - - name: USART234578SEL - description: "USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection" - bit_offset: 0 - bit_size: 3 - enum: USART234578SEL - - name: USART16SEL - description: USART1 and 6 kernel clock source selection - bit_offset: 3 - bit_size: 3 - enum: USART16SEL - - name: RNGSEL - description: RNG kernel clock source selection - bit_offset: 8 - bit_size: 2 - enum: RNGSEL - - name: I2C123SEL - description: "I2C1,2,3 kernel clock source selection" - bit_offset: 12 - bit_size: 2 - enum: I2C123SEL - - name: USBSEL - description: USBOTG 1 and 2 kernel clock source selection - bit_offset: 20 - bit_size: 2 - enum: USBSEL - - name: CECSEL - description: HDMI-CEC kernel clock source selection - bit_offset: 22 - bit_size: 2 - enum: CECSEL - - name: LPTIM1SEL - description: LPTIM1 kernel clock source selection - bit_offset: 28 - bit_size: 3 - enum: LPTIM1SEL + - bit_offset: 0 + bit_size: 4 + description: D1 domain AHB prescaler + enum: HPRE + name: HPRE + - bit_offset: 4 + bit_size: 3 + description: D1 domain APB3 prescaler + enum: DPPRE + name: D1PPRE + - bit_offset: 8 + bit_size: 4 + description: D1 domain Core prescaler + enum: HPRE + name: D1CPRE fieldset/D2CFGR: description: RCC Domain 2 Clock Configuration Register fields: - - name: D2PPRE1 - description: D2 domain APB1 prescaler - bit_offset: 4 - bit_size: 3 - enum: D2PPRE1 - - name: D2PPRE2 - description: D2 domain APB2 prescaler - bit_offset: 8 - bit_size: 3 - enum: D2PPRE1 + - bit_offset: 4 + bit_size: 3 + description: D2 domain APB1 prescaler + enum: DPPRE + name: D2PPRE1 + - bit_offset: 8 + bit_size: 3 + description: D2 domain APB2 prescaler + enum: DPPRE + name: D2PPRE2 fieldset/D3AMR: description: RCC D3 Autonomous mode Register fields: - - name: BDMAAMEN - description: BDMA and DMAMUX Autonomous mode enable - bit_offset: 0 - bit_size: 1 - - - name: LPUART1AMEN - description: LPUART1 Autonomous mode enable - bit_offset: 3 - bit_size: 1 - - - name: SPI6AMEN - description: SPI6 Autonomous mode enable - bit_offset: 5 - bit_size: 1 - - - name: I2C4AMEN - description: I2C4 Autonomous mode enable - bit_offset: 7 - bit_size: 1 - - - name: LPTIM2AMEN - description: LPTIM2 Autonomous mode enable - bit_offset: 9 - bit_size: 1 - - - name: LPTIM3AMEN - description: LPTIM3 Autonomous mode enable - bit_offset: 10 - bit_size: 1 - - - name: LPTIM4AMEN - description: LPTIM4 Autonomous mode enable - bit_offset: 11 - bit_size: 1 - - - name: LPTIM5AMEN - description: LPTIM5 Autonomous mode enable - bit_offset: 12 - bit_size: 1 - - - name: COMP12AMEN - description: COMP12 Autonomous mode enable - bit_offset: 14 - bit_size: 1 - - - name: VREFAMEN - description: VREF Autonomous mode enable - bit_offset: 15 - bit_size: 1 - - - name: RTCAMEN - description: RTC Autonomous mode enable - bit_offset: 16 - bit_size: 1 - - - name: CRCAMEN - description: CRC Autonomous mode enable - bit_offset: 19 - bit_size: 1 - - - name: SAI4AMEN - description: SAI4 Autonomous mode enable - bit_offset: 21 - bit_size: 1 - - - name: ADC3AMEN - description: ADC3 Autonomous mode enable - bit_offset: 24 - bit_size: 1 - - - name: BKPRAMAMEN - description: Backup RAM Autonomous mode enable - bit_offset: 28 - bit_size: 1 - - - name: SRAM4AMEN - description: SRAM4 Autonomous mode enable - bit_offset: 29 - bit_size: 1 - -fieldset/D3CCIPR: - description: RCC Domain 3 Kernel Clock Configuration Register - fields: - - name: LPUART1SEL - description: LPUART1 kernel clock source selection - bit_offset: 0 - bit_size: 3 - enum: LPUART1SEL - - name: I2C4SEL - description: I2C4 kernel clock source selection - bit_offset: 8 - bit_size: 2 - enum: I2C4SEL - - name: LPTIM2SEL - description: LPTIM2 kernel clock source selection - bit_offset: 10 - bit_size: 3 - enum: LPTIM2SEL - - name: LPTIM345SEL - description: "LPTIM3,4,5 kernel clock source selection" - bit_offset: 13 - bit_size: 3 - enum: LPTIM2SEL - - name: ADCSEL - description: SAR ADC kernel clock source selection - bit_offset: 16 - bit_size: 2 - enum: ADCSEL - - name: SAI4ASEL - description: Sub-Block A of SAI4 kernel clock source selection - bit_offset: 21 - bit_size: 3 - enum: SAI4ASEL - - name: SAI4BSEL - description: Sub-Block B of SAI4 kernel clock source selection - bit_offset: 24 - bit_size: 3 - enum: SAI4ASEL - - name: SPI6SEL - description: SPI6 kernel clock source selection - bit_offset: 28 - bit_size: 3 - enum: SPI6SEL + - bit_offset: 0 + bit_size: 1 + description: BDMA and DMAMUX Autonomous mode enable + name: BDMAAMEN + - bit_offset: 3 + bit_size: 1 + description: LPUART1 Autonomous mode enable + name: LPUART1AMEN + - bit_offset: 5 + bit_size: 1 + description: SPI6 Autonomous mode enable + name: SPI6AMEN + - bit_offset: 7 + bit_size: 1 + description: I2C4 Autonomous mode enable + name: I2C4AMEN + - bit_offset: 9 + bit_size: 1 + description: LPTIM2 Autonomous mode enable + name: LPTIM2AMEN + - bit_offset: 10 + bit_size: 1 + description: LPTIM3 Autonomous mode enable + name: LPTIM3AMEN + - bit_offset: 14 + bit_size: 1 + description: COMP12 Autonomous mode enable + name: COMP12AMEN + - bit_offset: 15 + bit_size: 1 + description: VREF Autonomous mode enable + name: VREFAMEN + - bit_offset: 16 + bit_size: 1 + description: RTC Autonomous mode enable + name: RTCAMEN + - bit_offset: 19 + bit_size: 1 + description: CRC Autonomous mode enable + name: CRCAMEN + - bit_offset: 21 + bit_size: 1 + description: SAI4 Autonomous mode enable + name: SAI4AMEN + - bit_offset: 24 + bit_size: 1 + description: ADC3 Autonomous mode enable + name: ADC3AMEN + - bit_offset: 29 + bit_size: 1 + description: SRAM4 Autonomous mode enable + name: SRAM4AMEN fieldset/D3CFGR: description: RCC Domain 3 Clock Configuration Register fields: - - name: D3PPRE - description: D3 domain APB4 prescaler - bit_offset: 4 - bit_size: 3 - enum: D3PPRE + - bit_offset: 4 + bit_size: 3 + description: D3 domain APB4 prescaler + enum: DPPRE + name: D3PPRE fieldset/GCR: description: RCC Global Control Register fields: - - name: WW1RSC - description: WWDG1 reset scope control - bit_offset: 0 - bit_size: 1 - enum: WW1RSC -fieldset/HSICFGR: - description: RCC HSI configuration register - fields: - - name: HSICAL - description: HSI clock calibration - bit_offset: 0 - bit_size: 12 - - name: HSITRIM - description: HSI clock trimming - bit_offset: 24 - bit_size: 7 -fieldset/ICSCR: - description: RCC Internal Clock Source Calibration Register - fields: - - name: HSICAL - description: HSI clock calibration - bit_offset: 0 - bit_size: 12 - - name: HSITRIM - description: HSI clock trimming - bit_offset: 12 - bit_size: 6 - - name: CSICAL - description: CSI clock calibration - bit_offset: 18 - bit_size: 8 - - name: CSITRIM - description: CSI clock trimming - bit_offset: 26 - bit_size: 5 + - bit_offset: 0 + bit_size: 1 + description: WWDG1 reset scope control + enum: WWRSC + name: WW1RSC fieldset/PLL1DIVR: description: RCC PLL1 Dividers Configuration Register fields: - - name: DIVN1 - description: Multiplication factor for PLL1 VCO - bit_offset: 0 - bit_size: 9 - - name: DIVP1 - description: PLL1 DIVP division factor - bit_offset: 9 - bit_size: 7 - enum: DIVP1 - - name: DIVQ1 - description: PLL1 DIVQ division factor - bit_offset: 16 - bit_size: 7 - - name: DIVR1 - description: PLL1 DIVR division factor - bit_offset: 24 - bit_size: 7 + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 9 + description: Multiplication factor for PLL1 VCO + name: DIVN + - array: + len: 1 + stride: 0 + bit_offset: 9 + bit_size: 7 + description: PLL1 DIVP division factor + enum: DIVP + name: DIVP + - array: + len: 1 + stride: 0 + bit_offset: 16 + bit_size: 7 + description: PLL1 DIVQ division factor + name: DIVQ + - array: + len: 1 + stride: 0 + bit_offset: 24 + bit_size: 7 + description: PLL1 DIVR division factor + name: DIVR fieldset/PLL1FRACR: description: RCC PLL1 Fractional Divider Register fields: - - name: FRACN1 - description: Fractional part of the multiplication factor for PLL1 VCO - bit_offset: 3 - bit_size: 13 + - array: + len: 1 + stride: 0 + bit_offset: 3 + bit_size: 13 + description: Fractional part of the multiplication factor for PLL1 VCO + name: FRACN fieldset/PLL2DIVR: description: RCC PLL2 Dividers Configuration Register fields: - - name: DIVN2 - description: Multiplication factor for PLL1 VCO - bit_offset: 0 - bit_size: 9 - - name: DIVP2 - description: PLL1 DIVP division factor - bit_offset: 9 - bit_size: 7 - - name: DIVQ2 - description: PLL1 DIVQ division factor - bit_offset: 16 - bit_size: 7 - - name: DIVR2 - description: PLL1 DIVR division factor - bit_offset: 24 - bit_size: 7 + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 9 + description: Multiplication factor for PLL1 VCO + name: DIVN + - array: + len: 1 + stride: 0 + bit_offset: 9 + bit_size: 7 + description: PLL1 DIVP division factor + name: DIVP + - array: + len: 1 + stride: 0 + bit_offset: 16 + bit_size: 7 + description: PLL1 DIVQ division factor + name: DIVQ + - array: + len: 1 + stride: 0 + bit_offset: 24 + bit_size: 7 + description: PLL1 DIVR division factor + name: DIVR fieldset/PLL2FRACR: description: RCC PLL2 Fractional Divider Register fields: - - name: FRACN2 - description: Fractional part of the multiplication factor for PLL VCO - bit_offset: 3 - bit_size: 13 + - array: + len: 1 + stride: 0 + bit_offset: 3 + bit_size: 13 + description: Fractional part of the multiplication factor for PLL VCO + name: FRACN fieldset/PLL3DIVR: description: RCC PLL3 Dividers Configuration Register fields: - - name: DIVN3 - description: Multiplication factor for PLL1 VCO - bit_offset: 0 - bit_size: 9 - - name: DIVP3 - description: PLL DIVP division factor - bit_offset: 9 - bit_size: 7 - - name: DIVQ3 - description: PLL DIVQ division factor - bit_offset: 16 - bit_size: 7 - - name: DIVR3 - description: PLL DIVR division factor - bit_offset: 24 - bit_size: 7 + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 9 + description: Multiplication factor for PLL1 VCO + name: DIVN + - array: + len: 1 + stride: 0 + bit_offset: 9 + bit_size: 7 + description: PLL DIVP division factor + name: DIVP + - array: + len: 1 + stride: 0 + bit_offset: 16 + bit_size: 7 + description: PLL DIVQ division factor + name: DIVQ + - array: + len: 1 + stride: 0 + bit_offset: 24 + bit_size: 7 + description: PLL DIVR division factor + name: DIVR fieldset/PLL3FRACR: description: RCC PLL3 Fractional Divider Register fields: - - name: FRACN3 - description: Fractional part of the multiplication factor for PLL3 VCO - bit_offset: 3 - bit_size: 13 + - array: + len: 1 + stride: 0 + bit_offset: 3 + bit_size: 13 + description: Fractional part of the multiplication factor for PLL3 VCO + name: FRACN fieldset/PLLCFGR: description: RCC PLLs Configuration Register fields: - - name: PLLFRACEN - description: PLL1 fractional latch enable - bit_offset: 0 - bit_size: 1 - array: - len: 3 - stride: 4 - - - name: PLLVCOSEL - description: PLL1 VCO selection - bit_offset: 1 - bit_size: 1 - array: - len: 3 - stride: 4 - enum: PLL1VCOSEL - - name: PLLRGE - description: PLL1 input frequency range - bit_offset: 2 - bit_size: 2 - array: - len: 3 - stride: 4 - enum: PLL1RGE - - name: DIVPEN - description: PLL1 DIVP divider output enable - bit_offset: 16 - bit_size: 1 - array: - len: 3 - stride: 3 - - - name: DIVQEN - description: PLL1 DIVQ divider output enable - bit_offset: 17 - bit_size: 1 - array: - len: 3 - stride: 3 - - - name: DIVREN - description: PLL1 DIVR divider output enable - bit_offset: 18 - bit_size: 1 - array: - len: 3 - stride: 3 - + - bit_offset: 0 + bit_size: 1 + description: PLL1 fractional latch enable + name: PLL1FRACEN + - bit_offset: 1 + bit_size: 1 + description: PLL1 VCO selection + enum: PLLVCOSEL + name: PLL1VCOSEL + - bit_offset: 2 + bit_size: 2 + description: PLL1 input frequency range + enum: PLLRGE + name: PLL1RGE + - bit_offset: 4 + bit_size: 1 + description: PLL2 fractional latch enable + name: PLL2FRACEN + - bit_offset: 5 + bit_size: 1 + description: PLL2 VCO selection + enum: PLLVCOSEL + name: PLL2VCOSEL + - bit_offset: 6 + bit_size: 2 + description: PLL2 input frequency range + enum: PLLRGE + name: PLL2RGE + - bit_offset: 8 + bit_size: 1 + description: PLL3 fractional latch enable + name: PLL3FRACEN + - bit_offset: 9 + bit_size: 1 + description: PLL3 VCO selection + enum: PLLVCOSEL + name: PLL3VCOSEL + - bit_offset: 10 + bit_size: 2 + description: PLL3 input frequency range + enum: PLLRGE + name: PLL3RGE + - bit_offset: 16 + bit_size: 1 + description: PLL1 DIVP divider output enable + name: DIVP1EN + - bit_offset: 17 + bit_size: 1 + description: PLL1 DIVQ divider output enable + name: DIVQ1EN + - bit_offset: 18 + bit_size: 1 + description: PLL1 DIVR divider output enable + name: DIVR1EN + - bit_offset: 19 + bit_size: 1 + description: PLL2 DIVP divider output enable + name: DIVP2EN + - bit_offset: 20 + bit_size: 1 + description: PLL2 DIVQ divider output enable + name: DIVQ2EN + - bit_offset: 21 + bit_size: 1 + description: PLL2 DIVR divider output enable + name: DIVR2EN + - bit_offset: 22 + bit_size: 1 + description: PLL3 DIVP divider output enable + name: DIVP3EN + - bit_offset: 23 + bit_size: 1 + description: PLL3 DIVQ divider output enable + name: DIVQ3EN + - bit_offset: 24 + bit_size: 1 + description: PLL3 DIVR divider output enable + name: DIVR3EN fieldset/PLLCKSELR: description: RCC PLLs Clock Source Selection Register fields: - - name: PLLSRC - description: DIVMx and PLLs clock source selection - bit_offset: 0 - bit_size: 2 - enum: PLLSRC - - name: DIVM - description: Prescaler for PLL1 - bit_offset: 4 - bit_size: 6 - array: - len: 3 - stride: 8 -fieldset/RSR: - description: RCC Reset Status Register - fields: - - name: RMVF - description: Remove reset flag - bit_offset: 16 - bit_size: 1 - enum: RSR_RMVF - - name: CPURSTF - description: CPU reset flag - bit_offset: 17 - bit_size: 1 - enum_read: RSR_CPURSTFR - - name: D1RSTF - description: D1 domain power switch reset flag - bit_offset: 19 - bit_size: 1 - enum_read: RSR_CPURSTFR - - name: D2RSTF - description: D2 domain power switch reset flag - bit_offset: 20 - bit_size: 1 - enum_read: RSR_CPURSTFR - - name: BORRSTF - description: BOR reset flag - bit_offset: 21 - bit_size: 1 - enum_read: RSR_CPURSTFR - - name: PINRSTF - description: Pin reset flag (NRST) - bit_offset: 22 - bit_size: 1 - enum_read: RSR_CPURSTFR - - name: PORRSTF - description: POR/PDR reset flag - bit_offset: 23 - bit_size: 1 - enum_read: RSR_CPURSTFR - - name: SFTRSTF - description: System reset from CPU reset flag - bit_offset: 24 - bit_size: 1 - enum_read: RSR_CPURSTFR - - name: IWDG1RSTF - description: Independent Watchdog reset flag - bit_offset: 26 - bit_size: 1 - enum_read: RSR_CPURSTFR - - name: WWDG1RSTF - description: Window Watchdog reset flag - bit_offset: 28 - bit_size: 1 - enum_read: RSR_CPURSTFR - - name: LPWRRSTF - description: Reset due to illegal D1 DStandby or CPU CStop flag - bit_offset: 30 - bit_size: 1 - enum_read: RSR_CPURSTFR -enum/ADCSEL: - bit_size: 2 - variants: - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 0 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 1 - - name: PER - description: PER selected as peripheral clock - value: 2 -enum/C1_RSR_CPURSTFR: - bit_size: 1 - variants: - - name: NoResetOccoured - description: No reset occoured for block - value: 0 - - name: ResetOccourred - description: Reset occoured for block - value: 1 -enum/C1_RSR_RMVF: - bit_size: 1 - variants: - - name: NotActive - description: Not clearing the the reset flags - value: 0 - - name: Clear - description: Clear the reset flags - value: 1 -enum/CECSEL: - bit_size: 2 - variants: - - name: LSE - description: LSE selected as peripheral clock - value: 0 - - name: LSI - description: LSI selected as peripheral clock - value: 1 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 2 -enum/CKPERSEL: - bit_size: 2 - variants: - - name: HSI - description: HSI selected as peripheral clock - value: 0 - - name: CSI - description: CSI selected as peripheral clock - value: 1 - - name: HSE - description: HSE selected as peripheral clock - value: 2 -enum/D1PPRE: - bit_size: 3 - variants: - - name: Div1 - description: rcc_hclk not divided - value: 0 - - name: Div2 - description: rcc_hclk divided by 2 - value: 4 - - name: Div4 - description: rcc_hclk divided by 4 - value: 5 - - name: Div8 - description: rcc_hclk divided by 8 - value: 6 - - name: Div16 - description: rcc_hclk divided by 16 - value: 7 -enum/D2PPRE1: - bit_size: 3 - variants: - - name: Div1 - description: rcc_hclk not divided - value: 0 - - name: Div2 - description: rcc_hclk divided by 2 - value: 4 - - name: Div4 - description: rcc_hclk divided by 4 - value: 5 - - name: Div8 - description: rcc_hclk divided by 8 - value: 6 - - name: Div16 - description: rcc_hclk divided by 16 - value: 7 -enum/D3PPRE: - bit_size: 3 - variants: - - name: Div1 - description: rcc_hclk not divided - value: 0 - - name: Div2 - description: rcc_hclk divided by 2 - value: 4 - - name: Div4 - description: rcc_hclk divided by 4 - value: 5 - - name: Div8 - description: rcc_hclk divided by 8 - value: 6 - - name: Div16 - description: rcc_hclk divided by 16 - value: 7 -enum/DFSDM1SEL: - bit_size: 1 - variants: - - name: RCC_PCLK2 - description: rcc_pclk2 selected as peripheral clock - value: 0 - - name: SYS - description: System clock selected as peripheral clock - value: 1 -enum/DIVP1: - bit_size: 7 - variants: - - name: Div1 - description: pll_p_ck = vco_ck - value: 0 - - name: Div2 - description: pll_p_ck = vco_ck / 2 - value: 1 - - name: Div4 - description: pll_p_ck = vco_ck / 4 - value: 3 - - name: Div6 - description: pll_p_ck = vco_ck / 6 - value: 5 - - name: Div8 - description: pll_p_ck = vco_ck / 8 - value: 7 - - name: Div10 - description: pll_p_ck = vco_ck / 10 - value: 9 - - name: Div12 - description: pll_p_ck = vco_ck / 12 - value: 11 - - name: Div14 - description: pll_p_ck = vco_ck / 14 - value: 13 - - name: Div16 - description: pll_p_ck = vco_ck / 16 - value: 15 - - name: Div18 - description: pll_p_ck = vco_ck / 18 - value: 17 - - name: Div20 - description: pll_p_ck = vco_ck / 20 - value: 19 - - name: Div22 - description: pll_p_ck = vco_ck / 22 - value: 21 - - name: Div24 - description: pll_p_ck = vco_ck / 24 - value: 23 - - name: Div26 - description: pll_p_ck = vco_ck / 26 - value: 25 - - name: Div28 - description: pll_p_ck = vco_ck / 28 - value: 27 - - name: Div30 - description: pll_p_ck = vco_ck / 30 - value: 29 - - name: Div32 - description: pll_p_ck = vco_ck / 32 - value: 31 - - name: Div34 - description: pll_p_ck = vco_ck / 34 - value: 33 - - name: Div36 - description: pll_p_ck = vco_ck / 36 - value: 35 - - name: Div38 - description: pll_p_ck = vco_ck / 38 - value: 37 - - name: Div40 - description: pll_p_ck = vco_ck / 40 - value: 39 - - name: Div42 - description: pll_p_ck = vco_ck / 42 - value: 41 - - name: Div44 - description: pll_p_ck = vco_ck / 44 - value: 43 - - name: Div46 - description: pll_p_ck = vco_ck / 46 - value: 45 - - name: Div48 - description: pll_p_ck = vco_ck / 48 - value: 47 - - name: Div50 - description: pll_p_ck = vco_ck / 50 - value: 49 - - name: Div52 - description: pll_p_ck = vco_ck / 52 - value: 51 - - name: Div54 - description: pll_p_ck = vco_ck / 54 - value: 53 - - name: Div56 - description: pll_p_ck = vco_ck / 56 - value: 55 - - name: Div58 - description: pll_p_ck = vco_ck / 58 - value: 57 - - name: Div60 - description: pll_p_ck = vco_ck / 60 - value: 59 - - name: Div62 - description: pll_p_ck = vco_ck / 62 - value: 61 - - name: Div64 - description: pll_p_ck = vco_ck / 64 - value: 63 - - name: Div66 - description: pll_p_ck = vco_ck / 66 - value: 65 - - name: Div68 - description: pll_p_ck = vco_ck / 68 - value: 67 - - name: Div70 - description: pll_p_ck = vco_ck / 70 - value: 69 - - name: Div72 - description: pll_p_ck = vco_ck / 72 - value: 71 - - name: Div74 - description: pll_p_ck = vco_ck / 74 - value: 73 - - name: Div76 - description: pll_p_ck = vco_ck / 76 - value: 75 - - name: Div78 - description: pll_p_ck = vco_ck / 78 - value: 77 - - name: Div80 - description: pll_p_ck = vco_ck / 80 - value: 79 - - name: Div82 - description: pll_p_ck = vco_ck / 82 - value: 81 - - name: Div84 - description: pll_p_ck = vco_ck / 84 - value: 83 - - name: Div86 - description: pll_p_ck = vco_ck / 86 - value: 85 - - name: Div88 - description: pll_p_ck = vco_ck / 88 - value: 87 - - name: Div90 - description: pll_p_ck = vco_ck / 90 - value: 89 - - name: Div92 - description: pll_p_ck = vco_ck / 92 - value: 91 - - name: Div94 - description: pll_p_ck = vco_ck / 94 - value: 93 - - name: Div96 - description: pll_p_ck = vco_ck / 96 - value: 95 - - name: Div98 - description: pll_p_ck = vco_ck / 98 - value: 97 - - name: Div100 - description: pll_p_ck = vco_ck / 100 - value: 99 - - name: Div102 - description: pll_p_ck = vco_ck / 102 - value: 101 - - name: Div104 - description: pll_p_ck = vco_ck / 104 - value: 103 - - name: Div106 - description: pll_p_ck = vco_ck / 106 - value: 105 - - name: Div108 - description: pll_p_ck = vco_ck / 108 - value: 107 - - name: Div110 - description: pll_p_ck = vco_ck / 110 - value: 109 - - name: Div112 - description: pll_p_ck = vco_ck / 112 - value: 111 - - name: Div114 - description: pll_p_ck = vco_ck / 114 - value: 113 - - name: Div116 - description: pll_p_ck = vco_ck / 116 - value: 115 - - name: Div118 - description: pll_p_ck = vco_ck / 118 - value: 117 - - name: Div120 - description: pll_p_ck = vco_ck / 120 - value: 119 - - name: Div122 - description: pll_p_ck = vco_ck / 122 - value: 121 - - name: Div124 - description: pll_p_ck = vco_ck / 124 - value: 123 - - name: Div126 - description: pll_p_ck = vco_ck / 126 - value: 125 - - name: Div128 - description: pll_p_ck = vco_ck / 128 - value: 127 -enum/FDCANSEL: - bit_size: 2 - variants: - - name: HSE - description: HSE selected as peripheral clock - value: 0 - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 1 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 2 -enum/FMCSEL: - bit_size: 2 - variants: - - name: RCC_HCLK3 - description: rcc_hclk3 selected as peripheral clock - value: 0 - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 1 - - name: PLL2_R - description: pll2_r selected as peripheral clock - value: 2 - - name: PER - description: PER selected as peripheral clock - value: 3 -enum/HPRE: - bit_size: 4 - variants: - - name: Div1 - description: sys_ck not divided - value: 0 - - name: Div2 - description: sys_ck divided by 2 - value: 8 - - name: Div4 - description: sys_ck divided by 4 - value: 9 - - name: Div8 - description: sys_ck divided by 8 - value: 10 - - name: Div16 - description: sys_ck divided by 16 - value: 11 - - name: Div64 - description: sys_ck divided by 64 - value: 12 - - name: Div128 - description: sys_ck divided by 128 - value: 13 - - name: Div256 - description: sys_ck divided by 256 - value: 14 - - name: Div512 - description: sys_ck divided by 512 - value: 15 -enum/HRTIMSEL: - bit_size: 1 - variants: - - name: TIMY_KER - description: The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck) - value: 0 - - name: C_CK - description: The HRTIM prescaler clock source is the CPU clock (c_ck) - value: 1 -enum/HSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: HSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: HSE crystal oscillator bypassed with external clock - value: 1 -enum/HSIDIV: - bit_size: 2 - variants: - - name: Div1 - description: No division - value: 0 - - name: Div2 - description: Division by 2 - value: 1 - - name: Div4 - description: Division by 4 - value: 2 - - name: Div8 - description: Division by 8 - value: 3 -enum/HSIDIVFR: - bit_size: 1 - variants: - - name: NotPropagated - description: New HSIDIV ratio has not yet propagated to hsi_ck - value: 0 - - name: Propagated - description: HSIDIV ratio has propagated to hsi_ck - value: 1 -enum/HSION: - bit_size: 1 - variants: - - name: "Off" - description: Clock Off - value: 0 - - name: "On" - description: Clock On - value: 1 -enum/HSIRDYR: - bit_size: 1 - variants: - - name: NotReady - description: Clock not ready - value: 0 - - name: Ready - description: Clock ready - value: 1 -enum/I2C123SEL: - bit_size: 2 - variants: - - name: RCC_PCLK1 - description: rcc_pclk1 selected as peripheral clock - value: 0 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 1 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 2 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 3 -enum/I2C4SEL: - bit_size: 2 - variants: - - name: RCC_PCLK4 - description: rcc_pclk4 selected as peripheral clock - value: 0 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 1 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 2 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 3 -enum/LPTIM1SEL: - bit_size: 3 - variants: - - name: RCC_PCLK1 - description: rcc_pclk1 selected as peripheral clock - value: 0 - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 1 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 2 - - name: LSE - description: LSE selected as peripheral clock - value: 3 - - name: LSI - description: LSI selected as peripheral clock - value: 4 - - name: PER - description: PER selected as peripheral clock - value: 5 -enum/LPTIM2SEL: - bit_size: 3 - variants: - - name: RCC_PCLK4 - description: rcc_pclk4 selected as peripheral clock - value: 0 - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 1 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 2 - - name: LSE - description: LSE selected as peripheral clock - value: 3 - - name: LSI - description: LSI selected as peripheral clock - value: 4 - - name: PER - description: PER selected as peripheral clock - value: 5 -enum/LPUART1SEL: - bit_size: 3 - variants: - - name: RCC_PCLK_D3 - description: rcc_pclk_d3 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: LSE - description: LSE selected as peripheral clock - value: 5 -enum/LSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: LSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: LSE crystal oscillator bypassed with external clock - value: 1 -enum/LSECSSDR: - bit_size: 1 - variants: - - name: NoFailure - description: No failure detected on 32 kHz oscillator - value: 0 - - name: Failure - description: Failure detected on 32 kHz oscillator - value: 1 -enum/LSECSSON: - bit_size: 1 - variants: - - name: SecurityOff - description: Clock security system on 32 kHz oscillator off - value: 0 - - name: SecurityOn - description: Clock security system on 32 kHz oscillator on - value: 1 -enum/LSEDRV: - bit_size: 2 - variants: - - name: Lowest - description: Lowest LSE oscillator driving capability - value: 0 - - name: MediumLow - description: Medium low LSE oscillator driving capability - value: 1 - - name: MediumHigh - description: Medium high LSE oscillator driving capability - value: 2 - - name: Highest - description: Highest LSE oscillator driving capability - value: 3 -enum/LSEON: - bit_size: 1 - variants: - - name: "Off" - description: LSE oscillator Off - value: 0 - - name: "On" - description: LSE oscillator On - value: 1 -enum/LSERDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSE oscillator not ready - value: 0 - - name: Ready - description: LSE oscillator ready - value: 1 -enum/LSION: - bit_size: 1 - variants: - - name: "Off" - description: LSI oscillator Off - value: 0 - - name: "On" - description: LSI oscillator On - value: 1 -enum/LSIRDYC: - bit_size: 1 - variants: - - name: Clear - description: Clear interrupt flag - value: 1 -enum/LSIRDYIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt disabled - value: 0 - - name: Enabled - description: Interrupt enabled - value: 1 -enum/LSIRDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSI oscillator not ready - value: 0 - - name: Ready - description: LSI oscillator ready - value: 1 -enum/MCO1: - bit_size: 3 - variants: - - name: HSI - description: HSI selected for micro-controller clock output - value: 0 - - name: LSE - description: LSE selected for micro-controller clock output - value: 1 - - name: HSE - description: HSE selected for micro-controller clock output - value: 2 - - name: PLL1_Q - description: pll1_q selected for micro-controller clock output - value: 3 - - name: HSI48 - description: HSI48 selected for micro-controller clock output - value: 4 -enum/MCO2: - bit_size: 3 - variants: - - name: SYSCLK - description: System clock selected for micro-controller clock output - value: 0 - - name: PLL2_P - description: pll2_p selected for micro-controller clock output - value: 1 - - name: HSE - description: HSE selected for micro-controller clock output - value: 2 - - name: PLL1_P - description: pll1_p selected for micro-controller clock output - value: 3 - - name: CSI - description: CSI selected for micro-controller clock output - value: 4 - - name: LSI - description: LSI selected for micro-controller clock output - value: 5 -enum/PLL1RGE: - bit_size: 2 - variants: - - name: Range1 - description: Frequency is between 1 and 2 MHz - value: 0 - - name: Range2 - description: Frequency is between 2 and 4 MHz - value: 1 - - name: Range4 - description: Frequency is between 4 and 8 MHz - value: 2 - - name: Range8 - description: Frequency is between 8 and 16 MHz - value: 3 -enum/PLL1VCOSEL: - bit_size: 1 - variants: - - name: WideVCO - description: VCO frequency range 192 to 836 MHz - value: 0 - - name: MediumVCO - description: VCO frequency range 150 to 420 MHz - value: 1 -enum/PLLSRC: - bit_size: 2 - variants: - - name: HSI - description: HSI selected as PLL clock - value: 0 - - name: CSI - description: CSI selected as PLL clock - value: 1 - - name: HSE - description: HSE selected as PLL clock - value: 2 - - name: None - description: No clock sent to DIVMx dividers and PLLs - value: 3 -enum/RNGSEL: - bit_size: 2 - variants: - - name: HSI48 - description: HSI48 selected as peripheral clock - value: 0 - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 1 - - name: LSE - description: LSE selected as peripheral clock - value: 2 - - name: LSI - description: LSI selected as peripheral clock - value: 3 -enum/RSR_CPURSTFR: - bit_size: 1 - variants: - - name: NoResetOccoured - description: No reset occoured for block - value: 0 - - name: ResetOccourred - description: Reset occoured for block - value: 1 -enum/RSR_RMVF: - bit_size: 1 - variants: - - name: NotActive - description: Not clearing the the reset flags - value: 0 - - name: Clear - description: Clear the reset flags - value: 1 -enum/RTCSEL: - bit_size: 2 - variants: - - name: NoClock - description: No clock - value: 0 - - name: LSE - description: LSE oscillator clock used as RTC clock - value: 1 - - name: LSI - description: LSI oscillator clock used as RTC clock - value: 2 - - name: HSE - description: HSE oscillator clock divided by a prescaler used as RTC clock - value: 3 -enum/SAI1SEL: - bit_size: 3 - variants: - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 0 - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 1 - - name: PLL3_P - description: pll3_p selected as peripheral clock - value: 2 - - name: I2S_CKIN - description: I2S_CKIN selected as peripheral clock - value: 3 - - name: PER - description: PER selected as peripheral clock - value: 4 -enum/SAI4ASEL: - bit_size: 3 - variants: - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 0 - - name: PLL2_P - description: pll2_p selected as peripheral clock - value: 1 - - name: PLL3_P - description: pll3_p selected as peripheral clock - value: 2 - - name: I2S_CKIN - description: i2s_ckin selected as peripheral clock - value: 3 - - name: PER - description: PER selected as peripheral clock - value: 4 -enum/SDMMCSEL: - bit_size: 1 - variants: - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 0 - - name: PLL2_R - description: pll2_r selected as peripheral clock - value: 1 -enum/SPDIFSEL: - bit_size: 2 - variants: - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 0 - - name: PLL2_R - description: pll2_r selected as peripheral clock - value: 1 - - name: PLL3_R - description: pll3_r selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 -enum/SPI45SEL: - bit_size: 3 - variants: - - name: APB - description: APB clock selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: HSE - description: HSE selected as peripheral clock - value: 5 -enum/SPI6SEL: - bit_size: 3 - variants: - - name: RCC_PCLK4 - description: rcc_pclk4 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: HSE - description: HSE selected as peripheral clock - value: 5 -enum/STOPWUCK: - bit_size: 1 - variants: - - name: HSI - description: HSI selected as wake up clock from system Stop - value: 0 - - name: CSI - description: CSI selected as wake up clock from system Stop - value: 1 -enum/SW: - bit_size: 3 - variants: - - name: HSI - description: HSI selected as system clock - value: 0 - - name: CSI - description: CSI selected as system clock - value: 1 - - name: HSE - description: HSE selected as system clock - value: 2 - - name: PLL1 - description: PLL1 selected as system clock - value: 3 -enum/SWPSEL: - bit_size: 1 - variants: - - name: PCLK - description: pclk selected as peripheral clock - value: 0 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 1 -enum/SWSR: - bit_size: 3 - variants: - - name: HSI - description: HSI oscillator used as system clock - value: 0 - - name: CSI - description: CSI oscillator used as system clock - value: 1 - - name: HSE - description: HSE oscillator used as system clock - value: 2 - - name: PLL1 - description: PLL1 used as system clock - value: 3 -enum/TIMPRE: - bit_size: 1 - variants: - - name: DefaultX2 - description: Timer kernel clock equal to 2x pclk by default - value: 0 - - name: DefaultX4 - description: Timer kernel clock equal to 4x pclk by default - value: 1 -enum/USART16SEL: - bit_size: 3 - variants: - - name: RCC_PCLK2 - description: rcc_pclk2 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: LSE - description: LSE selected as peripheral clock - value: 5 -enum/USART234578SEL: - bit_size: 3 - variants: - - name: RCC_PCLK1 - description: rcc_pclk1 selected as peripheral clock - value: 0 - - name: PLL2_Q - description: pll2_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI_KER - description: hsi_ker selected as peripheral clock - value: 3 - - name: CSI_KER - description: csi_ker selected as peripheral clock - value: 4 - - name: LSE - description: LSE selected as peripheral clock - value: 5 -enum/USBSEL: - bit_size: 2 - variants: - - name: DISABLE - description: Disable the kernel clock - value: 0 - - name: PLL1_Q - description: pll1_q selected as peripheral clock - value: 1 - - name: PLL3_Q - description: pll3_q selected as peripheral clock - value: 2 - - name: HSI48 - description: HSI48 selected as peripheral clock - value: 3 -enum/WW1RSC: - bit_size: 1 - variants: - - name: Clear - description: Clear WWDG1 scope control - value: 0 - - name: Set - description: Set WWDG1 scope control - value: 1 + - bit_offset: 0 + bit_size: 2 + description: DIVMx and PLLs clock source selection + enum: PLLSRC + name: PLLSRC + - array: + len: 3 + stride: 8 + bit_offset: 4 + bit_size: 6 + description: Prescaler for PLL1 + name: DIVM diff --git a/merge_regs.py b/merge_regs.py new file mode 100644 index 0000000..fc9381a --- /dev/null +++ b/merge_regs.py @@ -0,0 +1,67 @@ +import xmltodict +import yaml +import re +import json +import sys +import os +from collections import OrderedDict +from glob import glob + +def item_key(a): + return int(a["byte_offset"]) + +def field_key(a): + return int(a["bit_offset"]) + +def block_items(origin, new): + newarr=[] + sorted(origin, key=item_key) + sorted(new, key=item_key) + + for val in origin: + for newval in new: + if val["name"] == newval["name"] and val["byte_offset"] == newval["byte_offset"] and val["fieldset"] == newval["fieldset"]: + newarr.append(newval) + + return newarr + +def reg_fields(origin, new): + newarr=[] + sorted(origin, key=field_key) + sorted(new, key=field_key) + for val in origin: + for newval in new: + if val["name"] == newval["name"] and val["bit_offset"] == newval["bit_offset"]: + newarr.append(newval) + return newarr + +def merge_dicts(origin, new): + merged={} + for k, v in origin.items(): + if k in new: + if type(v) is dict: + merged[k] = merge_dicts(v, new[k]) + elif type(v) is list: + if k == "items": + merged[k] = block_items(v, new[k]) + if k == "fields": + merged[k] = reg_fields(v, new[k]) + else: + merged[k] = v + return merged + + +first=True +reg_map={} +for regfile in sys.argv[1:]: + print("Loading", regfile) + with open(regfile, 'r') as f: + y = yaml.load(f, Loader=yaml.SafeLoader) + if not reg_map: + reg_map = y + else: + reg_map = merge_dicts(reg_map, y) + + +with open('regs_merged.yaml', 'w') as f: + f.write(yaml.dump(reg_map))