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rcc/h7: add missing stuff, cleanup.

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This commit is contained in:
Dario Nieuwenhuis 2022-02-24 05:54:43 +01:00
parent b6bccb1456
commit 324e5bee8d
2 changed files with 498 additions and 233 deletions
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50
data/registers/rcc_h7.yaml
View File

@ -131,7 +131,7 @@ block/RCC:
byte_offset: 156 byte_offset: 156
fieldset: APB4RSTR fieldset: APB4RSTR
- name: GCR - name: GCR
description: RCC Global Control Register description: Global Control Register
byte_offset: 160 byte_offset: 160
fieldset: GCR fieldset: GCR
- name: D3AMR - name: D3AMR
@ -776,7 +776,7 @@ fieldset/AHB4ENR:
description: HSEM peripheral clock enable description: HSEM peripheral clock enable
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: BKPRAMEN - name: BKPSRAMEN
description: Backup RAM Clock Enable description: Backup RAM Clock Enable
bit_offset: 28 bit_offset: 28
bit_size: 1 bit_size: 1
@ -839,7 +839,7 @@ fieldset/AHB4LPENR:
description: ADC3 Peripheral Clocks Enable During CSleep Mode description: ADC3 Peripheral Clocks Enable During CSleep Mode
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: BKPRAMLPEN - name: BKPSRAMLPEN
description: Backup RAM Clock Enable During CSleep Mode description: Backup RAM Clock Enable During CSleep Mode
bit_offset: 28 bit_offset: 28
bit_size: 1 bit_size: 1
@ -1601,6 +1601,10 @@ fieldset/APB4ENR:
description: LPTIM5 Peripheral Clocks Enable description: LPTIM5 Peripheral Clocks Enable
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: DAC2EN
description: DAC2 (containing one converter) peripheral clock enable
bit_offset: 13
bit_size: 1
- name: COMP12EN - name: COMP12EN
description: COMP1/2 peripheral clock enable description: COMP1/2 peripheral clock enable
bit_offset: 14 bit_offset: 14
@ -1656,6 +1660,10 @@ fieldset/APB4LPENR:
description: LPTIM5 Peripheral Clocks Enable During CSleep Mode description: LPTIM5 Peripheral Clocks Enable During CSleep Mode
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: DAC2LPEN
description: DAC2 (containing one converter) peripheral clock enable during CSleep mode
bit_offset: 13
bit_size: 1
- name: COMP12LPEN - name: COMP12LPEN
description: COMP1/2 peripheral clock enable during CSleep mode description: COMP1/2 peripheral clock enable during CSleep mode
bit_offset: 14 bit_offset: 14
@ -1711,6 +1719,10 @@ fieldset/APB4RSTR:
description: LPTIM5 block reset description: LPTIM5 block reset
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: DAC2RST
description: DAC2 (containing one converter) reset
bit_offset: 13
bit_size: 1
- name: COMP12RST - name: COMP12RST
description: COMP12 Blocks Reset description: COMP12 Blocks Reset
bit_offset: 14 bit_offset: 14
@ -2093,7 +2105,7 @@ fieldset/C1_AHB4ENR:
description: HSEM peripheral clock enable description: HSEM peripheral clock enable
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: BKPRAMEN - name: BKPSRAMEN
description: Backup RAM Clock Enable description: Backup RAM Clock Enable
bit_offset: 28 bit_offset: 28
bit_size: 1 bit_size: 1
@ -2156,7 +2168,7 @@ fieldset/C1_AHB4LPENR:
description: ADC3 Peripheral Clocks Enable During CSleep Mode description: ADC3 Peripheral Clocks Enable During CSleep Mode
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: BKPRAMLPEN - name: BKPSRAMLPEN
description: Backup RAM Clock Enable During CSleep Mode description: Backup RAM Clock Enable During CSleep Mode
bit_offset: 28 bit_offset: 28
bit_size: 1 bit_size: 1
@ -3105,11 +3117,11 @@ fieldset/D2CCIP1R:
bit_offset: 16 bit_offset: 16
bit_size: 3 bit_size: 3
enum: SPI45SEL enum: SPI45SEL
- name: SPDIFSEL - name: SPDIFRXSEL
description: SPDIFRX kernel clock source selection description: SPDIFRX kernel clock source selection
bit_offset: 20 bit_offset: 20
bit_size: 2 bit_size: 2
enum: SPDIFSEL enum: SPDIFRXSEL
- name: DFSDM1SEL - name: DFSDM1SEL
description: DFSDM1 kernel Clk clock source selection description: DFSDM1 kernel Clk clock source selection
bit_offset: 24 bit_offset: 24
@ -3134,7 +3146,7 @@ fieldset/D2CCIP2R:
bit_size: 3 bit_size: 3
enum: USART234578SEL enum: USART234578SEL
- name: USART16910SEL - name: USART16910SEL
description: USART1 and 6 kernel clock source selection description: "USART1, 6, 9 and 10 kernel clock source selection"
bit_offset: 3 bit_offset: 3
bit_size: 3 bit_size: 3
enum: USART16910SEL enum: USART16910SEL
@ -3211,6 +3223,10 @@ fieldset/D3AMR:
description: LPTIM5 Autonomous mode enable description: LPTIM5 Autonomous mode enable
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
- name: DAC2AMEN
description: DAC2 (containing one converter) Autonomous mode enable
bit_offset: 13
bit_size: 1
- name: COMP12AMEN - name: COMP12AMEN
description: COMP12 Autonomous mode enable description: COMP12 Autonomous mode enable
bit_offset: 14 bit_offset: 14
@ -3285,6 +3301,10 @@ fieldset/D3CCIPR:
bit_offset: 24 bit_offset: 24
bit_size: 3 bit_size: 3
enum: SAIASEL enum: SAIASEL
- name: DFSDM2SEL
description: DFSDM2 kernel clock source selection
bit_offset: 27
bit_size: 1
- name: SPI6SEL - name: SPI6SEL
description: SPI6 kernel clock source selection description: SPI6 kernel clock source selection
bit_offset: 28 bit_offset: 28
@ -3299,7 +3319,7 @@ fieldset/D3CFGR:
bit_size: 3 bit_size: 3
enum: DPPRE enum: DPPRE
fieldset/GCR: fieldset/GCR:
description: RCC Global Control Register description: Global Control Register
fields: fields:
- name: WW1RSC - name: WW1RSC
description: WWDG1 reset scope control description: WWDG1 reset scope control
@ -3495,7 +3515,6 @@ fieldset/RSR:
description: Remove reset flag description: Remove reset flag
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum: RSR_RMVF
- name: CPURSTF - name: CPURSTF
description: CPU reset flag description: CPU reset flag
bit_offset: 17 bit_offset: 17
@ -4079,15 +4098,6 @@ enum/RNGSEL:
- name: LSI - name: LSI
description: LSI selected as peripheral clock description: LSI selected as peripheral clock
value: 3 value: 3
enum/RSR_RMVF:
bit_size: 1
variants:
- name: NotActive
description: Not clearing the the reset flags
value: 0
- name: Clear
description: Clear the reset flags
value: 1
enum/RTCSEL: enum/RTCSEL:
bit_size: 2 bit_size: 2
variants: variants:
@ -4148,7 +4158,7 @@ enum/SDMMCSEL:
- name: PLL2_R - name: PLL2_R
description: pll2_r selected as peripheral clock description: pll2_r selected as peripheral clock
value: 1 value: 1
enum/SPDIFSEL: enum/SPDIFRXSEL:
bit_size: 2 bit_size: 2
variants: variants:
- name: PLL1_Q - name: PLL1_Q

681
data/registers/rcc_h7ab.yaml
View File

@ -57,22 +57,22 @@ block/RCC:
stride: 8 stride: 8
byte_offset: 52 byte_offset: 52
fieldset: PLL1FRACR fieldset: PLL1FRACR
- name: CDCCIPR - name: D1CCIPR
description: RCC Domain 1 Kernel Clock Configuration Register description: RCC Domain 1 Kernel Clock Configuration Register
byte_offset: 76 byte_offset: 76
fieldset: CDCCIPR fieldset: D1CCIPR
- name: CDCCIP1R - name: D2CCIP1R
description: RCC Domain 2 Kernel Clock Configuration Register description: RCC Domain 2 Kernel Clock Configuration Register
byte_offset: 80 byte_offset: 80
fieldset: CDCCIP1R fieldset: D2CCIP1R
- name: CDCCIP2R - name: D2CCIP2R
description: RCC Domain 2 Kernel Clock Configuration Register description: RCC Domain 2 Kernel Clock Configuration Register
byte_offset: 84 byte_offset: 84
fieldset: CDCCIP2R fieldset: D2CCIP2R
- name: SRDCCIPR - name: D3CCIPR
description: RCC Domain 3 Kernel Clock Configuration Register description: RCC Domain 3 Kernel Clock Configuration Register
byte_offset: 88 byte_offset: 88
fieldset: SRDCCIPR fieldset: D3CCIPR
- name: CIER - name: CIER
description: RCC Clock Source Interrupt Enable Register description: RCC Clock Source Interrupt Enable Register
byte_offset: 96 byte_offset: 96
@ -138,10 +138,10 @@ block/RCC:
description: RCC D3 Autonomous mode Register description: RCC D3 Autonomous mode Register
byte_offset: 168 byte_offset: 168
fieldset: D3AMR fieldset: D3AMR
- name: C1_RSR - name: RSR
description: RCC Reset Status Register description: RCC Reset Status Register
byte_offset: 304 byte_offset: 304
fieldset: C1_RSR fieldset: RSR
- name: AHB3ENR - name: AHB3ENR
description: RCC AHB3 Clock Register description: RCC AHB3 Clock Register
byte_offset: 308 byte_offset: 308
@ -229,6 +229,10 @@ fieldset/AHB1ENR:
description: ADC1/2 Peripheral Clocks Enable description: ADC1/2 Peripheral Clocks Enable
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: ARTEN
description: ART Clock Enable
bit_offset: 14
bit_size: 1
- name: ETH1MACEN - name: ETH1MACEN
description: Ethernet MAC bus interface Clock Enable description: Ethernet MAC bus interface Clock Enable
bit_offset: 15 bit_offset: 15
@ -241,6 +245,10 @@ fieldset/AHB1ENR:
description: Ethernet Reception Clock Enable description: Ethernet Reception Clock Enable
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
- name: USB2OTGHSULPIEN
description: " Enable USB_PHY2 clocks "
bit_offset: 18
bit_size: 1
- name: USB1OTGEN - name: USB1OTGEN
description: USB1OTG Peripheral Clocks Enable description: USB1OTG Peripheral Clocks Enable
bit_offset: 25 bit_offset: 25
@ -249,6 +257,14 @@ fieldset/AHB1ENR:
description: USB_PHY1 Clocks Enable description: USB_PHY1 Clocks Enable
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
- name: USB2OTGEN
description: USB2OTG Peripheral Clocks Enable
bit_offset: 27
bit_size: 1
- name: USB2ULPIEN
description: USB_PHY2 Clocks Enable
bit_offset: 28
bit_size: 1
fieldset/AHB1LPENR: fieldset/AHB1LPENR:
description: RCC AHB1 Sleep Clock Register description: RCC AHB1 Sleep Clock Register
fields: fields:
@ -264,6 +280,10 @@ fieldset/AHB1LPENR:
description: ADC1/2 Peripheral Clocks Enable During CSleep Mode description: ADC1/2 Peripheral Clocks Enable During CSleep Mode
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: ARTLPEN
description: ART Clock Enable During CSleep Mode
bit_offset: 14
bit_size: 1
- name: ETH1MACLPEN - name: ETH1MACLPEN
description: Ethernet MAC bus interface Clock Enable During CSleep Mode description: Ethernet MAC bus interface Clock Enable During CSleep Mode
bit_offset: 15 bit_offset: 15
@ -280,10 +300,26 @@ fieldset/AHB1LPENR:
description: USB1OTG peripheral clock enable during CSleep mode description: USB1OTG peripheral clock enable during CSleep mode
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
- name: USB1OTGHSULPILPEN
description: USB_PHY1 clock enable during CSleep mode
bit_offset: 26
bit_size: 1
- name: USB1ULPILPEN - name: USB1ULPILPEN
description: USB_PHY1 clock enable during CSleep mode description: USB_PHY1 clock enable during CSleep mode
bit_offset: 26 bit_offset: 26
bit_size: 1 bit_size: 1
- name: USB2OTGLPEN
description: USB2OTG peripheral clock enable during CSleep mode
bit_offset: 27
bit_size: 1
- name: USB2OTGHSULPILPEN
description: USB_PHY2 clocks enable during CSleep mode
bit_offset: 28
bit_size: 1
- name: USB2ULPILPEN
description: USB_PHY2 clocks enable during CSleep mode
bit_offset: 28
bit_size: 1
fieldset/AHB1RSTR: fieldset/AHB1RSTR:
description: RCC AHB1 Peripheral Reset Register description: RCC AHB1 Peripheral Reset Register
fields: fields:
@ -299,6 +335,10 @@ fieldset/AHB1RSTR:
description: ADC1&2 block reset description: ADC1&2 block reset
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: ARTRST
description: ART block reset
bit_offset: 14
bit_size: 1
- name: ETH1MACRST - name: ETH1MACRST
description: ETH1MAC block reset description: ETH1MAC block reset
bit_offset: 15 bit_offset: 15
@ -334,6 +374,18 @@ fieldset/AHB2ENR:
description: SDMMC2 and SDMMC2 delay clock enable description: SDMMC2 and SDMMC2 delay clock enable
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: BDMA1EN
description: BDMA1 clock enable
bit_offset: 11
bit_size: 1
- name: FMACEN
description: FMAC enable
bit_offset: 16
bit_size: 1
- name: CORDICEN
description: CORDIC enable
bit_offset: 17
bit_size: 1
- name: SRAM1EN - name: SRAM1EN
description: SRAM1 block enable description: SRAM1 block enable
bit_offset: 29 bit_offset: 29
@ -369,6 +421,18 @@ fieldset/AHB2LPENR:
description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: BDMA1LPEN
description: BDMA1 Clock Enable During CSleep Mode
bit_offset: 11
bit_size: 1
- name: FMACLPEN
description: FMAC enable during CSleep Mode
bit_offset: 16
bit_size: 1
- name: CORDICLPEN
description: CORDIC enable during CSleep Mode
bit_offset: 17
bit_size: 1
- name: SRAM1LPEN - name: SRAM1LPEN
description: SRAM1 Clock Enable During CSleep Mode description: SRAM1 Clock Enable During CSleep Mode
bit_offset: 29 bit_offset: 29
@ -384,8 +448,8 @@ fieldset/AHB2LPENR:
fieldset/AHB2RSTR: fieldset/AHB2RSTR:
description: RCC AHB2 Peripheral Reset Register description: RCC AHB2 Peripheral Reset Register
fields: fields:
- name: CAMITFRST - name: DCMIRST
description: CAMITF block reset description: DCMI block reset
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: CRYPTRST - name: CRYPTRST
@ -404,6 +468,18 @@ fieldset/AHB2RSTR:
description: SDMMC2 and SDMMC2 Delay block reset description: SDMMC2 and SDMMC2 Delay block reset
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: BDMA1RST
description: BDMA1 block reset
bit_offset: 11
bit_size: 1
- name: FMACRST
description: FMAC reset
bit_offset: 16
bit_size: 1
- name: CORDICRST
description: CORDIC reset
bit_offset: 17
bit_size: 1
fieldset/AHB3ENR: fieldset/AHB3ENR:
description: RCC AHB3 Clock Register description: RCC AHB3 Clock Register
fields: fields:
@ -431,6 +507,22 @@ fieldset/AHB3ENR:
description: SDMMC1 and SDMMC1 Delay Clock Enable description: SDMMC1 and SDMMC1 Delay Clock Enable
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: OCTOSPI2EN
description: OCTOSPI2 and OCTOSPI2 delay block enable
bit_offset: 19
bit_size: 1
- name: IOMNGREN
description: OCTOSPI IO manager enable
bit_offset: 21
bit_size: 1
- name: OTFD1EN
description: OTFDEC1 enable
bit_offset: 22
bit_size: 1
- name: OTFD2EN
description: OTFDEC2 enable
bit_offset: 23
bit_size: 1
- name: DTCM1EN - name: DTCM1EN
description: D1 DTCM1 block enable description: D1 DTCM1 block enable
bit_offset: 28 bit_offset: 28
@ -462,8 +554,8 @@ fieldset/AHB3LPENR:
description: JPGDEC Clock Enable During CSleep Mode description: JPGDEC Clock Enable During CSleep Mode
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: FLASHPREN - name: FLASHLPEN
description: Flash interface clock enable during csleep mode description: FLASH Clock Enable During CSleep Mode
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: FMCLPEN - name: FMCLPEN
@ -478,6 +570,22 @@ fieldset/AHB3LPENR:
description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: OCTOSPI2LPEN
description: OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode
bit_offset: 19
bit_size: 1
- name: IOMNGRLPEN
description: OCTOSPI IO manager enable during CSleep Mode
bit_offset: 21
bit_size: 1
- name: OTFD1LPEN
description: OTFDEC1 enable during CSleep Mode
bit_offset: 22
bit_size: 1
- name: OTFD2LPEN
description: OTFDEC2 enable during CSleep Mode
bit_offset: 23
bit_size: 1
- name: D1DTCM1LPEN - name: D1DTCM1LPEN
description: D1DTCM1 Block Clock Enable During CSleep mode description: D1DTCM1 Block Clock Enable During CSleep mode
bit_offset: 28 bit_offset: 28
@ -521,6 +629,22 @@ fieldset/AHB3RSTR:
description: SDMMC1 and SDMMC1 delay block reset description: SDMMC1 and SDMMC1 delay block reset
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
- name: OCTOSPI2RST
description: OCTOSPI2 and OCTOSPI2 delay block reset
bit_offset: 19
bit_size: 1
- name: IOMNGRRST
description: OCTOSPI IO manager reset
bit_offset: 21
bit_size: 1
- name: OTFD1RST
description: OTFDEC1 reset
bit_offset: 22
bit_size: 1
- name: OTFD2RST
description: OTFDEC2 reset
bit_offset: 23
bit_size: 1
- name: CPURST - name: CPURST
description: CPU reset description: CPU reset
bit_offset: 31 bit_offset: 31
@ -580,6 +704,10 @@ fieldset/AHB4ENR:
description: BDMA and DMAMUX2 Clock Enable description: BDMA and DMAMUX2 Clock Enable
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: BDMA2EN
description: BDMA2 and DMAMUX2 Clock Enable
bit_offset: 21
bit_size: 1
- name: ADC3EN - name: ADC3EN
description: ADC3 Peripheral Clocks Enable description: ADC3 Peripheral Clocks Enable
bit_offset: 24 bit_offset: 24
@ -647,6 +775,10 @@ fieldset/AHB4LPENR:
description: BDMA Clock Enable During CSleep Mode description: BDMA Clock Enable During CSleep Mode
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: BDMA2LPEN
description: BDMA2 Clock Enable During CSleep Mode
bit_offset: 21
bit_size: 1
- name: ADC3LPEN - name: ADC3LPEN
description: ADC3 Peripheral Clocks Enable During CSleep Mode description: ADC3 Peripheral Clocks Enable During CSleep Mode
bit_offset: 24 bit_offset: 24
@ -714,6 +846,10 @@ fieldset/AHB4RSTR:
description: BDMA block reset description: BDMA block reset
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: BDMA2RST
description: BDMA2 block reset
bit_offset: 21
bit_size: 1
- name: ADC3RST - name: ADC3RST
description: ADC3 block reset description: ADC3 block reset
bit_offset: 24 bit_offset: 24
@ -745,6 +881,14 @@ fieldset/APB1HENR:
description: FDCAN Peripheral Clocks Enable description: FDCAN Peripheral Clocks Enable
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: TIM23EN
description: TIM23 block enable
bit_offset: 24
bit_size: 1
- name: TIM24EN
description: TIM24 block enable
bit_offset: 25
bit_size: 1
fieldset/APB1HLPENR: fieldset/APB1HLPENR:
description: RCC APB1 High Sleep Clock Register description: RCC APB1 High Sleep Clock Register
fields: fields:
@ -768,6 +912,14 @@ fieldset/APB1HLPENR:
description: FDCAN Peripheral Clocks Enable During CSleep Mode description: FDCAN Peripheral Clocks Enable During CSleep Mode
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: TIM23LPEN
description: TIM23 block enable during CSleep Mode
bit_offset: 24
bit_size: 1
- name: TIM24LPEN
description: TIM24 block enable during CSleep Mode
bit_offset: 25
bit_size: 1
fieldset/APB1HRSTR: fieldset/APB1HRSTR:
description: RCC APB1 Peripheral Reset Register description: RCC APB1 Peripheral Reset Register
fields: fields:
@ -791,6 +943,14 @@ fieldset/APB1HRSTR:
description: FDCAN block reset description: FDCAN block reset
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
- name: TIM23RST
description: TIM23 block reset
bit_offset: 24
bit_size: 1
- name: TIM24RST
description: TIM24 block reset
bit_offset: 25
bit_size: 1
fieldset/APB1LENR: fieldset/APB1LENR:
description: RCC APB1 Clock Register description: RCC APB1 Clock Register
fields: fields:
@ -834,6 +994,10 @@ fieldset/APB1LENR:
description: LPTIM1 Peripheral Clocks Enable description: LPTIM1 Peripheral Clocks Enable
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: WWDG2EN
description: WWDG2 peripheral clock enable
bit_offset: 11
bit_size: 1
- name: SPI2EN - name: SPI2EN
description: SPI2 Peripheral Clocks Enable description: SPI2 Peripheral Clocks Enable
bit_offset: 14 bit_offset: 14
@ -874,6 +1038,10 @@ fieldset/APB1LENR:
description: I2C3 Peripheral Clocks Enable description: I2C3 Peripheral Clocks Enable
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: I2C5EN
description: "I2C5 Peripheral Clocks\r Enable"
bit_offset: 25
bit_size: 1
- name: CECEN - name: CECEN
description: HDMI-CEC peripheral clock enable description: HDMI-CEC peripheral clock enable
bit_offset: 27 bit_offset: 27
@ -933,6 +1101,10 @@ fieldset/APB1LLPENR:
description: LPTIM1 Peripheral Clocks Enable During CSleep Mode description: LPTIM1 Peripheral Clocks Enable During CSleep Mode
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
- name: WWDG2LPEN
description: WWDG2 peripheral Clocks Enable During CSleep Mode
bit_offset: 11
bit_size: 1
- name: SPI2LPEN - name: SPI2LPEN
description: SPI2 Peripheral Clocks Enable During CSleep Mode description: SPI2 Peripheral Clocks Enable During CSleep Mode
bit_offset: 14 bit_offset: 14
@ -973,6 +1145,10 @@ fieldset/APB1LLPENR:
description: I2C3 Peripheral Clocks Enable During CSleep Mode description: I2C3 Peripheral Clocks Enable During CSleep Mode
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: I2C5LPEN
description: I2C5 block enable during CSleep Mode
bit_offset: 25
bit_size: 1
- name: CECLPEN - name: CECLPEN
description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode
bit_offset: 27 bit_offset: 27
@ -1072,6 +1248,10 @@ fieldset/APB1LRSTR:
description: I2C3 block reset description: I2C3 block reset
bit_offset: 23 bit_offset: 23
bit_size: 1 bit_size: 1
- name: I2C5RST
description: I2C5 block reset
bit_offset: 25
bit_size: 1
- name: CECRST - name: CECRST
description: HDMI-CEC block reset description: HDMI-CEC block reset
bit_offset: 27 bit_offset: 27
@ -1107,6 +1287,14 @@ fieldset/APB2ENR:
description: USART6 Peripheral Clocks Enable description: USART6 Peripheral Clocks Enable
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: UART9EN
description: "UART9 Peripheral Clocks\r Enable"
bit_offset: 6
bit_size: 1
- name: USART10EN
description: "USART10 Peripheral Clocks\r Enable"
bit_offset: 7
bit_size: 1
- name: SPI1EN - name: SPI1EN
description: SPI1 Peripheral Clocks Enable description: SPI1 Peripheral Clocks Enable
bit_offset: 12 bit_offset: 12
@ -1233,6 +1421,14 @@ fieldset/APB2RSTR:
description: USART6 block reset description: USART6 block reset
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
- name: UART9RST
description: UART9 block reset
bit_offset: 6
bit_size: 1
- name: USART10RST
description: USART10 block reset
bit_offset: 7
bit_size: 1
- name: SPI1RST - name: SPI1RST
description: SPI1 block reset description: SPI1 block reset
bit_offset: 12 bit_offset: 12
@ -1284,6 +1480,10 @@ fieldset/APB3ENR:
description: LTDC peripheral clock enable description: LTDC peripheral clock enable
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: DSIEN
description: DSI Peripheral clocks enable
bit_offset: 4
bit_size: 1
- name: WWDG1EN - name: WWDG1EN
description: WWDG1 Clock Enable description: WWDG1 Clock Enable
bit_offset: 6 bit_offset: 6
@ -1295,6 +1495,10 @@ fieldset/APB3LPENR:
description: LTDC peripheral clock enable during CSleep mode description: LTDC peripheral clock enable during CSleep mode
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: DSILPEN
description: DSI Peripheral Clock Enable During CSleep Mode
bit_offset: 4
bit_size: 1
- name: WWDG1LPEN - name: WWDG1LPEN
description: WWDG1 Clock Enable During CSleep Mode description: WWDG1 Clock Enable During CSleep Mode
bit_offset: 6 bit_offset: 6
@ -1306,6 +1510,10 @@ fieldset/APB3RSTR:
description: LTDC block reset description: LTDC block reset
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
- name: DSIRST
description: DSI block reset
bit_offset: 4
bit_size: 1
fieldset/APB4ENR: fieldset/APB4ENR:
description: RCC APB4 Clock Register description: RCC APB4 Clock Register
fields: fields:
@ -1333,6 +1541,14 @@ fieldset/APB4ENR:
description: LPTIM3 Peripheral Clocks Enable description: LPTIM3 Peripheral Clocks Enable
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: LPTIM4EN
description: LPTIM4 Peripheral Clocks Enable
bit_offset: 11
bit_size: 1
- name: LPTIM5EN
description: LPTIM5 Peripheral Clocks Enable
bit_offset: 12
bit_size: 1
- name: DAC2EN - name: DAC2EN
description: DAC2 (containing one converter) peripheral clock enable description: DAC2 (containing one converter) peripheral clock enable
bit_offset: 13 bit_offset: 13
@ -1353,6 +1569,10 @@ fieldset/APB4ENR:
description: SAI4 Peripheral Clocks Enable description: SAI4 Peripheral Clocks Enable
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: DTSEN
description: Digital temperature sensor block enable
bit_offset: 26
bit_size: 1
fieldset/APB4LPENR: fieldset/APB4LPENR:
description: RCC APB4 Sleep Clock Register description: RCC APB4 Sleep Clock Register
fields: fields:
@ -1380,6 +1600,14 @@ fieldset/APB4LPENR:
description: LPTIM3 Peripheral Clocks Enable During CSleep Mode description: LPTIM3 Peripheral Clocks Enable During CSleep Mode
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: LPTIM4LPEN
description: LPTIM4 Peripheral Clocks Enable During CSleep Mode
bit_offset: 11
bit_size: 1
- name: LPTIM5LPEN
description: LPTIM5 Peripheral Clocks Enable During CSleep Mode
bit_offset: 12
bit_size: 1
- name: DAC2LPEN - name: DAC2LPEN
description: DAC2 (containing one converter) peripheral clock enable during CSleep mode description: DAC2 (containing one converter) peripheral clock enable during CSleep mode
bit_offset: 13 bit_offset: 13
@ -1400,6 +1628,10 @@ fieldset/APB4LPENR:
description: SAI4 Peripheral Clocks Enable During CSleep Mode description: SAI4 Peripheral Clocks Enable During CSleep Mode
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: DTSLPEN
description: Digital temperature sensor block enable during CSleep Mode
bit_offset: 26
bit_size: 1
fieldset/APB4RSTR: fieldset/APB4RSTR:
description: RCC APB4 Peripheral Reset Register description: RCC APB4 Peripheral Reset Register
fields: fields:
@ -1427,6 +1659,14 @@ fieldset/APB4RSTR:
description: LPTIM3 block reset description: LPTIM3 block reset
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: LPTIM4RST
description: LPTIM4 block reset
bit_offset: 11
bit_size: 1
- name: LPTIM5RST
description: LPTIM5 block reset
bit_offset: 12
bit_size: 1
- name: DAC2RST - name: DAC2RST
description: DAC2 (containing one converter) reset description: DAC2 (containing one converter) reset
bit_offset: 13 bit_offset: 13
@ -1443,6 +1683,10 @@ fieldset/APB4RSTR:
description: SAI4 block reset description: SAI4 block reset
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
- name: DTSRST
description: Digital temperature sensor block reset
bit_offset: 26
bit_size: 1
fieldset/BDCR: fieldset/BDCR:
description: RCC Backup Domain Control Register description: RCC Backup Domain Control Register
fields: fields:
@ -1484,163 +1728,6 @@ fieldset/BDCR:
description: VSwitch domain software reset description: VSwitch domain software reset
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
fieldset/C1_RSR:
description: RCC Reset Status Register
fields:
- name: RMVF
description: Remove reset flag
bit_offset: 16
bit_size: 1
enum: RMVF
- name: CPURSTF
description: CPU reset flag
bit_offset: 17
bit_size: 1
- name: D1RSTF
description: D1 domain power switch reset flag
bit_offset: 19
bit_size: 1
- name: D2RSTF
description: D2 domain power switch reset flag
bit_offset: 20
bit_size: 1
- name: BORRSTF
description: BOR reset flag
bit_offset: 21
bit_size: 1
- name: PINRSTF
description: Pin reset flag (NRST)
bit_offset: 22
bit_size: 1
- name: PORRSTF
description: POR/PDR reset flag
bit_offset: 23
bit_size: 1
- name: SFTRSTF
description: System reset from CPU reset flag
bit_offset: 24
bit_size: 1
- name: IWDG1RSTF
description: Independent Watchdog reset flag
bit_offset: 26
bit_size: 1
- name: WWDG1RSTF
description: Window Watchdog reset flag
bit_offset: 28
bit_size: 1
- name: LPWRRSTF
description: Reset due to illegal D1 DStandby or CPU CStop flag
bit_offset: 30
bit_size: 1
fieldset/CDCCIP1R:
description: RCC Domain 2 Kernel Clock Configuration Register
fields:
- name: SAI1SEL
description: SAI1 and DFSDM1 kernel Aclk clock source selection
bit_offset: 0
bit_size: 3
enum: SAISEL
- name: SAI2ASEL
description: SAI2 kernel clock source A source selection
bit_offset: 6
bit_size: 3
enum: SAIASEL
- name: SAI2BSEL
description: SAI2 kernel clock source B source selection
bit_offset: 9
bit_size: 3
enum: SAIASEL
- name: SPI123SEL
description: "SPI/I2S1,2 and 3 kernel clock source selection"
bit_offset: 12
bit_size: 3
enum: SAISEL
- name: SPI45SEL
description: SPI4 and 5 kernel clock source selection
bit_offset: 16
bit_size: 3
enum: SPI45SEL
- name: SPDIFRXSEL
description: SPDIFRX kernel clock source selection
bit_offset: 20
bit_size: 2
enum: SPDIFRXSEL
- name: DFSDM1SEL
description: DFSDM1 kernel Clk clock source selection
bit_offset: 24
bit_size: 1
enum: DFSDMSEL
- name: FDCANSEL
description: FDCAN kernel clock source selection
bit_offset: 28
bit_size: 2
enum: FDCANSEL
- name: SWPSEL
description: SWPMI kernel clock source selection
bit_offset: 31
bit_size: 1
enum: SWPSEL
fieldset/CDCCIP2R:
description: RCC Domain 2 Kernel Clock Configuration Register
fields:
- name: USART234578SEL
description: "USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection"
bit_offset: 0
bit_size: 3
enum: USART234578SEL
- name: USART16910SEL
description: "USART1, 6, 9 and 10 kernel clock source selection"
bit_offset: 3
bit_size: 3
enum: USART16910SEL
- name: RNGSEL
description: RNG kernel clock source selection
bit_offset: 8
bit_size: 2
enum: RNGSEL
- name: I2C123SEL
description: "I2C1,2,3 kernel clock source selection"
bit_offset: 12
bit_size: 2
enum: I2C123SEL
- name: USBSEL
description: USBOTG 1 and 2 kernel clock source selection
bit_offset: 20
bit_size: 2
enum: USBSEL
- name: CECSEL
description: HDMI-CEC kernel clock source selection
bit_offset: 22
bit_size: 2
enum: CECSEL
- name: LPTIM1SEL
description: LPTIM1 kernel clock source selection
bit_offset: 28
bit_size: 3
enum: LPTIM1SEL
fieldset/CDCCIPR:
description: RCC Domain 1 Kernel Clock Configuration Register
fields:
- name: FMCSEL
description: FMC kernel clock source selection
bit_offset: 0
bit_size: 2
enum: FMCSEL
- name: OCTOSPISEL
description: OCTOSPI kernel clock source selection
bit_offset: 4
bit_size: 2
enum: FMCSEL
- name: SDMMCSEL
description: SDMMC kernel clock source selection
bit_offset: 16
bit_size: 1
enum: SDMMCSEL
- name: CKPERSEL
description: per_ck clock source selection
bit_offset: 28
bit_size: 2
enum: CKPERSEL
fieldset/CFGR: fieldset/CFGR:
description: RCC Clock Configuration Register description: RCC Clock Configuration Register
fields: fields:
@ -1929,6 +2016,33 @@ fieldset/CSR:
description: LSI oscillator ready description: LSI oscillator ready
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
fieldset/D1CCIPR:
description: RCC Domain 1 Kernel Clock Configuration Register
fields:
- name: FMCSEL
description: FMC kernel clock source selection
bit_offset: 0
bit_size: 2
enum: FMCSEL
- name: OCTOSPISEL
description: OCTOSPI kernel clock source selection
bit_offset: 4
bit_size: 2
enum: FMCSEL
- name: DSISEL
description: kernel clock source selection
bit_offset: 8
bit_size: 1
- name: SDMMCSEL
description: SDMMC kernel clock source selection
bit_offset: 16
bit_size: 1
enum: SDMMCSEL
- name: CKPERSEL
description: per_ck clock source selection
bit_offset: 28
bit_size: 2
enum: CKPERSEL
fieldset/D1CFGR: fieldset/D1CFGR:
description: RCC Domain 1 Clock Configuration Register description: RCC Domain 1 Clock Configuration Register
fields: fields:
@ -1947,6 +2061,92 @@ fieldset/D1CFGR:
bit_offset: 8 bit_offset: 8
bit_size: 4 bit_size: 4
enum: HPRE enum: HPRE
fieldset/D2CCIP1R:
description: RCC Domain 2 Kernel Clock Configuration Register
fields:
- name: SAI1SEL
description: SAI1 and DFSDM1 kernel Aclk clock source selection
bit_offset: 0
bit_size: 3
enum: SAISEL
- name: SAI2ASEL
description: SAI2 kernel clock source A source selection
bit_offset: 6
bit_size: 3
enum: SAIASEL
- name: SAI2BSEL
description: SAI2 kernel clock source B source selection
bit_offset: 9
bit_size: 3
enum: SAIASEL
- name: SPI123SEL
description: "SPI/I2S1,2 and 3 kernel clock source selection"
bit_offset: 12
bit_size: 3
enum: SAISEL
- name: SPI45SEL
description: SPI4 and 5 kernel clock source selection
bit_offset: 16
bit_size: 3
enum: SPI45SEL
- name: SPDIFRXSEL
description: SPDIFRX kernel clock source selection
bit_offset: 20
bit_size: 2
enum: SPDIFRXSEL
- name: DFSDM1SEL
description: DFSDM1 kernel Clk clock source selection
bit_offset: 24
bit_size: 1
enum: DFSDMSEL
- name: FDCANSEL
description: FDCAN kernel clock source selection
bit_offset: 28
bit_size: 2
enum: FDCANSEL
- name: SWPSEL
description: SWPMI kernel clock source selection
bit_offset: 31
bit_size: 1
enum: SWPSEL
fieldset/D2CCIP2R:
description: RCC Domain 2 Kernel Clock Configuration Register
fields:
- name: USART234578SEL
description: "USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection"
bit_offset: 0
bit_size: 3
enum: USART234578SEL
- name: USART16910SEL
description: "USART1, 6, 9 and 10 kernel clock source selection"
bit_offset: 3
bit_size: 3
enum: USART16910SEL
- name: RNGSEL
description: RNG kernel clock source selection
bit_offset: 8
bit_size: 2
enum: RNGSEL
- name: I2C1235SEL
description: "I2C1,2,3 kernel clock source selection"
bit_offset: 12
bit_size: 2
enum: I2C1235SEL
- name: USBSEL
description: USBOTG 1 and 2 kernel clock source selection
bit_offset: 20
bit_size: 2
enum: USBSEL
- name: CECSEL
description: HDMI-CEC kernel clock source selection
bit_offset: 22
bit_size: 2
enum: CECSEL
- name: LPTIM1SEL
description: LPTIM1 kernel clock source selection
bit_offset: 28
bit_size: 3
enum: LPTIM1SEL
fieldset/D2CFGR: fieldset/D2CFGR:
description: RCC Domain 2 Clock Configuration Register description: RCC Domain 2 Clock Configuration Register
fields: fields:
@ -1967,6 +2167,10 @@ fieldset/D3AMR:
description: BDMA and DMAMUX Autonomous mode enable description: BDMA and DMAMUX Autonomous mode enable
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: BDMA2AMEN
description: BDMA2 and DMAMUX Autonomous mode enable
bit_offset: 0
bit_size: 1
- name: LPUART1AMEN - name: LPUART1AMEN
description: LPUART1 Autonomous mode enable description: LPUART1 Autonomous mode enable
bit_offset: 3 bit_offset: 3
@ -1987,6 +2191,14 @@ fieldset/D3AMR:
description: LPTIM3 Autonomous mode enable description: LPTIM3 Autonomous mode enable
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
- name: LPTIM4AMEN
description: LPTIM4 Autonomous mode enable
bit_offset: 11
bit_size: 1
- name: LPTIM5AMEN
description: LPTIM5 Autonomous mode enable
bit_offset: 12
bit_size: 1
- name: DAC2AMEN - name: DAC2AMEN
description: DAC2 (containing one converter) Autonomous mode enable description: DAC2 (containing one converter) Autonomous mode enable
bit_offset: 13 bit_offset: 13
@ -2015,6 +2227,10 @@ fieldset/D3AMR:
description: ADC3 Autonomous mode enable description: ADC3 Autonomous mode enable
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: DTSAMEN
description: Digital temperature sensor Autonomous mode enable
bit_offset: 26
bit_size: 1
- name: BKPSRAMAMEN - name: BKPSRAMAMEN
description: Backup RAM Autonomous mode enable description: Backup RAM Autonomous mode enable
bit_offset: 28 bit_offset: 28
@ -2023,6 +2239,43 @@ fieldset/D3AMR:
description: SRAM4 Autonomous mode enable description: SRAM4 Autonomous mode enable
bit_offset: 29 bit_offset: 29
bit_size: 1 bit_size: 1
fieldset/D3CCIPR:
description: RCC Domain 3 Kernel Clock Configuration Register
fields:
- name: LPUART1SEL
description: LPUART1 kernel clock source selection
bit_offset: 0
bit_size: 3
enum: LPUARTSEL
- name: I2C4SEL
description: I2C4 kernel clock source selection
bit_offset: 8
bit_size: 2
enum: I2C4SEL
- name: LPTIM2SEL
description: LPTIM2 kernel clock source selection
bit_offset: 10
bit_size: 3
enum: LPTIM2SEL
- name: LPTIM345SEL
description: "LPTIM3,4,5 kernel clock source selection"
bit_offset: 13
bit_size: 3
enum: LPTIM2SEL
- name: ADCSEL
description: SAR ADC kernel clock source selection
bit_offset: 16
bit_size: 2
enum: ADCSEL
- name: DFSDM2SEL
description: DFSDM2 kernel clock source selection
bit_offset: 27
bit_size: 1
- name: SPI6SEL
description: SPI6 kernel clock source selection
bit_offset: 28
bit_size: 3
enum: SPI6SEL
fieldset/D3CFGR: fieldset/D3CFGR:
description: RCC Domain 3 Clock Configuration Register description: RCC Domain 3 Clock Configuration Register
fields: fields:
@ -2190,42 +2443,53 @@ fieldset/PLLCKSELR:
array: array:
len: 3 len: 3
stride: 8 stride: 8
fieldset/SRDCCIPR: fieldset/RSR:
description: RCC Domain 3 Kernel Clock Configuration Register description: RCC Reset Status Register
fields: fields:
- name: LPUART1SEL - name: RMVF
description: LPUART1 kernel clock source selection description: Remove reset flag
bit_offset: 0
bit_size: 3
enum: LPUARTSEL
- name: I2C4SEL
description: I2C4 kernel clock source selection
bit_offset: 8
bit_size: 2
enum: I2C4SEL
- name: LPTIM2SEL
description: LPTIM2 kernel clock source selection
bit_offset: 10
bit_size: 3
enum: LPTIM2SEL
- name: LPTIM3SEL
description: "LPTIM3,4,5 kernel clock source selection"
bit_offset: 13
bit_size: 3
- name: ADCSEL
description: SAR ADC kernel clock source selection
bit_offset: 16 bit_offset: 16
bit_size: 2
enum: ADCSEL
- name: DFSDM2SEL
description: DFSDM2 kernel clock source selection
bit_offset: 27
bit_size: 1 bit_size: 1
- name: SPI6SEL - name: CPURSTF
description: SPI6 kernel clock source selection description: CPU reset flag
bit_offset: 17
bit_size: 1
- name: D1RSTF
description: D1 domain power switch reset flag
bit_offset: 19
bit_size: 1
- name: D2RSTF
description: D2 domain power switch reset flag
bit_offset: 20
bit_size: 1
- name: BORRSTF
description: BOR reset flag
bit_offset: 21
bit_size: 1
- name: PINRSTF
description: Pin reset flag (NRST)
bit_offset: 22
bit_size: 1
- name: PORRSTF
description: POR/PDR reset flag
bit_offset: 23
bit_size: 1
- name: SFTRSTF
description: System reset from CPU reset flag
bit_offset: 24
bit_size: 1
- name: IWDG1RSTF
description: Independent Watchdog reset flag
bit_offset: 26
bit_size: 1
- name: WWDG1RSTF
description: Window Watchdog reset flag
bit_offset: 28 bit_offset: 28
bit_size: 3 bit_size: 1
enum: SPI6SEL - name: LPWRRSTF
description: Reset due to illegal D1 DStandby or CPU CStop flag
bit_offset: 30
bit_size: 1
enum/ADCSEL: enum/ADCSEL:
bit_size: 2 bit_size: 2
variants: variants:
@ -2568,7 +2832,7 @@ enum/HSIDIV:
- name: Div8 - name: Div8
description: Division by 8 description: Division by 8
value: 3 value: 3
enum/I2C123SEL: enum/I2C1235SEL:
bit_size: 2 bit_size: 2
variants: variants:
- name: RCC_PCLK1 - name: RCC_PCLK1
@ -2754,15 +3018,6 @@ enum/PLLVCOSEL:
- name: MediumVCO - name: MediumVCO
description: VCO frequency range 150 to 420 MHz description: VCO frequency range 150 to 420 MHz
value: 1 value: 1
enum/RMVF:
bit_size: 1
variants:
- name: NotActive
description: Not clearing the the reset flags
value: 0
- name: Clear
description: Clear the reset flags
value: 1
enum/RNGSEL: enum/RNGSEL:
bit_size: 2 bit_size: 2
variants: variants: