diff --git a/data/registers/lptim_g0.yaml b/data/registers/lptim_g0.yaml new file mode 100644 index 0000000..403b419 --- /dev/null +++ b/data/registers/lptim_g0.yaml @@ -0,0 +1,292 @@ +--- +block/LPTIM: + description: Low power timer + items: + - name: ISR + description: Interrupt and Status Register + byte_offset: 0 + access: Read + fieldset: ISR + - name: ICR + description: Interrupt Clear Register + byte_offset: 4 + access: Write + fieldset: ICR + - name: IER + description: Interrupt Enable Register + byte_offset: 8 + fieldset: IER + - name: CFGR + description: Configuration Register + byte_offset: 12 + fieldset: CFGR + - name: CR + description: Control Register + byte_offset: 16 + fieldset: CR + - name: CMP + description: Compare Register + byte_offset: 20 + fieldset: CMP + - name: ARR + description: Autoreload Register + byte_offset: 24 + fieldset: ARR + - name: CNT + description: Counter Register + byte_offset: 28 + access: Read + fieldset: CNT + - name: CFGR2 + description: LPTIM configuration register 2 + byte_offset: 36 + fieldset: CFGR2 +fieldset/ARR: + description: Autoreload Register + fields: + - name: ARR + description: Auto reload value + bit_offset: 0 + bit_size: 16 +fieldset/CFGR: + description: Configuration Register + fields: + - name: CKSEL + description: Clock selector + bit_offset: 0 + bit_size: 1 + enum: CKSEL + - name: CKPOL + description: Clock Polarity + bit_offset: 1 + bit_size: 2 + - name: CKFLT + description: Configurable digital filter for external clock + bit_offset: 3 + bit_size: 2 + - name: TRGFLT + description: Configurable digital filter for trigger + bit_offset: 6 + bit_size: 2 + - name: PRESC + description: Clock prescaler + bit_offset: 9 + bit_size: 3 + enum: PRESC + - name: TRIGSEL + description: Trigger selector + bit_offset: 13 + bit_size: 3 + - name: TRIGEN + description: Trigger enable and polarity + bit_offset: 17 + bit_size: 2 + enum: TRIGEN + - name: TIMOUT + description: Timeout enable + bit_offset: 19 + bit_size: 1 + - name: WAVE + description: Waveform shape + bit_offset: 20 + bit_size: 1 + - name: WAVPOL + description: Waveform shape polarity + bit_offset: 21 + bit_size: 1 + - name: PRELOAD + description: Registers update mode + bit_offset: 22 + bit_size: 1 + - name: COUNTMODE + description: counter mode enabled + bit_offset: 23 + bit_size: 1 + - name: ENC + description: Encoder mode enable + bit_offset: 24 + bit_size: 1 +fieldset/CFGR2: + description: LPTIM configuration register 2 + fields: + - name: IN1SEL + description: LPTIMx Input 1 selection + bit_offset: 0 + bit_size: 2 + - name: IN2SEL + description: LPTIM1 Input 2 selection + bit_offset: 4 + bit_size: 2 +fieldset/CMP: + description: Compare Register + fields: + - name: CMP + description: Compare value + bit_offset: 0 + bit_size: 16 +fieldset/CNT: + description: Counter Register + fields: + - name: CNT + description: Counter value + bit_offset: 0 + bit_size: 16 +fieldset/CR: + description: Control Register + fields: + - name: ENABLE + description: LPTIM Enable + bit_offset: 0 + bit_size: 1 + - name: SNGSTRT + description: LPTIM start in single mode + bit_offset: 1 + bit_size: 1 + - name: CNTSTRT + description: Timer start in continuous mode + bit_offset: 2 + bit_size: 1 + - name: COUNTRST + description: Counter reset + bit_offset: 3 + bit_size: 1 + - name: RSTARE + description: Reset after read enable + bit_offset: 4 + bit_size: 1 +fieldset/ICR: + description: Interrupt Clear Register + fields: + - name: CMPMCF + description: compare match Clear Flag + bit_offset: 0 + bit_size: 1 + - name: ARRMCF + description: Autoreload match Clear Flag + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge Clear Flag + bit_offset: 2 + bit_size: 1 + - name: CMPOKCF + description: Compare register update OK Clear Flag + bit_offset: 3 + bit_size: 1 + - name: ARROKCF + description: Autoreload register update OK Clear Flag + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: Direction change to UP Clear Flag + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: Direction change to down Clear Flag + bit_offset: 6 + bit_size: 1 +fieldset/IER: + description: Interrupt Enable Register + fields: + - name: CMPMIE + description: Compare match Interrupt Enable + bit_offset: 0 + bit_size: 1 + - name: ARRMIE + description: Autoreload match Interrupt Enable + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable + bit_offset: 2 + bit_size: 1 + - name: CMPOKIE + description: Compare register update OK Interrupt Enable + bit_offset: 3 + bit_size: 1 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: Direction change to UP Interrupt Enable + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: Direction change to down Interrupt Enable + bit_offset: 6 + bit_size: 1 +fieldset/ISR: + description: Interrupt and Status Register + fields: + - name: CMPM + description: Compare match + bit_offset: 0 + bit_size: 1 + - name: ARRM + description: Autoreload match + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: External trigger edge event + bit_offset: 2 + bit_size: 1 + - name: CMPOK + description: Compare register update OK + bit_offset: 3 + bit_size: 1 + - name: ARROK + description: Autoreload register update OK + bit_offset: 4 + bit_size: 1 + - name: UP + description: Counter direction change down to up + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: Counter direction change up to down + bit_offset: 6 + bit_size: 1 +enum/CKSEL: + bit_size: 1 + variants: + - name: INTERNAL + description: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) + value: 0 + - name: EXTERNAL + description: LPTIM is clocked by an external clock source through the LPTIM external Input1 + value: 1 +enum/PRESC: + bit_size: 3 + variants: + - name: DIV_BY_1 + value: 0x0 + - name: DIV_BY_2 + value: 0x1 + - name: DIV_BY_4 + value: 0x2 + - name: DIV_BY_8 + value: 0x3 + - name: DIV_BY_16 + value: 0x4 + - name: DIV_BY_32 + value: 0x5 + - name: DIV_BY_64 + value: 0x6 + - name: DIV_BY_128 + value: 0x7 +enum/TRIGEN: + bit_size: 2 + variants: + - name: SOFTWARE + description: software trigger (counting start is initiated by software) + value: 0x0 + - name: RISING + description: rising edge is the active edge + value: 0x1 + - name: FALLING + description: rising edge is the active edge + value: 0x2 + - name: BOTH + description: both edges are active edges + value: 0x3 diff --git a/parse.py b/parse.py index 3d208d9..be70234 100755 --- a/parse.py +++ b/parse.py @@ -424,6 +424,8 @@ perimap = [ ('STM32F7.*:ETH:ETH:ethermac110_v2_0', 'eth_v1c/ETH'), ('.*ETH:ethermac110_v3_0', 'eth_v2/ETH'), + ('.*LPTIM\d.*:G0xx_lptimer1_v1_4', 'lptim_g0/LPTIM'), + ('STM32F7.*:TIM1:.*', 'timer_v1/TIM_ADV'), ('STM32F7.*:TIM8:.*', 'timer_v1/TIM_ADV'), ('.*TIM\d.*:gptimer.*', 'timer_v1/TIM_GP16'),