Parse our memory location bases and name them well-ish.
This commit is contained in:
Bob McWhirter
parent
2d38aad861
commit
2e7af6b842
168
parse.py
168
parse.py
@ -3,6 +3,7 @@
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import sys
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import xmltodict
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import yaml
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try:
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from yaml import CSafeLoader as SafeLoader
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except ImportError:
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@ -14,6 +15,24 @@ import os
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from collections import OrderedDict
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from glob import glob
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class DecimalInt:
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def __init__(self, val):
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self.val = val
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def represent_decimal_int(dumper, data):
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return dumper.represent_int(data.val)
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yaml.add_representer(DecimalInt, represent_decimal_int)
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class HexInt:
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def __init__(self, val):
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self.val = val
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def represent_hex_int(dumper, data):
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return dumper.represent_int(hex(data.val))
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yaml.add_representer(HexInt, represent_hex_int)
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def removeprefix(value: str, prefix: str, /) -> str:
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if value.startswith(prefix):
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@ -52,6 +71,7 @@ def represent_ordereddict(dumper, data):
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yaml.add_representer(OrderedDict, represent_ordereddict)
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def hexint_presenter(dumper, data):
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if data > 0x10000:
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return dumper.represent_int(hex(data))
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@ -112,6 +132,7 @@ def paren_ok(val):
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return False
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return n == 0
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# warning: horrible abomination ahead
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@ -167,21 +188,21 @@ def parse_header(f):
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cur_core = "cm" + str(m.group(1))
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if m.group(2) != None:
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cur_core += "p"
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#print("Cur core is ", cur_core, "matched", l)
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# print("Cur core is ", cur_core, "matched", l)
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found = False
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for core in cores:
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if core == cur_core:
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found = True
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if not found:
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cores.append(cur_core)
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#print("Switching to core", cur_core, "for", f)
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# print("Switching to core", cur_core, "for", f)
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elif m := re.match('.*else.*', l):
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cur_core = "all"
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if m := re.match('.*else.*CORE_CM(\\d+)(PLUS)?.*', l):
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cur_core = "cm" + str(m.group(1))
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if m.group(2) != None:
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cur_core += "p"
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#print("Cur core is ", cur_core, "matched", l)
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# print("Cur core is ", cur_core, "matched", l)
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elif len(cores) > 1:
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# Pick the second core assuming we've already parsed one
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cur_core = cores[1]
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@ -192,19 +213,19 @@ def parse_header(f):
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found = True
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if not found:
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cores.append(cur_core)
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#print("Switching to core", cur_core, "for", f)
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# print("Switching to core", cur_core, "for", f)
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elif m := re.match('.*endif.*', l):
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#print("Switching to common core for", f)
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# print("Switching to common core for", f)
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cur_core = "all"
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if cur_core not in irqs:
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#print("Registering new core", cur_core)
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# print("Registering new core", cur_core)
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irqs[cur_core] = {}
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if cur_core not in defines:
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defines[cur_core] = {}
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if m := re.match('([a-zA-Z0-9_]+)_IRQn += (\\d+),? +/\\*!< (.*) \\*/', l):
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#print("Found irq for", cur_core)
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# print("Found irq for", cur_core)
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irqs[cur_core][m.group(1)] = int(m.group(2))
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if m := re.match('#define +([0-9A-Za-z_]+)\\(', l):
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@ -217,11 +238,11 @@ def parse_header(f):
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continue
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val = val.split('/*')[0].strip()
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val = parse_value(val, defines[cur_core])
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#print("Found define for", cur_core)
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# print("Found define for", cur_core)
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defines[cur_core][name] = val
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#print("Found", len(cores), "cores for", f)
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#print("Found", len(irqs['all']), "shared interrupts for", f)
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# print("Found", len(cores), "cores for", f)
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# print("Found", len(irqs['all']), "shared interrupts for", f)
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if len(cores) == 0:
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cores.append("all")
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@ -369,7 +390,7 @@ perimap = [
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def match_peri(peri):
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for r, block in perimap:
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if re.match('^'+r+'$', peri):
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if re.match('^' + r + '$', peri):
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if block == '':
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return None
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return block
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@ -462,11 +483,28 @@ def chip_name_from_package_name(x):
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]
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for a, b in name_map:
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r, n = re.subn('^'+a+'$', b, x)
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r, n = re.subn('^' + a + '$', b, x)
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if n != 0:
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return r
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raise Exception("bad name: {}".format(x))
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memories_map = {
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'flash': [
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'FLASH', 'FLASH_BANK1', 'FLASH_BANK2',
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'D1_AXIFLASH', 'D1_AXIICP',
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],
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'ram': [
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'SRAM', 'SRAM1', 'SRAM2',
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'D1_AXISRAM',
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'D1_ITCMRAM',
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'D1_DTCMRAM',
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'D1_AHBSRAM',
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'D2_AXISRAM',
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'D3_BKPSRAM',
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'D3_SRAM'
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],
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}
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def parse_chips():
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os.makedirs('data/chips', exist_ok=True)
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@ -488,19 +526,19 @@ def parse_chips():
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package_flashs = r['Flash']
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die = r['Die']
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if type(package_rams) != list:
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package_rams = [package_rams]*len(package_names)
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package_rams = [package_rams] * len(package_names)
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if type(package_flashs) != list:
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package_flashs = [package_flashs]*len(package_names)
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package_flashs = [package_flashs] * len(package_names)
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for package_i, package_name in enumerate(package_names):
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chip_name = chip_name_from_package_name(package_name)
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flash = OrderedDict( {
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'size': int(package_flashs[package_i]),
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'base': None,
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} )
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ram = OrderedDict( {
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'size': int(package_rams[package_i]),
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'base': None,
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} )
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flash = OrderedDict({
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'bytes': DecimalInt(int(package_flashs[package_i]) * 1024),
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'regions': []
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})
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ram = OrderedDict({
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'bytes': DecimalInt(int(package_rams[package_i]) * 1024),
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'regions': [],
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})
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gpio_af = next(filter(lambda x: x['@Name'] == 'GPIO', r['IP']))['@Version']
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gpio_af = removesuffix(gpio_af, '_gpio_v1_0')
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@ -586,7 +624,7 @@ def parse_chips():
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for ip in r['IP']:
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pname = ip['@InstanceName']
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pkind = ip['@Name']+':'+ip['@Version']
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pkind = ip['@Name'] + ':' + ip['@Version']
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pkind = removesuffix(pkind, '_Cube')
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if pname == 'SYS':
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@ -595,7 +633,7 @@ def parse_chips():
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continue
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if pname.startswith('ADC'):
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if not 'ADC_COMMON' in peris:
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peris['ADC_COMMON'] = 'ADC_COMMON:'+removesuffix(ip['@Version'], '_Cube')
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peris['ADC_COMMON'] = 'ADC_COMMON:' + removesuffix(ip['@Version'], '_Cube')
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peris[pname] = pkind
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pins[pname] = []
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@ -653,14 +691,57 @@ def parse_chips():
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raise Exception("missing header for {}".format(chip_name))
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h = headers_parsed[h]
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chip['flash']['base'] = h['defines']['all']['FLASH_BASE']
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found = []
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for each in memories_map['flash']:
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if each + '_BASE' in h['defines']['all']:
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if each == 'FLASH':
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key = 'BANK_1'
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elif each == 'FLASH_BANK1':
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key = 'BANK_1'
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elif each == 'FLASH_BANK2':
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key = 'BANK_2'
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else:
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key = each
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if key in found:
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continue
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found.append(key)
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chip['flash']['regions'].append(
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OrderedDict({
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key: {
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'base': HexInt(h['defines']['all'][each + '_BASE']),
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}
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})
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)
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found = []
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for each in memories_map['ram']:
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if each + '_BASE' in h['defines']['all']:
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if each == 'D1_AXISRAM':
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key = 'SRAM'
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elif each == 'SRAM1':
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key = 'SRAM'
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else:
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key = each
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if key in found:
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continue
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found.append(key)
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chip['ram']['regions'].append(
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OrderedDict({
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key: {
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'base': HexInt(h['defines']['all'][each + '_BASE'])
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}
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})
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)
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if 'SRAM_BASE' in h['defines']['all']:
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chip['ram']['base'] = h['defines']['all']['SRAM_BASE']
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elif 'SRAM1_BASE' in h['defines']['all']:
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chip['ram']['base'] = h['defines']['all']['SRAM1_BASE']
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elif 'D1_AXISRAM_BASE' in h['defines']['all']:
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chip['ram']['base'] = h['defines']['all']['D1_AXISRAM_BASE']
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# print("Got", len(chip['cores']), "cores")
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for core in chip['cores']:
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@ -672,7 +753,7 @@ def parse_chips():
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if not core_name in h['interrupts'] or not core_name in h['defines']:
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core_name = 'all'
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#print("Defining for core", core_name)
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# print("Defining for core", core_name)
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# Gather all interrupts and defines for this core
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@ -702,7 +783,7 @@ def parse_chips():
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if pname in clocks[rcc]:
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p['clock'] = clocks[rcc][pname]
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if block := match_peri(chip_name+':'+pname+':'+pkind):
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if block := match_peri(chip_name + ':' + pname + ':' + pkind):
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p['block'] = block
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if pname in chip['pins']:
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@ -725,7 +806,7 @@ def parse_chips():
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# Handle GPIO specially.
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for p in range(20):
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port = 'GPIO' + chr(ord('A')+p)
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port = 'GPIO' + chr(ord('A') + p)
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if addr := defines.get(port + '_BASE'):
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block = 'gpio_v2/GPIO'
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if chip['family'] == 'STM32F1':
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@ -743,7 +824,7 @@ def parse_chips():
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p = OrderedDict({
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'address': addr,
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})
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if block := match_peri(chip_name+':'+dma+':DMA'):
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if block := match_peri(chip_name + ':' + dma + ':DMA'):
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p['block'] = block
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if chip_nvic in chip_interrupts:
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@ -755,13 +836,13 @@ def parse_chips():
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# DMAMUX is not in the cubedb XMLs
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for dma in ('DMAMUX', 'DMAMUX1', "DMAMUX2"):
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if addr := defines.get(dma+'_BASE'):
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if addr := defines.get(dma + '_BASE'):
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kind = 'DMAMUX:v1'
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dbg_peri = OrderedDict({
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'address': addr,
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'kind': kind,
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})
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if block := match_peri(chip_name+':'+dma+':'+kind):
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if block := match_peri(chip_name + ':' + dma + ':' + kind):
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dbg_peri['block'] = block
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peris[dma] = dbg_peri
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@ -852,7 +933,6 @@ def parse_chips():
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# Process peripheral - DMA channel associations
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for pname, p in peris.items():
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if (peri_chs := dma_channels[chip_dma]['peripherals'].get(pname)) is not None:
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p['dma_channels'] = {
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req: [
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ch
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@ -866,7 +946,7 @@ def parse_chips():
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del chip['pins']
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del chip['peripherals']
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with open('data/chips/'+chip_name+'.yaml', 'w') as f:
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with open('data/chips/' + chip_name + '.yaml', 'w') as f:
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f.write(yaml.dump(chip, width=500))
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@ -874,7 +954,7 @@ af = {}
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def parse_gpio_af():
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#os.makedirs('data/gpio_af', exist_ok=True)
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# os.makedirs('data/gpio_af', exist_ok=True)
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for f in glob('sources/cubedb/mcu/IP/GPIO-*_gpio_v1_0_Modes.xml'):
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if 'STM32F1' in f:
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continue
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@ -956,7 +1036,7 @@ def parse_dma():
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with open(mf, 'r') as yaml_file:
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y = yaml.load(yaml_file, Loader=SafeLoader)
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mf = removesuffix(mf, '.yaml')
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dmamux = mf[mf.index('_')+1:] # DMAMUX1 or DMAMUX2
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dmamux = mf[mf.index('_') + 1:] # DMAMUX1 or DMAMUX2
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for (request_name, request_num) in y.items():
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parts = request_name.split('_')
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@ -990,8 +1070,8 @@ def parse_dma():
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if low == 1:
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low -= 1
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high -= 1
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for i in range(low, high+1):
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chip_dma['channels'][n+'_CH'+str(i)] = OrderedDict({
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for i in range(low, high + 1):
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chip_dma['channels'][n + '_CH' + str(i)] = OrderedDict({
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'dma': n,
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'channel': i,
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'dmamux': dmamux,
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@ -1114,7 +1194,7 @@ def match_peri_clock(rcc_block, peri_name):
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family_clocks = peripheral_to_clock[rcc_block]
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if peri_name in family_clocks:
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return family_clocks[peri_name]
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#print("found no clock for ", peri_name)
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# print("found no clock for ", peri_name)
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if peri_name.endswith("1"):
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return match_peri_clock(rcc_block, removesuffix(peri_name, "1"))
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return None
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