Parse our memory location bases and name them well-ish.

parse.py

@@ -3,6 +3,7 @@
 import sys
 import xmltodict
 import yaml
+
 try:
     from yaml import CSafeLoader as SafeLoader
 except ImportError:
@@ -14,6 +15,24 @@ import os
 from collections import OrderedDict
 from glob import glob
 
+class DecimalInt:
+    def __init__(self, val):
+        self.val = val
+
+def represent_decimal_int(dumper, data):
+    return dumper.represent_int(data.val)
+
+yaml.add_representer(DecimalInt, represent_decimal_int)
+
+class HexInt:
+    def __init__(self, val):
+        self.val = val
+
+def represent_hex_int(dumper, data):
+    return dumper.represent_int(hex(data.val))
+
+yaml.add_representer(HexInt, represent_hex_int)
+
 
 def removeprefix(value: str, prefix: str, /) -> str:
     if value.startswith(prefix):
@@ -52,6 +71,7 @@ def represent_ordereddict(dumper, data):
 yaml.add_representer(OrderedDict, represent_ordereddict)
 
 
+
 def hexint_presenter(dumper, data):
     if data > 0x10000:
         return dumper.represent_int(hex(data))
@@ -112,6 +132,7 @@ def paren_ok(val):
             return False
     return n == 0
 
+
 # warning: horrible abomination ahead
 
 
@@ -467,6 +488,23 @@ def chip_name_from_package_name(x):
             return r
     raise Exception("bad name: {}".format(x))
 
+memories_map = {
+    'flash': [
+        'FLASH', 'FLASH_BANK1', 'FLASH_BANK2',
+        'D1_AXIFLASH', 'D1_AXIICP',
+    ],
+    'ram': [
+        'SRAM', 'SRAM1', 'SRAM2',
+        'D1_AXISRAM',
+        'D1_ITCMRAM',
+        'D1_DTCMRAM',
+        'D1_AHBSRAM',
+        'D2_AXISRAM',
+        'D3_BKPSRAM',
+        'D3_SRAM'
+    ],
+}
+
 
 def parse_chips():
     os.makedirs('data/chips', exist_ok=True)
@@ -494,12 +532,12 @@ def parse_chips():
         for package_i, package_name in enumerate(package_names):
             chip_name = chip_name_from_package_name(package_name)
             flash = OrderedDict({
-                'size': int(package_flashs[package_i]),
-                'base': None,
+                'bytes': DecimalInt(int(package_flashs[package_i]) * 1024),
+                'regions': []
             })
             ram = OrderedDict({
-                'size': int(package_rams[package_i]),
-                'base': None,
+                'bytes': DecimalInt(int(package_rams[package_i]) * 1024),
+                'regions': [],
             })
             gpio_af = next(filter(lambda x: x['@Name'] == 'GPIO', r['IP']))['@Version']
             gpio_af = removesuffix(gpio_af, '_gpio_v1_0')
@@ -653,14 +691,57 @@ def parse_chips():
             raise Exception("missing header for {}".format(chip_name))
         h = headers_parsed[h]
 
-        chip['flash']['base'] = h['defines']['all']['FLASH_BASE']
+        found = []
+
+        for each in memories_map['flash']:
+            if each + '_BASE' in h['defines']['all']:
+                if each == 'FLASH':
+                    key = 'BANK_1'
+                elif each == 'FLASH_BANK1':
+                    key = 'BANK_1'
+                elif each == 'FLASH_BANK2':
+                    key = 'BANK_2'
+                else:
+                    key = each
+
+                if key in found:
+                    continue
+
+                found.append(key)
+
+                chip['flash']['regions'].append(
+                    OrderedDict({
+                        key: {
+                            'base': HexInt(h['defines']['all'][each + '_BASE']),
+                        }
+                    })
+                )
+
+        found = []
+
+        for each in memories_map['ram']:
+            if each + '_BASE' in h['defines']['all']:
+                if each == 'D1_AXISRAM':
+                    key = 'SRAM'
+                elif each == 'SRAM1':
+                    key = 'SRAM'
+                else:
+                    key = each
+
+                if key in found:
+                    continue
+
+                found.append(key)
+
+                chip['ram']['regions'].append(
+                    OrderedDict({
+                        key: {
+                            'base': HexInt(h['defines']['all'][each + '_BASE'])
+                        }
+                    })
+                )
+
 
-        if 'SRAM_BASE' in h['defines']['all']:
-            chip['ram']['base'] = h['defines']['all']['SRAM_BASE']
-        elif 'SRAM1_BASE' in h['defines']['all']:
-            chip['ram']['base'] = h['defines']['all']['SRAM1_BASE']
-        elif 'D1_AXISRAM_BASE' in h['defines']['all']:
-            chip['ram']['base'] = h['defines']['all']['D1_AXISRAM_BASE']
 
         # print("Got", len(chip['cores']), "cores")
         for core in chip['cores']:
@@ -852,7 +933,6 @@ def parse_chips():
             # Process peripheral - DMA channel associations
             for pname, p in peris.items():
                 if (peri_chs := dma_channels[chip_dma]['peripherals'].get(pname)) is not None:
-
                     p['dma_channels'] = {
                         req: [
                             ch