Merge pull request #399 from eZioPan/dcache_v1

dcache v1

data/registers/dcache_v1.yaml

@@ -0,0 +1,193 @@
+block/DCACHE:
+  description: Data cache.
+  items:
+  - name: CR
+    description: DCACHE control register.
+    byte_offset: 0
+    fieldset: CR
+  - name: SR
+    description: DCACHE status register.
+    byte_offset: 4
+    fieldset: SR
+  - name: IER
+    description: DCACHE interrupt enable register.
+    byte_offset: 8
+    fieldset: IER
+  - name: FCR
+    description: DCACHE flag clear register.
+    byte_offset: 12
+    fieldset: FCR
+  - name: RHMONR
+    description: DCACHE read-hit monitor register.
+    byte_offset: 16
+    fieldset: RHMONR
+  - name: RMMONR
+    description: DCACHE read-miss monitor register.
+    byte_offset: 20
+    fieldset: RMMONR
+  - name: WHMONR
+    description: DCACHE write-hit monitor register.
+    byte_offset: 32
+    fieldset: WHMONR
+  - name: WMMONR
+    description: DCACHE write-miss monitor register.
+    byte_offset: 36
+    fieldset: WMMONR
+  - name: CMDRSADDRR
+    description: DCACHE command range start address register.
+    byte_offset: 40
+    fieldset: CMDRSADDRR
+  - name: CMDREADDRR
+    description: DCACHE command range end address register.
+    byte_offset: 44
+    fieldset: CMDREADDRR
+fieldset/CMDREADDRR:
+  description: DCACHE command range end address register.
+  fields:
+  - name: CMDENDADDR
+    description: end address of range to which the cache maintenance command specified in DCACHE_CR.CACHECMD field applies This register must be set before DCACHE_CR.CACHECMD is written.
+    bit_offset: 4
+    bit_size: 28
+fieldset/CMDRSADDRR:
+  description: DCACHE command range start address register.
+  fields:
+  - name: CMDSTARTADDR
+    description: start address of range to which the cache maintenance command specified in DCACHE_CR.CACHECMD field applies This register must be set before DCACHE_CR.CACHECMD is written..
+    bit_offset: 4
+    bit_size: 28
+fieldset/CR:
+  description: DCACHE control register.
+  fields:
+  - name: EN
+    description: enable.
+    bit_offset: 0
+    bit_size: 1
+  - name: CACHEINV
+    description: full cache invalidation Can be set by software, only when EN = 1. Cleared by hardware when the BUSYF flag is set (during full cache invalidation operation). Writing 0 has no effect.
+    bit_offset: 1
+    bit_size: 1
+  - name: CACHECMD
+    description: 'cache command maintenance operation (cleans and/or invalidates an address range) Can be set and cleared by software, only when no maintenance command is ongoing (BUSYCMDF = 0). others: reserved.'
+    bit_offset: 8
+    bit_size: 3
+  - name: STARTCMD
+    description: starts maintenance command (maintenance operation defined in CACHECMD). Can be set by software, only when EN = 1, BUSYCMDF = 0, BUSYF = 0 and CACHECMD = 0b001, 0b010 or 0b011. Cleared by hardware when the BUSYCMDF flag is set (during cache maintenance operation). Writing 0 has no effect.
+    bit_offset: 11
+    bit_size: 1
+  - name: RHITMEN
+    description: read-hit monitor enable.
+    bit_offset: 16
+    bit_size: 1
+  - name: RMISSMEN
+    description: read-miss monitor enable.
+    bit_offset: 17
+    bit_size: 1
+  - name: RHITMRST
+    description: read-hit monitor reset.
+    bit_offset: 18
+    bit_size: 1
+  - name: RMISSMRST
+    description: read-miss monitor reset.
+    bit_offset: 19
+    bit_size: 1
+  - name: WHITMEN
+    description: write-hit monitor enable.
+    bit_offset: 20
+    bit_size: 1
+  - name: WMISSMEN
+    description: write-miss monitor enable.
+    bit_offset: 21
+    bit_size: 1
+  - name: WHITMRST
+    description: write-hit monitor reset.
+    bit_offset: 22
+    bit_size: 1
+  - name: WMISSMRST
+    description: write-miss monitor reset.
+    bit_offset: 23
+    bit_size: 1
+  - name: HBURST
+    description: output burst type for cache master port read accesses Write access is always done in INCR burst type.
+    bit_offset: 31
+    bit_size: 1
+fieldset/FCR:
+  description: DCACHE flag clear register.
+  fields:
+  - name: CBSYENDF
+    description: clear full invalidate busy end flag Set by software.
+    bit_offset: 1
+    bit_size: 1
+  - name: CERRF
+    description: clear cache error flag Set by software.
+    bit_offset: 2
+    bit_size: 1
+  - name: CCMDENDF
+    description: clear command end flag Set by software.
+    bit_offset: 4
+    bit_size: 1
+fieldset/IER:
+  description: DCACHE interrupt enable register.
+  fields:
+  - name: BSYENDIE
+    description: interrupt enable on busy end Set by SW to enable an interrupt generation at the end of a cache full invalidate operation.
+    bit_offset: 1
+    bit_size: 1
+  - name: ERRIE
+    description: interrupt enable on cache error Set by software to enable an interrupt generation in case of cache functional error (eviction or clean operation write-back error).
+    bit_offset: 2
+    bit_size: 1
+  - name: CMDENDIE
+    description: interrupt enable on command end Set by software to enable an interrupt generation at the end of a cache command (clean and/or invalidate an address range).
+    bit_offset: 4
+    bit_size: 1
+fieldset/RHMONR:
+  description: DCACHE read-hit monitor register.
+  fields:
+  - name: RHITMON
+    description: cache read-hit monitor counter.
+    bit_offset: 0
+    bit_size: 32
+fieldset/RMMONR:
+  description: DCACHE read-miss monitor register.
+  fields:
+  - name: RMISSMON
+    description: cache read-miss monitor counter.
+    bit_offset: 0
+    bit_size: 16
+fieldset/SR:
+  description: DCACHE status register.
+  fields:
+  - name: BUSYF
+    description: full invalidate busy flag.
+    bit_offset: 0
+    bit_size: 1
+  - name: BSYENDF
+    description: full invalidate busy end flag Cleared by writing DCACHE_FCR.CBSYENDF = 1.
+    bit_offset: 1
+    bit_size: 1
+  - name: ERRF
+    description: cache error flag Cleared by writing DCACHE_FCR.CERRF = 1.
+    bit_offset: 2
+    bit_size: 1
+  - name: BUSYCMDF
+    description: command busy flag.
+    bit_offset: 3
+    bit_size: 1
+  - name: CMDENDF
+    description: command end flag Cleared by writing DCACHE_FCR.CCMDENDF = 1.
+    bit_offset: 4
+    bit_size: 1
+fieldset/WHMONR:
+  description: DCACHE write-hit monitor register.
+  fields:
+  - name: WHITMON
+    description: cache write-hit monitor counter.
+    bit_offset: 0
+    bit_size: 32
+fieldset/WMMONR:
+  description: DCACHE write-miss monitor register.
+  fields:
+  - name: WMISSMON
+    description: cache write-miss monitor counter.
+    bit_offset: 0
+    bit_size: 16

stm32-data-gen/src/chips.rs

@@ -601,6 +601,7 @@ impl PeriMatcher {
             ("STM32G0.1.*:.*:COMP:.*", ("comp", "v1", "COMP")),
             ("STM32G4.*:.*:COMP:.*", ("comp", "v2", "COMP")),
             ("STM32WL.*:.*:COMP:.*", ("comp", "v3", "COMP")),
+            (r".*:.*:DCACHE:.*", ("dcache", "v1", "DCACHE")),
         ];
 
         Self {