Unify handling of "ghost peripherals" missing from the XMLs.
This commit is contained in:
Dario Nieuwenhuis
parent
a447451969
commit
2d6befa3a4
@ -118,19 +118,19 @@ perimap = [
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('.*:ADC_COMMON:aditf5_v2_0', 'adccommon_v3/ADC_COMMON'),
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('.*:ADC_COMMON:aditf4_v3_0_WL', 'adccommon_v3/ADC_COMMON'),
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('.*:DCMI:cci_v2_0', 'dcmi_v1/DCMI'),
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('STM32F0.*:SYS:.*', 'syscfg_f0/SYSCFG'),
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('STM32F4.*:SYS:.*', 'syscfg_f4/SYSCFG'),
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('STM32F7.*:SYS:.*', 'syscfg_f7/SYSCFG'),
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('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'),
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('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),
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('STM32L1.*:SYS:.*', 'syscfg_l1/SYSCFG'),
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('STM32G0.*:SYS:.*', 'syscfg_g0/SYSCFG'),
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('STM32G4.*:SYS:.*', 'syscfg_g4/SYSCFG'),
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('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'),
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('STM32U5.*:SYS:.*', 'syscfg_u5/SYSCFG'),
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('STM32WB.*:SYS:.*', 'syscfg_wb/SYSCFG'),
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('STM32WL5.*:SYS:.*', 'syscfg_wl5/SYSCFG'),
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('STM32WLE.*:SYS:.*', 'syscfg_wle/SYSCFG'),
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('STM32F0.*:SYSCFG:.*', 'syscfg_f0/SYSCFG'),
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('STM32F4.*:SYSCFG:.*', 'syscfg_f4/SYSCFG'),
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('STM32F7.*:SYSCFG:.*', 'syscfg_f7/SYSCFG'),
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('STM32L4.*:SYSCFG:.*', 'syscfg_l4/SYSCFG'),
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('STM32L0.*:SYSCFG:.*', 'syscfg_l0/SYSCFG'),
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('STM32L1.*:SYSCFG:.*', 'syscfg_l1/SYSCFG'),
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('STM32G0.*:SYSCFG:.*', 'syscfg_g0/SYSCFG'),
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('STM32G4.*:SYSCFG:.*', 'syscfg_g4/SYSCFG'),
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('STM32H7.*:SYSCFG:.*', 'syscfg_h7/SYSCFG'),
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('STM32U5.*:SYSCFG:.*', 'syscfg_u5/SYSCFG'),
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('STM32WB.*:SYSCFG:.*', 'syscfg_wb/SYSCFG'),
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('STM32WL5.*:SYSCFG:.*', 'syscfg_wl5/SYSCFG'),
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('STM32WLE.*:SYSCFG:.*', 'syscfg_wle/SYSCFG'),
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('.*:IWDG:iwdg1_v2_0', 'iwdg_v2/IWDG'),
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('.*:WWDG:wwdg1_v1_0', 'wwdg_v1/WWDG'),
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@ -178,24 +178,24 @@ perimap = [
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('STM32WLE.*:EXTI:.*', 'exti_wle/EXTI'),
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('.*:EXTI:.*', 'exti_v1/EXTI'),
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('.*:STM32L0_crs_v1_0', 'crs_l0/CRS'),
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('STM32L0.*:CRS:.*', 'crs_l0/CRS'),
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('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'),
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('.*:STM32G0_pwr_v1_0', 'pwr_g0/PWR'),
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('.*:STM32G4_pwr_v1_0', 'pwr_g4/PWR'),
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('STM32H7(42|43|53|50).*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'),
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('.*:STM32H7_pwr_v1_0', 'pwr_h7smps/PWR'),
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('.*:STM32F4_pwr_v1_0', 'pwr_f4/PWR'),
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('.*:STM32F7_pwr_v1_0', 'pwr_f7/PWR'),
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('.*:STM32L1_pwr_v1_0', 'pwr_l1/PWR'),
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('.*:STM32U5_pwr_v1_0', 'pwr_u5/PWR'),
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('.*:STM32WL_pwr_v1_0', 'pwr_wl5/PWR'),
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('.*:STM32H7_flash_v1_0', 'flash_h7/FLASH'),
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('.*:STM32F0_flash_v1_0', 'flash_f0/FLASH'),
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('.*:STM32F1_flash_v1_0', 'flash_f1/FLASH'),
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('.*:STM32F4_flash_v1_0', 'flash_f4/FLASH'),
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('.*:STM32F7_flash_v1_0', 'flash_f7/FLASH'),
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('.*:STM32L4_flash_v1_0', 'flash_l4/FLASH'),
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('.*:STM32U5_flash_v1_0', 'flash_u5/FLASH'),
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('STM32G0.*:PWR:.*', 'pwr_g0/PWR'),
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('STM32G4.*:PWR:.*', 'pwr_g4/PWR'),
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('STM32H7(42|43|53|50).*:PWR:.*', 'pwr_h7/PWR'),
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('STM32H7.*:PWR:.*', 'pwr_h7smps/PWR'),
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('STM32F4.*:PWR:.*', 'pwr_f4/PWR'),
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('STM32F7.*:PWR:.*', 'pwr_f7/PWR'),
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('STM32L1.*:PWR:.*', 'pwr_l1/PWR'),
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('STM32U5.*:PWR:.*', 'pwr_u5/PWR'),
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('STM32WL.*:PWR:.*', 'pwr_wl5/PWR'),
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('STM32H7.*:FLASH:.*', 'flash_h7/FLASH'),
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('STM32F0.*:FLASH:.*', 'flash_f0/FLASH'),
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('STM32F1.*:FLASH:.*', 'flash_f1/FLASH'),
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('STM32F4.*:FLASH:.*', 'flash_f4/FLASH'),
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('STM32F7.*:FLASH:.*', 'flash_f7/FLASH'),
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('STM32L4.*:FLASH:.*', 'flash_l4/FLASH'),
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('STM32U5.*:FLASH:.*', 'flash_u5/FLASH'),
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('STM32F7.*:ETH:ETH:ethermac110_v2_0', 'eth_v1c/ETH'),
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('.*ETH:ethermac110_v3_0', 'eth_v2/ETH'),
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@ -205,35 +205,38 @@ perimap = [
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('STM32F7.*:TIM8:.*', 'timer_v1/TIM_ADV'),
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('.*TIM\d.*:gptimer.*', 'timer_v1/TIM_GP16'),
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('.*:STM32F0_dbgmcu_v1_0', 'dbgmcu_f0/DBGMCU'),
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('.*:STM32F1_dbgmcu_v1_0', 'dbgmcu_f1/DBGMCU'),
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('.*:STM32F2_dbgmcu_v1_0', 'dbgmcu_f2/DBGMCU'),
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('.*:STM32F3_dbgmcu_v1_0', 'dbgmcu_f3/DBGMCU'),
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('.*:STM32F4_dbgmcu_v1_0', 'dbgmcu_f4/DBGMCU'),
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('.*:STM32F7_dbgmcu_v1_0', 'dbgmcu_f7/DBGMCU'),
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('.*:STM32G0_dbgmcu_v1_0', 'dbgmcu_g0/DBGMCU'),
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('.*:STM32G4_dbgmcu_v1_0', 'dbgmcu_g4/DBGMCU'),
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('.*:STM32H7_dbgmcu_v1_0', 'dbgmcu_h7/DBGMCU'),
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('.*:STM32L0_dbgmcu_v1_0', 'dbgmcu_l0/DBGMCU'),
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('.*:STM32L1_dbgmcu_v1_0', 'dbgmcu_l1/DBGMCU'),
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('.*:STM32L4_dbgmcu_v1_0', 'dbgmcu_l4/DBGMCU'),
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('.*:STM32U5_dbgmcu_v1_0', 'dbgmcu_u5/DBGMCU'),
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('.*:STM32WB_dbgmcu_v1_0', 'dbgmcu_wb/DBGMCU'),
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('.*:STM32WL_dbgmcu_v1_0', 'dbgmcu_wl/DBGMCU'),
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('STM32F0.*:DBGMCU:.*', 'dbgmcu_f0/DBGMCU'),
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('STM32F1.*:DBGMCU:.*', 'dbgmcu_f1/DBGMCU'),
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('STM32F2.*:DBGMCU:.*', 'dbgmcu_f2/DBGMCU'),
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('STM32F3.*:DBGMCU:.*', 'dbgmcu_f3/DBGMCU'),
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('STM32F4.*:DBGMCU:.*', 'dbgmcu_f4/DBGMCU'),
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('STM32F7.*:DBGMCU:.*', 'dbgmcu_f7/DBGMCU'),
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('STM32G0.*:DBGMCU:.*', 'dbgmcu_g0/DBGMCU'),
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('STM32G4.*:DBGMCU:.*', 'dbgmcu_g4/DBGMCU'),
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('STM32H7.*:DBGMCU:.*', 'dbgmcu_h7/DBGMCU'),
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('STM32L0.*:DBGMCU:.*', 'dbgmcu_l0/DBGMCU'),
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('STM32L1.*:DBGMCU:.*', 'dbgmcu_l1/DBGMCU'),
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('STM32L4.*:DBGMCU:.*', 'dbgmcu_l4/DBGMCU'),
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('STM32U5.*:DBGMCU:.*', 'dbgmcu_u5/DBGMCU'),
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('STM32WB.*:DBGMCU:.*', 'dbgmcu_wb/DBGMCU'),
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('STM32WL.*:DBGMCU:.*', 'dbgmcu_wl/DBGMCU'),
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('STM32F1.*:GPIO.*', 'gpio_v1/GPIO'),
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('.*:GPIO.*', 'gpio_v2/GPIO'),
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('.*:IPCC:v1_0', 'ipcc_v1/IPCC'),
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('.*:DMAMUX:v1', 'dmamux_v1/DMAMUX'),
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('.*:DMAMUX.*', 'dmamux_v1/DMAMUX'),
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('.*:BDMA:DMA', 'bdma_v1/DMA'),
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('.*:BDMA:.*', 'bdma_v1/DMA'),
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('STM32H7.*:DMA2D:DMA2D:dma2d1_v1_0', 'dma2d_v2/DMA2D'),
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('.*:DMA2D:dma2d1_v1_0', 'dma2d_v1/DMA2D'),
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('STM32L4[PQRS].*:.*:DMA', 'bdma_v1/DMA'), # L4+
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('STM32L[04].*:.*:DMA', 'bdma_v2/DMA'), # L0, L4 non-plus (since plus is handled above)
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('STM32F030.C.*:.*:DMA', 'bdma_v2/DMA'), # Weird F0
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('STM32F09.*:.*:DMA', 'bdma_v2/DMA'), # Weird F0
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('STM32F[247].*:.*:DMA', 'dma_v2/DMA'),
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('STM32H7.*:.*:DMA', 'dma_v1/DMA'),
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('.*:DMA', 'bdma_v1/DMA'),
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('STM32L4[PQRS].*:DMA.*', 'bdma_v1/DMA'), # L4+
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('STM32L[04].*:DMA.*', 'bdma_v2/DMA'), # L0, L4 non-plus (since plus is handled above)
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('STM32F030.C.*:DMA.*', 'bdma_v2/DMA'), # Weird F0
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('STM32F09.*:DMA.*', 'bdma_v2/DMA'), # Weird F0
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('STM32F[247].*:DMA.*', 'dma_v2/DMA'),
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('STM32H7.*:DMA.*', 'dma_v1/DMA'),
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('.*:DMA.*', 'bdma_v1/DMA'),
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('.*:CAN:bxcan1_v1_1.*', 'can_bxcan/CAN'),
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# stm32F4 CRC peripheral
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@ -245,7 +248,12 @@ perimap = [
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('STM32L[04].*:CRC:integtest1_v2_0', 'crc_v3/CRC'),
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('.*:CRC:integtest1_v2_0', 'crc_v2/CRC'),
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('.*:CRC:integtest1_v2_2', 'crc_v3/CRC'),
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]
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ghost_peris = [
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'GPIOA', 'GPIOB', 'GPIOC', 'GPIOD', 'GPIOE', 'GPIOF', 'GPIOG', 'GPIOH', 'GPIOI', 'GPIOJ', 'GPIOK', 'GPIOL', 'GPIOM', 'GPION', 'GPIOO', 'GPIOP', 'GPIOQ', 'GPIOR', 'GPIOS', 'GPIOT',
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'DMA1', 'DMA2', 'BDMA', 'DMAMUX', 'DMAMUX1', 'DMAMUX2',
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'EXTI', 'FLASH', 'DBGMCU', 'CRS', 'PWR', 'AFIO',
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]
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# Device address overrides, in case of missing from headers
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@ -596,6 +604,10 @@ def parse_chips():
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peri_kinds[pname] = pkind
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for pname in ghost_peris:
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if pname not in peri_kinds and (addr := defines.get(f'{pname}_BASE')):
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peri_kinds[pname] = 'unknown'
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peris = {}
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for pname, pkind in peri_kinds.items():
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addr = defines.get(pname)
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@ -639,114 +651,6 @@ def parse_chips():
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for (extra_name, extra_p) in extra['peripherals'].items():
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peris[extra_name] = extra_p
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# Handle GPIO specially.
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for p in range(20):
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port = 'GPIO' + chr(ord('A') + p)
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if addr := lookup_address(defines, chip_name, port + '_BASE'):
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block = 'gpio_v2/GPIO'
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if chip['family'] == 'STM32F1':
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block = 'gpio_v1/GPIO'
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p = OrderedDict({
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'address': addr,
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'block': block,
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})
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peris[port] = p
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# Handle DMA specially.
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for dma in ('DMA1', 'DMA2', 'BDMA'):
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if addr := defines.get(dma + '_BASE'):
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p = OrderedDict({
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'address': addr,
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})
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if block := match_peri(chip_name + ':' + dma + ':DMA'):
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p['block'] = block
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if chip_nvic in chip_interrupts:
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if dma in chip_interrupts[chip_nvic]:
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# filter by available, because some are conditioned on <Die>
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p['interrupts'] = filter_interrupts(chip_interrupts[chip_nvic][dma], interrupts)
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peris[dma] = p
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# DMAMUX is not in the cubedb XMLs
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for dma in ('DMAMUX', 'DMAMUX1', "DMAMUX2"):
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if addr := defines.get(dma + '_BASE'):
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kind = 'DMAMUX:v1'
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dbg_peri = OrderedDict({
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'address': addr,
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'kind': kind,
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})
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if block := match_peri(chip_name + ':' + dma + ':' + kind):
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dbg_peri['block'] = block
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peris[dma] = dbg_peri
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# EXTI is not in the cubedb XMLs
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if addr := defines.get('EXTI_BASE'):
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peri = OrderedDict({
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'address': addr,
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'kind': 'EXTI',
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})
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if block := match_peri(chip_name + ':EXTI:EXTI:v1'):
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peri['block'] = block
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peris['EXTI'] = peri
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# FLASH is not in the cubedb XMLs
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if addr := defines.get('FLASH_R_BASE'):
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kind = 'FLASH:' + chip_name[:7] + '_flash_v1_0'
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flash_peri = OrderedDict({
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'address': addr,
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'kind': kind,
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})
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if block := match_peri(kind):
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flash_peri['block'] = block
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peris['FLASH'] = flash_peri
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# DBGMCU is not in the cubedb XMLs
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if addr := defines.get('DBGMCU_BASE') or defines.get('DBG_BASE'):
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kind = 'DBGMCU:' + chip_name[:7] + '_dbgmcu_v1_0'
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dbg_peri = OrderedDict({
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'address': addr,
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'kind': kind,
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})
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if block := match_peri(kind):
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dbg_peri['block'] = block
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peris['DBGMCU'] = dbg_peri
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# CRS is not in the cubedb XMLs
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if addr := defines.get('CRS_BASE'):
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kind = 'CRS:' + chip_name[:7] + '_crs_v1_0'
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crs_peri = OrderedDict({
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'address': addr,
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'kind': kind,
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})
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if block := match_peri(kind):
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crs_peri['block'] = block
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peris['CRS'] = crs_peri
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# PWR is not in some XMLs
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if 'PWR' not in peris:
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if addr := defines.get('PWR_BASE'):
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kind = 'PWR:' + chip_name[:7] + '_pwr_v1_0'
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pwr_peri = OrderedDict({
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'address': addr,
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'kind': kind,
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})
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if block := match_peri(kind):
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pwr_peri['block'] = block
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peris['PWR'] = pwr_peri
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# AFIO is not in the cubedb XMLs
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if addr := defines.get('AFIO_BASE'):
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kind = 'AFIO'
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afio_peri = OrderedDict({
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'address': addr,
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'kind': kind,
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})
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if block := match_peri(chip_name[:7] + ':' + kind + ':'):
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afio_peri['block'] = block
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peris['AFIO'] = afio_peri
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core['peripherals'] = peris
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if 'block' in core['peripherals']['RCC']:
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