From 2ceed56e9454a142e0c132b25542391a3b988a99 Mon Sep 17 00:00:00 2001 From: Matt Ickstadt Date: Thu, 5 Oct 2023 11:18:49 -0500 Subject: [PATCH] RCC: add LSEDRV enums for WB and WL series These are in the RMs but previously missing. --- data/registers/rcc_wb.yaml | 16 ++++++++++++++++ data/registers/rcc_wl5.yaml | 16 ++++++++++++++++ data/registers/rcc_wle.yaml | 16 ++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/data/registers/rcc_wb.yaml b/data/registers/rcc_wb.yaml index a0c7adc..1461252 100644 --- a/data/registers/rcc_wb.yaml +++ b/data/registers/rcc_wb.yaml @@ -723,6 +723,7 @@ fieldset/BDCR: description: SE oscillator drive capability bit_offset: 3 bit_size: 2 + enum: LSEDRV - name: LSECSSON description: LSECSSON bit_offset: 5 @@ -1717,3 +1718,18 @@ enum/RTCSEL: - name: HSE description: HSE oscillator clock divided by 32 selected value: 3 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Low + description: Low driving capability + value: 0 + - name: MediumLow + description: Medium low driving capability + value: 1 + - name: MediumHigh + description: Medium high driving capability + value: 2 + - name: High + description: High driving capability + value: 3 diff --git a/data/registers/rcc_wl5.yaml b/data/registers/rcc_wl5.yaml index a8ee025..38e1d87 100644 --- a/data/registers/rcc_wl5.yaml +++ b/data/registers/rcc_wl5.yaml @@ -669,6 +669,7 @@ fieldset/BDCR: description: LSE oscillator drive capability bit_offset: 3 bit_size: 2 + enum: LSEDRV - name: LSECSSON description: CSS on LSE enable bit_offset: 5 @@ -1569,3 +1570,18 @@ enum/RTCSEL: - name: HSE description: HSE oscillator clock divided by 32 selected value: 3 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Low + description: Low driving capability + value: 0 + - name: MediumLow + description: Medium low driving capability + value: 1 + - name: MediumHigh + description: Medium high driving capability + value: 2 + - name: High + description: High driving capability + value: 3 diff --git a/data/registers/rcc_wle.yaml b/data/registers/rcc_wle.yaml index 17d34f8..64c1330 100644 --- a/data/registers/rcc_wle.yaml +++ b/data/registers/rcc_wle.yaml @@ -605,6 +605,7 @@ fieldset/BDCR: description: LSE oscillator drive capability bit_offset: 3 bit_size: 2 + enum: LSEDRV - name: LSECSSON description: CSS on LSE enable bit_offset: 5 @@ -1191,3 +1192,18 @@ enum/RTCSEL: - name: HSE description: HSE oscillator clock divided by 32 selected value: 3 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Low + description: Low driving capability + value: 0 + - name: MediumLow + description: Medium low driving capability + value: 1 + - name: MediumHigh + description: Medium high driving capability + value: 2 + - name: High + description: High driving capability + value: 3