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Add correct H7 timer register blocks.

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This commit is contained in:
Matous Hybl 2021-11-29 10:16:37 +01:00
parent 8f150ead7f
commit 2b56ec9e99
1 changed files with 7 additions and 0 deletions
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7
stm32data/__main__.py
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@ -207,6 +207,13 @@ perimap = [
('.*LPTIM\d.*:G0xx_lptimer1_v1_4', 'lptim_g0/LPTIM'),
('STM32H7.*:TIM1:.*', 'timer_v1/TIM_ADV'),
('STM32H7.*:TIM2:.*', 'timer_v1/TIM_GP32'),
('STM32H7.*:TIM5:.*', 'timer_v1/TIM_GP32'),
('STM32H7.*:TIM6:.*', 'timer_v1/TIM_BASIC'),
('STM32H7.*:TIM7:.*', 'timer_v1/TIM_BASIC'),
('STM32H7.*:TIM8:.*', 'timer_v1/TIM_ADV'),
('STM32F7.*:TIM1:.*', 'timer_v1/TIM_ADV'),
('STM32F7.*:TIM8:.*', 'timer_v1/TIM_ADV'),
('.*TIM\d.*:gptimer.*', 'timer_v1/TIM_GP16'),