Merge pull request #351 from eZioPan/eth-cleanup

Eth cleanup

data/registers/eth_v1a.yaml

@@ -301,7 +301,6 @@ fieldset/DMABMR:
     description: Address-aligned beats
     bit_offset: 25
     bit_size: 1
-    enum: AAB
 fieldset/DMACHRBAR:
   description: Ethernet DMA current host receive buffer address register
   fields:
@@ -1000,7 +999,6 @@ fieldset/MMCCR:
     description: MMC counter freeze
     bit_offset: 3
     bit_size: 1
-    enum: MCF
 fieldset/MMCRFAECR:
   description: Ethernet MMC received frames with alignment error counter register
   fields:
@@ -1262,15 +1260,6 @@ fieldset/PTPTTLR:
     description: TTSL
     bit_offset: 0
     bit_size: 32
-enum/AAB:
-  bit_size: 1
-  variants:
-  - name: Unaligned
-    description: Bursts are not aligned
-    value: 0
-  - name: Aligned
-    description: Align bursts to start address LS bits. First burst alignment depends on FB bit
-    value: 1
 enum/APCS:
   bit_size: 1
   variants:
@@ -1547,15 +1536,6 @@ enum/MB_progress:
   - name: Busy
     description: This bit is set to 1 by the application to indicate that a read or write access is in progress
     value: 1
-enum/MCF:
-  bit_size: 1
-  variants:
-  - name: Unfrozen
-    description: All MMC counters update normally
-    value: 0
-  - name: Frozen
-    description: All MMC counters frozen to their current value
-    value: 1
 enum/MW:
   bit_size: 1
   variants:

data/registers/eth_v1b.yaml

@@ -309,7 +309,6 @@ fieldset/DMABMR:
     description: Address-aligned beats
     bit_offset: 25
     bit_size: 1
-    enum: AAB
   - name: MB
     description: Mixed burst
     bit_offset: 26
@@ -1024,7 +1023,6 @@ fieldset/MMCCR:
     description: MMC counter freeze
     bit_offset: 3
     bit_size: 1
-    enum: MCF
   - name: MCP
     description: MMC counter preset
     bit_offset: 4
@@ -1296,15 +1294,6 @@ fieldset/PTPTTLR:
     description: TTSL
     bit_offset: 0
     bit_size: 32
-enum/AAB:
-  bit_size: 1
-  variants:
-  - name: Unaligned
-    description: Bursts are not aligned
-    value: 0
-  - name: Aligned
-    description: Align bursts to start address LS bits. First burst alignment depends on FB bit
-    value: 1
 enum/APCS:
   bit_size: 1
   variants:
@@ -1590,15 +1579,6 @@ enum/MB_progress:
   - name: Busy
     description: This bit is set to 1 by the application to indicate that a read or write access is in progress
     value: 1
-enum/MCF:
-  bit_size: 1
-  variants:
-  - name: Unfrozen
-    description: All MMC counters update normally
-    value: 0
-  - name: Frozen
-    description: All MMC counters frozen to their current value
-    value: 1
 enum/MCFHP:
   bit_size: 1
   variants:

data/registers/eth_v1c.yaml

@@ -309,7 +309,6 @@ fieldset/DMABMR:
     description: Address-aligned beats
     bit_offset: 25
     bit_size: 1
-    enum: AAB
   - name: MB
     description: Mixed burst
     bit_offset: 26
@@ -1024,7 +1023,6 @@ fieldset/MMCCR:
     description: MMC counter freeze
     bit_offset: 3
     bit_size: 1
-    enum: MCF
   - name: MCP
     description: MMC counter preset
     bit_offset: 4
@@ -1296,15 +1294,6 @@ fieldset/PTPTTLR:
     description: TTSL
     bit_offset: 0
     bit_size: 32
-enum/AAB:
-  bit_size: 1
-  variants:
-  - name: Unaligned
-    description: Bursts are not aligned
-    value: 0
-  - name: Aligned
-    description: Align bursts to start address LS bits. First burst alignment depends on FB bit
-    value: 1
 enum/APCS:
   bit_size: 1
   variants:
@@ -1590,15 +1579,6 @@ enum/MB_progress:
   - name: Busy
     description: This bit is set to 1 by the application to indicate that a read or write access is in progress
     value: 1
-enum/MCF:
-  bit_size: 1
-  variants:
-  - name: Unfrozen
-    description: All MMC counters update normally
-    value: 0
-  - name: Frozen
-    description: All MMC counters frozen to their current value
-    value: 1
 enum/MCFHP:
   bit_size: 1
   variants:

data/registers/eth_v2.yaml

@@ -126,14 +126,6 @@ block/ETHERNET_MAC:
     description: Watchdog timeout register
     byte_offset: 12
     fieldset: MACWTR
-  - name: MACHT0R
-    description: Hash Table 0 register
-    byte_offset: 16
-    fieldset: MACHT0R
-  - name: MACHT1R
-    description: Hash Table 1 register
-    byte_offset: 20
-    fieldset: MACHT1R
   - name: MACVTR
     description: VLAN tag register
     byte_offset: 80
@@ -232,30 +224,6 @@ block/ETHERNET_MAC:
     description: Address 0 low register
     byte_offset: 772
     fieldset: MACA0LR
-  - name: MACA1HR
-    description: Address 1 high register
-    byte_offset: 776
-    fieldset: MACA1HR
-  - name: MACA1LR
-    description: Address 1 low register
-    byte_offset: 780
-    fieldset: MACA1LR
-  - name: MACA2HR
-    description: Address 2 high register
-    byte_offset: 784
-    fieldset: MACA2HR
-  - name: MACA2LR
-    description: Address 2 low register
-    byte_offset: 788
-    fieldset: MACA2LR
-  - name: MACA3HR
-    description: Address 3 high register
-    byte_offset: 792
-    fieldset: MACA3HR
-  - name: MACA3LR
-    description: Address 3 low register
-    byte_offset: 796
-    fieldset: MACA3LR
   - name: MMC_CONTROL
     description: MMC control register
     byte_offset: 1792
@@ -495,6 +463,27 @@ block/ETHERNET_MAC:
     description: Log message interval register
     byte_offset: 3024
     fieldset: MACLMIR
+  - name: MACAHR
+    description: Address 1/2/3 high register
+    array:
+      len: 3
+      stride: 8
+    byte_offset: 776
+    fieldset: MACAHR
+  - name: MACALR
+    description: Address 1/2/3 low register
+    array:
+      len: 3
+      stride: 8
+    byte_offset: 780
+    fieldset: MACALR
+  - name: MACHTR
+    description: Hash Table 0/1 register
+    array:
+      len: 2
+      stride: 4
+    byte_offset: 16
+    fieldset: MACHTR
 block/ETHERNET_MTL:
   description: 'Ethernet: MTL mode register (MTL)'
   items:
@@ -895,84 +884,6 @@ fieldset/MACA0LR:
     description: MAC Address 0 [31:0]
     bit_offset: 0
     bit_size: 32
-fieldset/MACA1HR:
-  description: Address 1 high register
-  fields:
-  - name: ADDRHI
-    description: MAC Address1 [47:32]
-    bit_offset: 0
-    bit_size: 16
-  - name: MBC
-    description: Mask Byte Control
-    bit_offset: 24
-    bit_size: 6
-  - name: SA
-    description: Source Address
-    bit_offset: 30
-    bit_size: 1
-  - name: AE
-    description: Address Enable
-    bit_offset: 31
-    bit_size: 1
-fieldset/MACA1LR:
-  description: Address 1 low register
-  fields:
-  - name: ADDRLO
-    description: MAC Address 1 [31:0]
-    bit_offset: 0
-    bit_size: 32
-fieldset/MACA2HR:
-  description: Address 2 high register
-  fields:
-  - name: ADDRHI
-    description: MAC Address2 [47:32]
-    bit_offset: 0
-    bit_size: 16
-  - name: MBC
-    description: Mask Byte Control
-    bit_offset: 24
-    bit_size: 6
-  - name: SA
-    description: Source Address
-    bit_offset: 30
-    bit_size: 1
-  - name: AE
-    description: Address Enable
-    bit_offset: 31
-    bit_size: 1
-fieldset/MACA2LR:
-  description: Address 2 low register
-  fields:
-  - name: ADDRLO
-    description: MAC Address 2 [31:0]
-    bit_offset: 0
-    bit_size: 32
-fieldset/MACA3HR:
-  description: Address 3 high register
-  fields:
-  - name: ADDRHI
-    description: MAC Address3 [47:32]
-    bit_offset: 0
-    bit_size: 16
-  - name: MBC
-    description: Mask Byte Control
-    bit_offset: 24
-    bit_size: 6
-  - name: SA
-    description: Source Address
-    bit_offset: 30
-    bit_size: 1
-  - name: AE
-    description: Address Enable
-    bit_offset: 31
-    bit_size: 1
-fieldset/MACA3LR:
-  description: Address 3 low register
-  fields:
-  - name: ADDRLO
-    description: MAC Address 3 [31:0]
-    bit_offset: 0
-    bit_size: 32
 fieldset/MACACR:
   description: Auxiliary control register
   fields:
@@ -980,22 +891,39 @@ fieldset/MACACR:
     description: Auxiliary Snapshot FIFO Clear
     bit_offset: 0
     bit_size: 1
-  - name: ATSEN0
+  - name: ATSEN
-    description: Auxiliary Snapshot 0 Enable
+    description: Auxiliary Snapshot 0-3 Enable
     bit_offset: 4
     bit_size: 1
-  - name: ATSEN1
+    array:
-    description: Auxiliary Snapshot 1 Enable
+      len: 4
-    bit_offset: 5
+      stride: 1
+fieldset/MACAHR:
+  description: Address 1/2/3 high register
+  fields:
+  - name: ADDRHI
+    description: MAC Address 1/2/3 [47:32]
+    bit_offset: 0
+    bit_size: 16
+  - name: MBC
+    description: Mask Byte Control
+    bit_offset: 24
+    bit_size: 6
+  - name: SA
+    description: Source Address
+    bit_offset: 30
     bit_size: 1
-  - name: ATSEN2
+  - name: AE
-    description: Auxiliary Snapshot 2 Enable
+    description: Address Enable
-    bit_offset: 6
+    bit_offset: 31
-    bit_size: 1
-  - name: ATSEN3
-    description: Auxiliary Snapshot 3 Enable
-    bit_offset: 7
     bit_size: 1
+fieldset/MACALR:
+  description: Address 1/2/3 low register
+  fields:
+  - name: ADDRLO
+    description: MAC Address 1/2/3 [31:0]
+    bit_offset: 0
+    bit_size: 32
 fieldset/MACARPAR:
   description: ARP address register
   fields:
@@ -1158,18 +1086,11 @@ fieldset/MACECR:
     description: Extended Inter-Packet Gap
     bit_offset: 25
     bit_size: 5
-fieldset/MACHT0R:
+fieldset/MACHTR:
-  description: Hash Table 0 register
+  description: Hash Table 0/1 register
   fields:
-  - name: HT31T0
+  - name: HT
-    description: MAC Hash Table First 32 Bits
+    description: MAC Hash Table 32 Bits
-    bit_offset: 0
-    bit_size: 32
-fieldset/MACHT1R:
-  description: Hash Table 1 register
-  fields:
-  - name: HT63T32
-    description: MAC Hash Table Second 32 Bits
     bit_offset: 0
     bit_size: 32
 fieldset/MACHWF1R:

transforms/ETH.yaml

@@ -1,6 +1,6 @@
 transforms:
   - !DeleteEnums
-    from: ^(DC|GU|MPE|PAM|PM|RA|RFCE|ROR|SAF|TFCE|UPFD|WFE|CSTF|EDFE|MACAHR_AE)$
+    from: ^(DC|GU|MPE|PAM|PM|RA|RFCE|ROR|SAF|TFCE|UPFD|WFE|CSTF|EDFE|MACAHR_AE|MCF|AAB)$
   - !RenameEnumVariants
     enum: ^CSR$
     from: Disabled
@@ -9,6 +9,13 @@ transforms:
     enum: ^CSR$
     from: Enabled
     to: NotRollover
+
+  - !MakeFieldArray
+    fieldsets: ^MACACR$
+    from: ATSEN\d
+    to: ATSEN
+
+  # merge MAC Address 1/2/3 high/low register
   - !RenameFields
     fieldset: .*
     from: MACA[1-3]([HL])
@@ -27,3 +34,16 @@ transforms:
     blocks: .*
     from: MACA[1-3]LR
     to: MACALR
+
+  # merge Hash Table 0/1 register
+  - !RenameFields
+    fieldset: MACHT\dR
+    from: HT.+
+    to: HT
+  - !MergeFieldsets
+    from: MACHT\dR
+    to: MACHTR
+  - !MakeRegisterArray
+    blocks: ^ETHERNET_MAC$
+    from: MACHT\dR
+    to: MACHTR