Added rtc registers for stm32l5
This commit is contained in:
Christian Enderle
parent
8caf2f0bda
commit
28306c1d75
963
data/registers/rtc_v3l5.yaml
Normal file
963
data/registers/rtc_v3l5.yaml
Normal file
@ -0,0 +1,963 @@
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---
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block/RTC:
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description: Real-time clock
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items:
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- name: TR
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description: Time register
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byte_offset: 0
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fieldset: TR
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- name: DR
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description: Date register
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byte_offset: 4
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fieldset: DR
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- name: SSR
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description: Sub second register
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byte_offset: 8
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access: Read
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fieldset: SSR
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- name: ICSR
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description: Initialization control and status register
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byte_offset: 12
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fieldset: ICSR
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- name: PRER
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description: Prescaler register
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byte_offset: 16
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fieldset: PRER
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- name: WUTR
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description: Wakeup timer register
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byte_offset: 20
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fieldset: WUTR
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- name: CR
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description: Control register
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byte_offset: 24
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fieldset: CR
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- name: PRIVCR
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description: Privilege mode control register
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byte_offset: 28
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fieldset: PRIVCR
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- name: SMCR
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description:
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byte_offset: 32
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fieldset: SMCR
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- name: WPR
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description: Write protection register
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byte_offset: 36
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access: Write
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fieldset: WPR
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- name: CALR
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description: Calibration register
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byte_offset: 40
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fieldset: CALR
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- name: SHIFTR
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description: Shift control register
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byte_offset: 44
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access: Write
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fieldset: SHIFTR
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- name: TSTR
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description: Timestamp time register
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byte_offset: 48
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access: Read
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fieldset: TSTR
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- name: TSDR
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description: Timestamp date register
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byte_offset: 52
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access: Read
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fieldset: TSDR
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- name: TSSSR
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description: Timestamp sub second register
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byte_offset: 56
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access: Read
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fieldset: TSSSR
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- name: ALRMR
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description: Alarm register
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array:
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len: 2
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stride: 8
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byte_offset: 64
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fieldset: ALRMR
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- name: ALRMSSR
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description: Alarm sub second register
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array:
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len: 2
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stride: 8
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byte_offset: 68
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fieldset: ALRMSSR
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- name: SR
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description: Status register
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byte_offset: 80
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access: Read
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fieldset: SR
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- name: MISR
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description: Masked interrupt status register
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byte_offset: 84
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access: Read
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fieldset: MISR
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- name: SMISR
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description: Secure masked interrupt status register
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byte_offset: 88
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access: Read
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fieldset: SMISR
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- name: SCR
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description: Status clear register
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byte_offset: 92
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access: Write
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fieldset: SCR
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fieldset/ALRMR:
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description: Alarm register
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fields:
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- name: SU
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description: Second units in BCD format
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bit_offset: 0
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bit_size: 4
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- name: ST
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description: Second tens in BCD format
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bit_offset: 4
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bit_size: 3
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- name: MSK1
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description: Alarm A seconds mask
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bit_offset: 7
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bit_size: 1
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enum: ALRMR_MSK
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- name: MNU
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description: Minute units in BCD format
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bit_offset: 8
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bit_size: 4
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- name: MNT
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description: Minute tens in BCD format
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bit_offset: 12
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bit_size: 3
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- name: MSK2
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description: Alarm A minutes mask
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bit_offset: 15
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bit_size: 1
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enum: ALRMR_MSK
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- name: HU
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description: Hour units in BCD format
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bit_offset: 16
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bit_size: 4
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- name: HT
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description: Hour tens in BCD format
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bit_offset: 20
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bit_size: 2
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- name: PM
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description: AM/PM notation
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bit_offset: 22
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bit_size: 1
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enum: ALRMR_PM
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- name: MSK3
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description: Alarm A hours mask
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bit_offset: 23
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bit_size: 1
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enum: ALRMR_MSK
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- name: DU
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description: Date units or day in BCD format
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bit_offset: 24
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bit_size: 4
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- name: DT
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description: Date tens in BCD format
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bit_offset: 28
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bit_size: 2
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- name: WDSEL
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description: Week day selection
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bit_offset: 30
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bit_size: 1
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enum: ALRMR_WDSEL
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- name: MSK4
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description: Alarm A date mask
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bit_offset: 31
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bit_size: 1
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enum: ALRMR_MSK
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fieldset/ALRMSSR:
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description: Alarm sub second register
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fields:
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- name: SS
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description: Sub seconds value
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bit_offset: 0
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bit_size: 15
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- name: MASKSS
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description: Mask the most-significant bits starting at this bit
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bit_offset: 24
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bit_size: 4
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fieldset/CALR:
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description: Calibration register
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fields:
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- name: CALM
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description: Calibration minus
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bit_offset: 0
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bit_size: 9
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- name: LPCAL
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description: Calibration low-power mode
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bit_offset: 12
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bit_size: 1
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enum: LPCAL
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- name: CALW16
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description: Use a 16-second calibration cycle period
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bit_offset: 13
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bit_size: 1
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enum: CALW16
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- name: CALW8
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description: Use an 8-second calibration cycle period
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bit_offset: 14
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bit_size: 1
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enum: CALW8
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- name: CALP
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description: Increase frequency of RTC by 488.5 ppm
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bit_offset: 15
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bit_size: 1
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enum: CALP
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fieldset/CR:
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description: Control register
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fields:
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- name: WUCKSEL
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description: Wakeup clock selection
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bit_offset: 0
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bit_size: 3
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enum: WUCKSEL
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- name: TSEDGE
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description: Timestamp event active edge
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bit_offset: 3
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bit_size: 1
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enum: TSEDGE
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- name: REFCKON
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description: RTC_REFIN reference clock detection enable (50 or 60 Hz)
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bit_offset: 4
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bit_size: 1
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- name: BYPSHAD
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description: Bypass the shadow registers
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bit_offset: 5
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bit_size: 1
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- name: FMT
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description: Hour format
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bit_offset: 6
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bit_size: 1
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enum: FMT
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- name: ALRE
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description: Alarm enable
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bit_offset: 8
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bit_size: 1
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array:
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len: 2
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stride: 1
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- name: WUTE
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description: Wakeup timer enable
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bit_offset: 10
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bit_size: 1
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- name: TSE
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description: Timestamp enable
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bit_offset: 11
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bit_size: 1
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- name: ALRIE
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description: Alarm interrupt enable
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bit_offset: 12
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bit_size: 1
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array:
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len: 2
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stride: 1
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- name: WUTIE
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description: Wakeup timer interrupt enable
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bit_offset: 14
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bit_size: 1
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- name: TSIE
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description: Timestamp interrupt enable
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bit_offset: 15
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bit_size: 1
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- name: ADD1H
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description: Add 1 hour (summer time change)
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bit_offset: 16
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bit_size: 1
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- name: SUB1H
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description: Subtract 1 hour (winter time change)
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bit_offset: 17
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bit_size: 1
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- name: BKP
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description: Backup
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bit_offset: 18
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bit_size: 1
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- name: COSEL
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description: Calibration output selection
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bit_offset: 19
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bit_size: 1
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enum: COSEL
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- name: POL
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description: Output polarity
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bit_offset: 20
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bit_size: 1
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enum: POL
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- name: OSEL
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description: Output selection
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bit_offset: 21
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bit_size: 2
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enum: OSEL
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- name: COE
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description: Calibration output enable
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bit_offset: 23
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bit_size: 1
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- name: ITSE
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description: Timestamp on internal event enable
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bit_offset: 24
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bit_size: 1
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- name: TAMPTS
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description: Activate timestamp on tamper detection event
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bit_offset: 25
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bit_size: 1
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- name: TAMPOE
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description: Tamper detection output enable on TAMPALRM
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bit_offset: 26
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bit_size: 1
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- name: TAMPALRM_PU
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description: TAMPALRM pull-up enable
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bit_offset: 29
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bit_size: 1
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- name: TAMPALRM_TYPE
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description: TAMPALRM output type
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bit_offset: 30
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bit_size: 1
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enum: TAMPALRM_TYPE
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- name: OUT2EN
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description: RTC_OUT2 output enable
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bit_offset: 31
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bit_size: 1
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fieldset/DR:
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description: Date register
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fields:
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- name: DU
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description: Date units in BCD format
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bit_offset: 0
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bit_size: 4
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- name: DT
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description: Date tens in BCD format
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bit_offset: 4
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bit_size: 2
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- name: MU
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description: Month units in BCD format
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bit_offset: 8
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bit_size: 4
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- name: MT
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description: Month tens in BCD format
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bit_offset: 12
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bit_size: 1
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- name: WDU
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description: Week day units
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bit_offset: 13
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bit_size: 3
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- name: YU
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description: Year units in BCD format
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bit_offset: 16
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bit_size: 4
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- name: YT
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description: Year tens in BCD format
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bit_offset: 20
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bit_size: 4
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fieldset/ICSR:
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description: Initialization control and status register
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fields:
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- name: WUTWF
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description: Wakeup timer write flag
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bit_offset: 2
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bit_size: 1
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- name: SHPF
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description: Shift operation pending
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bit_offset: 3
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bit_size: 1
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- name: INITS
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description: Initialization status flag
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bit_offset: 4
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bit_size: 1
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- name: RSF
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description: Registers synchronization flag
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bit_offset: 5
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bit_size: 1
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- name: INITF
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description: Initialization flag
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bit_offset: 6
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bit_size: 1
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- name: INIT
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description: Initialization mode
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bit_offset: 7
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bit_size: 1
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- name: RECALPF
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description: Recalibration pending Flag
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bit_offset: 16
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bit_size: 1
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enum: RECALPF
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fieldset/MISR:
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description: Masked interrupt status register
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fields:
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- name: ALRMF
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description: Alarm masked flag
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bit_offset: 0
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bit_size: 1
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array:
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len: 2
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stride: 1
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enum: ALRMF
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- name: WUTMF
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description: Wakeup timer masked flag
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bit_offset: 2
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bit_size: 1
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enum: WUTMF
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- name: TSMF
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description: Timestamp masked flag
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bit_offset: 3
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bit_size: 1
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enum: TSMF
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- name: TSOVMF
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description: Timestamp overflow masked flag
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bit_offset: 4
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bit_size: 1
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enum: TSOVMF
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- name: ITSMF
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description: Internal timestamp masked flag
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bit_offset: 5
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bit_size: 1
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enum: ITSMF
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fieldset/PRER:
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description: Prescaler register
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fields:
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- name: PREDIV_S
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description: Synchronous prescaler factor
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bit_offset: 0
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bit_size: 15
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- name: PREDIV_A
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description: Asynchronous prescaler factor
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bit_offset: 16
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bit_size: 7
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fieldset/PRIVCR:
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description: Privilege mode control register
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fields:
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- name: ALRPRIV
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description: ALRAPRIV
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bit_offset: 0
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bit_size: 1
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array:
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len: 2
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stride: 1
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- name: WUTPRIV
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description: WUTPRIV
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bit_offset: 2
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bit_size: 1
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- name: TSPRIV
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description: TSPRIV
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: CALPRIV
|
||||||
|
description: CALPRIV
|
||||||
|
bit_offset: 13
|
||||||
|
bit_size: 1
|
||||||
|
- name: INITPRIV
|
||||||
|
description: INITPRIV
|
||||||
|
bit_offset: 14
|
||||||
|
bit_size: 1
|
||||||
|
- name: PRIV
|
||||||
|
description: PRIV
|
||||||
|
bit_offset: 15
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/SMCR:
|
||||||
|
description: RTC secure mode control register
|
||||||
|
fields:
|
||||||
|
- name: ALRDPROT
|
||||||
|
description: Alarm x protection
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 2
|
||||||
|
stride: 1
|
||||||
|
- name: WUTDPROT
|
||||||
|
description: Wakeup timer protection
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
- name: TSDPROT
|
||||||
|
description: Timestamp protection
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: CALDPROT
|
||||||
|
description: Shift register, daylight saving, calibration and reference clock protection
|
||||||
|
bit_offset: 13
|
||||||
|
bit_size: 1
|
||||||
|
- name: INITDPROT
|
||||||
|
description: Initialization protection
|
||||||
|
bit_offset: 14
|
||||||
|
bit_size: 1
|
||||||
|
- name: DECPROT
|
||||||
|
description: RTC global protection
|
||||||
|
bit_offset: 15
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/SCR:
|
||||||
|
description: Status clear register
|
||||||
|
fields:
|
||||||
|
- name: CALRF
|
||||||
|
description: Clear alarm x flag
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 2
|
||||||
|
stride: 1
|
||||||
|
enum: CALRF
|
||||||
|
- name: CWUTF
|
||||||
|
description: Clear wakeup timer flag
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
enum: CALRF
|
||||||
|
- name: CTSF
|
||||||
|
description: Clear timestamp flag
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
enum: CALRF
|
||||||
|
- name: CTSOVF
|
||||||
|
description: Clear timestamp overflow flag
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
enum: CALRF
|
||||||
|
- name: CITSF
|
||||||
|
description: Clear internal timestamp flag
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
enum: CALRF
|
||||||
|
fieldset/SHIFTR:
|
||||||
|
description: Shift control register
|
||||||
|
fields:
|
||||||
|
- name: SUBFS
|
||||||
|
description: Subtract a fraction of a second
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 15
|
||||||
|
- name: ADD1S
|
||||||
|
description: Add one second
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/SMISR:
|
||||||
|
description: Secure masked interrupt status register
|
||||||
|
fields:
|
||||||
|
- name: ALRMF
|
||||||
|
description: Alarm x interrupt secure masked flag
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 2
|
||||||
|
stride: 1
|
||||||
|
- name: WUTMF
|
||||||
|
description: WUTMF
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
- name: TSMF
|
||||||
|
description: TSMF
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: TSOVMF
|
||||||
|
description: TSOVMF
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
- name: ITSMF
|
||||||
|
description: ITSMF
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/SR:
|
||||||
|
description: Status register
|
||||||
|
fields:
|
||||||
|
- name: ALRF
|
||||||
|
description: Alarm flag
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 2
|
||||||
|
stride: 1
|
||||||
|
enum: ALRF
|
||||||
|
- name: WUTF
|
||||||
|
description: Wakeup timer flag
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
enum: WUTF
|
||||||
|
- name: TSF
|
||||||
|
description: Timestamp flag
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
enum: TSF
|
||||||
|
- name: TSOVF
|
||||||
|
description: Timestamp overflow flag
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
enum: TSOVF
|
||||||
|
- name: ITSF
|
||||||
|
description: Internal timestamp flag
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
enum: ITSF
|
||||||
|
fieldset/SSR:
|
||||||
|
description: Sub second register
|
||||||
|
fields:
|
||||||
|
- name: SS
|
||||||
|
description: Synchronous binary counter
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 16
|
||||||
|
fieldset/TR:
|
||||||
|
description: Time register
|
||||||
|
fields:
|
||||||
|
- name: SU
|
||||||
|
description: Second units in BCD format
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 4
|
||||||
|
- name: ST
|
||||||
|
description: Second tens in BCD format
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 3
|
||||||
|
- name: MNU
|
||||||
|
description: Minute units in BCD format
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 4
|
||||||
|
- name: MNT
|
||||||
|
description: Minute tens in BCD format
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 3
|
||||||
|
- name: HU
|
||||||
|
description: Hour units in BCD format
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 4
|
||||||
|
- name: HT
|
||||||
|
description: Hour tens in BCD format
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 2
|
||||||
|
- name: PM
|
||||||
|
description: AM/PM notation
|
||||||
|
bit_offset: 22
|
||||||
|
bit_size: 1
|
||||||
|
enum: AMPM
|
||||||
|
fieldset/TSDR:
|
||||||
|
description: Timestamp date register
|
||||||
|
fields:
|
||||||
|
- name: DU
|
||||||
|
description: Date units in BCD format
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 4
|
||||||
|
- name: DT
|
||||||
|
description: Date tens in BCD format
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 2
|
||||||
|
- name: MU
|
||||||
|
description: Month units in BCD format
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 4
|
||||||
|
- name: MT
|
||||||
|
description: Month tens in BCD format
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 1
|
||||||
|
- name: WDU
|
||||||
|
description: Week day units
|
||||||
|
bit_offset: 13
|
||||||
|
bit_size: 3
|
||||||
|
fieldset/TSSSR:
|
||||||
|
description: Timestamp sub second register
|
||||||
|
fields:
|
||||||
|
- name: SS
|
||||||
|
description: Sub second value
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 16
|
||||||
|
fieldset/TSTR:
|
||||||
|
description: Timestamp time register
|
||||||
|
fields:
|
||||||
|
- name: SU
|
||||||
|
description: Second units in BCD format
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 4
|
||||||
|
- name: ST
|
||||||
|
description: Second tens in BCD format
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 3
|
||||||
|
- name: MNU
|
||||||
|
description: Minute units in BCD format
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 4
|
||||||
|
- name: MNT
|
||||||
|
description: Minute tens in BCD format
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 3
|
||||||
|
- name: HU
|
||||||
|
description: Hour units in BCD format
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 4
|
||||||
|
- name: HT
|
||||||
|
description: Hour tens in BCD format
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 2
|
||||||
|
- name: PM
|
||||||
|
description: AM/PM notation
|
||||||
|
bit_offset: 22
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/WPR:
|
||||||
|
description: Write protection register
|
||||||
|
fields:
|
||||||
|
- name: KEY
|
||||||
|
description: Write protection key
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
|
enum: KEY
|
||||||
|
fieldset/WUTR:
|
||||||
|
description: Wakeup timer register
|
||||||
|
fields:
|
||||||
|
- name: WUT
|
||||||
|
description: Wakeup auto-reload value bits
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 16
|
||||||
|
- name: WUTOCLR
|
||||||
|
description: Wakeup auto-reload output clear value
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 16
|
||||||
|
enum/ALRF:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Match
|
||||||
|
description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)
|
||||||
|
value: 1
|
||||||
|
enum/ALRMF:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Match
|
||||||
|
description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)
|
||||||
|
value: 1
|
||||||
|
enum/ALRMR_MSK:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Mask
|
||||||
|
description: Alarm set if the date/day match
|
||||||
|
value: 0
|
||||||
|
- name: NotMask
|
||||||
|
description: Date/day don’t care in Alarm comparison
|
||||||
|
value: 1
|
||||||
|
enum/ALRMR_PM:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: AM
|
||||||
|
description: AM or 24-hour format
|
||||||
|
value: 0
|
||||||
|
- name: PM
|
||||||
|
description: PM
|
||||||
|
value: 1
|
||||||
|
enum/ALRMR_WDSEL:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: DateUnits
|
||||||
|
description: "DU[3:0] represents the date units"
|
||||||
|
value: 0
|
||||||
|
- name: WeekDay
|
||||||
|
description: "DU[3:0] represents the week day. DT[1:0] is don’t care."
|
||||||
|
value: 1
|
||||||
|
enum/AMPM:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: AM
|
||||||
|
description: AM or 24-hour format
|
||||||
|
value: 0
|
||||||
|
- name: PM
|
||||||
|
description: PM
|
||||||
|
value: 1
|
||||||
|
enum/CALP:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: NoChange
|
||||||
|
description: No RTCCLK pulses are added
|
||||||
|
value: 0
|
||||||
|
- name: IncreaseFreq
|
||||||
|
description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)
|
||||||
|
value: 1
|
||||||
|
enum/CALRF:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Clear
|
||||||
|
description: Clear interrupt flag by writing 1
|
||||||
|
value: 1
|
||||||
|
enum/CALW16:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: SixteenSeconds
|
||||||
|
description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1"
|
||||||
|
value: 1
|
||||||
|
enum/CALW8:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: EightSeconds
|
||||||
|
description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected"
|
||||||
|
value: 1
|
||||||
|
enum/COSEL:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: CalFreq_512Hz
|
||||||
|
description: Calibration output is 512 Hz (with default prescaler setting)
|
||||||
|
value: 0
|
||||||
|
- name: CalFreq_1Hz
|
||||||
|
description: Calibration output is 1 Hz (with default prescaler setting)
|
||||||
|
value: 1
|
||||||
|
enum/FMT:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: TwentyFourHour
|
||||||
|
description: 24 hour/day format
|
||||||
|
value: 0
|
||||||
|
- name: AmPm
|
||||||
|
description: AM/PM hour format
|
||||||
|
value: 1
|
||||||
|
enum/ITSF:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: TimestampEvent
|
||||||
|
description: This flag is set by hardware when a timestamp on the internal event occurs
|
||||||
|
value: 1
|
||||||
|
enum/ITSMF:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: TimestampEvent
|
||||||
|
description: This flag is set by hardware when a timestamp on the internal event occurs
|
||||||
|
value: 1
|
||||||
|
enum/KEY:
|
||||||
|
bit_size: 8
|
||||||
|
variants:
|
||||||
|
- name: Activate
|
||||||
|
description: Activate write protection (any value that is not the keys)
|
||||||
|
value: 0
|
||||||
|
- name: Deactivate2
|
||||||
|
description: Key 2
|
||||||
|
value: 83
|
||||||
|
- name: Deactivate1
|
||||||
|
description: Key 1
|
||||||
|
value: 202
|
||||||
|
enum/LPCAL:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: RTCCLK
|
||||||
|
description: "Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required"
|
||||||
|
value: 0
|
||||||
|
- name: CkApre
|
||||||
|
description: "Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode"
|
||||||
|
value: 1
|
||||||
|
enum/OSEL:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: Disabled
|
||||||
|
description: Output disabled
|
||||||
|
value: 0
|
||||||
|
- name: AlarmA
|
||||||
|
description: Alarm A output enabled
|
||||||
|
value: 1
|
||||||
|
- name: AlarmB
|
||||||
|
description: Alarm B output enabled
|
||||||
|
value: 2
|
||||||
|
- name: Wakeup
|
||||||
|
description: Wakeup output enabled
|
||||||
|
value: 3
|
||||||
|
enum/POL:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: High
|
||||||
|
description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"
|
||||||
|
value: 0
|
||||||
|
- name: Low
|
||||||
|
description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"
|
||||||
|
value: 1
|
||||||
|
enum/RECALPF:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Pending
|
||||||
|
description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0"
|
||||||
|
value: 1
|
||||||
|
enum/REFCKON:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Disabled
|
||||||
|
description: RTC_REFIN detection disabled
|
||||||
|
value: 0
|
||||||
|
- name: Enabled
|
||||||
|
description: RTC_REFIN detection enabled
|
||||||
|
value: 1
|
||||||
|
enum/SSRUF:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Underflow
|
||||||
|
description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1
|
||||||
|
value: 1
|
||||||
|
enum/SSRUMF:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Underflow
|
||||||
|
description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1
|
||||||
|
value: 1
|
||||||
|
enum/TAMPALRM_PU:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: NoPullUp
|
||||||
|
description: No pull-up is applied on TAMPALRM output
|
||||||
|
value: 0
|
||||||
|
- name: PullUp
|
||||||
|
description: A pull-up is applied on TAMPALRM output
|
||||||
|
value: 1
|
||||||
|
enum/TAMPALRM_TYPE:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: PushPull
|
||||||
|
description: TAMPALRM is push-pull output
|
||||||
|
value: 0
|
||||||
|
- name: OpenDrain
|
||||||
|
description: TAMPALRM is open-drain output
|
||||||
|
value: 1
|
||||||
|
enum/TSEDGE:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: RisingEdge
|
||||||
|
description: RTC_TS input rising edge generates a time-stamp event
|
||||||
|
value: 0
|
||||||
|
- name: FallingEdge
|
||||||
|
description: RTC_TS input falling edge generates a time-stamp event
|
||||||
|
value: 1
|
||||||
|
enum/TSF:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: TimestampEvent
|
||||||
|
description: This flag is set by hardware when a time-stamp event occurs
|
||||||
|
value: 1
|
||||||
|
enum/TSMF:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: TimestampEvent
|
||||||
|
description: This flag is set by hardware when a time-stamp event occurs
|
||||||
|
value: 1
|
||||||
|
enum/TSOVF:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Overflow
|
||||||
|
description: This flag is set by hardware when a time-stamp event occurs while TSF is already set
|
||||||
|
value: 1
|
||||||
|
enum/TSOVMF:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Overflow
|
||||||
|
description: This flag is set by hardware when a time-stamp event occurs while TSF is already set
|
||||||
|
value: 1
|
||||||
|
enum/WUCKSEL:
|
||||||
|
bit_size: 3
|
||||||
|
variants:
|
||||||
|
- name: Div16
|
||||||
|
description: RTC/16 clock is selected
|
||||||
|
value: 0
|
||||||
|
- name: Div8
|
||||||
|
description: RTC/8 clock is selected
|
||||||
|
value: 1
|
||||||
|
- name: Div4
|
||||||
|
description: RTC/4 clock is selected
|
||||||
|
value: 2
|
||||||
|
- name: Div2
|
||||||
|
description: RTC/2 clock is selected
|
||||||
|
value: 3
|
||||||
|
- name: ClockSpare
|
||||||
|
description: ck_spre (usually 1 Hz) clock is selected
|
||||||
|
value: 4
|
||||||
|
- name: ClockSpareWithOffset
|
||||||
|
description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
|
||||||
|
value: 6
|
||||||
|
enum/WUTF:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Zero
|
||||||
|
description: This flag is set by hardware when the wakeup auto-reload counter reaches 0
|
||||||
|
value: 1
|
||||||
|
enum/WUTMF:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Zero
|
||||||
|
description: This flag is set by hardware when the wakeup auto-reload counter reaches 0
|
||||||
|
value: 1
|
||||||
@ -263,6 +263,7 @@ impl PeriMatcher {
|
|||||||
("STM32L0.*:RTC:rtc2_.*", ("rtc", "v2l0", "RTC")),
|
("STM32L0.*:RTC:rtc2_.*", ("rtc", "v2l0", "RTC")),
|
||||||
("STM32L1.*:RTC:rtc2_.*", ("rtc", "v2l1", "RTC")),
|
("STM32L1.*:RTC:rtc2_.*", ("rtc", "v2l1", "RTC")),
|
||||||
("STM32L4.*:RTC:rtc2_.*", ("rtc", "v2l4", "RTC")),
|
("STM32L4.*:RTC:rtc2_.*", ("rtc", "v2l4", "RTC")),
|
||||||
|
("STM32L5.*:RTC:rtc2_.*", ("rtc", "v3l5", "RTC")),
|
||||||
("STM32WBA.*:RTC:rtc2_.*", ("rtc", "v3u5", "RTC")),
|
("STM32WBA.*:RTC:rtc2_.*", ("rtc", "v3u5", "RTC")),
|
||||||
("STM32WB.*:RTC:rtc2_.*", ("rtc", "v2wb", "RTC")),
|
("STM32WB.*:RTC:rtc2_.*", ("rtc", "v2wb", "RTC")),
|
||||||
("STM32H5.*:RTC:rtc2_.*", ("rtc", "v3u5", "RTC")),
|
("STM32H5.*:RTC:rtc2_.*", ("rtc", "v3u5", "RTC")),
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user