From 27c71ac451ff9011fca1d09dc3b7c1d92929bfb7 Mon Sep 17 00:00:00 2001
From: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Date: Tue, 21 Nov 2023 10:40:16 +0000
Subject: [PATCH] fdcan: generate register blocks for message RAM

this is a special case, as most data sources don't mention this as a
separate peripheral at all, and those that do don't handle the offsets
in the case of multiple FDCANS

H7 chips have a single 10KB block shared between all FDCANs
---
 data/registers/fdcanram_h7.yaml | 10 ++++++++
 data/registers/fdcanram_v1.yaml | 45 +++++++++++++++++++++++++++++++++
 stm32-data-gen/src/chips.rs     | 36 ++++++++++++++++++++++++++
 stm32-data-gen/src/header.rs    |  1 +
 4 files changed, 92 insertions(+)
 create mode 100644 data/registers/fdcanram_h7.yaml
 create mode 100644 data/registers/fdcanram_v1.yaml

diff --git a/data/registers/fdcanram_h7.yaml b/data/registers/fdcanram_h7.yaml
new file mode 100644
index 0000000..3ea15da
--- /dev/null
+++ b/data/registers/fdcanram_h7.yaml
@@ -0,0 +1,10 @@
+block/FDCANRAM:
+  description: FDCAN Message RAM
+  items:
+  - name: RAM
+    description: FDCAN Message RAM
+    array:
+      len: 2560
+      stride: 4
+    byte_offset: 0
+    bit_size: 32
diff --git a/data/registers/fdcanram_v1.yaml b/data/registers/fdcanram_v1.yaml
new file mode 100644
index 0000000..73c2ee1
--- /dev/null
+++ b/data/registers/fdcanram_v1.yaml
@@ -0,0 +1,45 @@
+block/FDCANRAM:
+  description: FDCAN Message RAM
+  items:
+  - name: FLSSA
+    description: 11-bit filter
+    array:
+      len: 28
+      stride: 4
+    byte_offset: 0
+    bit_size: 32
+  - name: FLESA
+    description: 29-bit filter
+    array:
+      len: 16
+      stride: 4
+    byte_offset: 112
+    bit_size: 32
+  - name: RXFIFO0
+    description: Rx FIFO 0
+    array:
+      len: 54
+      stride: 4
+    byte_offset: 176
+    bit_size: 32
+  - name: RXFIFO1
+    description: Rx FIFO 1
+    array:
+      len: 54
+      stride: 4
+    byte_offset: 392
+    bit_size: 32
+  - name: TXEFIFO
+    description: Tx event FIFO
+    array:
+      len: 6
+      stride: 4
+    byte_offset: 608
+    bit_size: 32
+  - name: TXBUF
+    description: Tx buffer
+    array:
+      len: 54
+      stride: 4
+    byte_offset: 632
+    bit_size: 32
diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs
index e889ddd..ad0812f 100644
--- a/stm32-data-gen/src/chips.rs
+++ b/stm32-data-gen/src/chips.rs
@@ -459,6 +459,8 @@ impl PeriMatcher {
             (".*:CAN:bxcan1_v1_1.*", ("can", "bxcan", "CAN")),
             ("STM32H7.*:FDCAN:fdcan1_v1_[01].*", ("can", "fdcan_h7", "FDCAN")),
             (".*:FDCAN:fdcan1_v1_[01].*", ("can", "fdcan_v1", "FDCAN")),
+            ("STM32H7.*:FDCANRAM.*", ("fdcanram", "h7", "FDCANRAM")),
+            (".*:FDCANRAM.*", ("fdcanram", "v1", "FDCANRAM")),
             // # stm32F4 CRC peripheral
             // # ("STM32F4*:CRC:CRC:crc_f4")
             // # v1: F1, F2, F4, L1
@@ -883,6 +885,29 @@ fn process_core(
     if peri_kinds.contains_key("BDMA1") {
         peri_kinds.remove("BDMA");
     }
+    let fdcans = peri_kinds
+        .keys()
+        .filter_map(|pname| {
+            regex!(r"^FDCAN(?<idx>[0-9]+)$")
+                .captures(pname)
+                .map(|cap| cap["idx"].to_string())
+        })
+        .collect::<Vec<_>>();
+    if !fdcans.is_empty() {
+        if chip_name.starts_with("STM32H7") {
+            // H7 has one message RAM shared between FDCANs
+            peri_kinds
+                .entry("FDCANRAM".to_string())
+                .or_insert("unknown".to_string());
+        } else {
+            // Other chips with FDCANs have separate message RAM per module
+            for fdcan in fdcans {
+                peri_kinds
+                    .entry(format!("FDCANRAM{}", fdcan))
+                    .or_insert("unknown".to_string());
+            }
+        }
+    }
     // get possible used GPIOs for each peripheral from the chip xml
     // it's not the full info we would want (stuff like AFIO info which comes from GPIO xml),
     //   but we actually need to use it because of F1 line
@@ -929,6 +954,17 @@ fn process_core(
             defines.get_peri_addr("ADC1")
         } else if chip_name.starts_with("STM32H7") && pname == "HRTIM" {
             defines.get_peri_addr("HRTIM1")
+        } else if let Some(cap) = regex!(r"^FDCANRAM(?<idx>[0-9]+)$").captures(&pname) {
+            defines.get_peri_addr("FDCANRAM").and_then(|addr| {
+                if chip_name.starts_with("STM32H7") {
+                    Some(addr)
+                } else {
+                    let idx = u32::from_str_radix(&cap["idx"], 10).unwrap();
+                    // FIXME: this offset should not be hardcoded, but I think
+                    // it appears in no data sources (only in RMs)
+                    Some(addr + (idx - 1) * 0x350)
+                }
+            })
         } else {
             defines.get_peri_addr(&pname)
         };
diff --git a/stm32-data-gen/src/header.rs b/stm32-data-gen/src/header.rs
index 7052ad2..f1f1bf9 100644
--- a/stm32-data-gen/src/header.rs
+++ b/stm32-data-gen/src/header.rs
@@ -174,6 +174,7 @@ impl Defines {
                 "USBRAM",
                 &["USB_PMAADDR", "USB_DRD_PMAADDR", "USB_PMAADDR_NS", "USB_DRD_PMAADDR_NS"],
             ),
+            ("FDCANRAM", &["SRAMCAN_BASE", "SRAMCAN_BASE_NS"]),
         ];
         let alt_peri_defines: HashMap<_, _> = ALT_PERI_DEFINES.iter().copied().collect();