spi: rename v4 to v5, add v4 for h5.
This commit is contained in:
Dario Nieuwenhuis
parent
93cbb06a4a
commit
2715747076
@ -32,9 +32,6 @@ block/SPI:
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byte_offset: 24
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byte_offset: 24
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access: Write
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access: Write
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fieldset: IFCR
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fieldset: IFCR
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- name: AUTOCR
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byte_offset: 28
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fieldset: AUTOCR
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- name: TXDR
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- name: TXDR
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description: Transmit Data Register
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description: Transmit Data Register
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byte_offset: 32
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byte_offset: 32
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@ -61,21 +58,6 @@ block/SPI:
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description: Underrun Data Register
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description: Underrun Data Register
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byte_offset: 76
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byte_offset: 76
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fieldset: UDRDR
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fieldset: UDRDR
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fieldset/AUTOCR:
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fields:
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- name: TRIGSEL
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description: "trigger selection (refer ).\n ...\n Note: these bits can be written only when SPE = 0."
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bit_offset: 16
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bit_size: 4
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- name: TRIGPOL
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description: "trigger polarity\n Note: This bit can be written only when SPE = 0."
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bit_offset: 20
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bit_size: 1
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enum: TRIGPOL
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- name: TRIGEN
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description: "trigger of CSTART control enable\n Note: if user can't prevent trigger event during write, the TRIGEN has to be changed when SPI is disabled"
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bit_offset: 21
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bit_size: 1
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fieldset/CFG1:
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fieldset/CFG1:
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description: configuration register 1
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description: configuration register 1
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fields:
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fields:
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@ -699,15 +681,6 @@ enum/TCRCINI:
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- name: AllOnes
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- name: AllOnes
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description: All ones TX CRC initialization pattern
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description: All ones TX CRC initialization pattern
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value: 1
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value: 1
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enum/TRIGPOL:
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bit_size: 1
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variants:
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- name: RisingEdge
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description: trigger is active on raising edge
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value: 0
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- name: FallingEdge
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description: trigger is active on falling edge
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value: 1
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enum/UDRCFG:
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enum/UDRCFG:
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bit_size: 2
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bit_size: 2
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variants:
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variants:
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722
data/registers/spi_v5.yaml
Normal file
722
data/registers/spi_v5.yaml
Normal file
@ -0,0 +1,722 @@
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---
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block/SPI:
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description: Serial peripheral interface
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items:
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- name: CR1
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description: control register 1
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byte_offset: 0
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fieldset: CR1
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- name: CR2
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description: control register 2
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byte_offset: 4
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fieldset: CR2
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- name: CFG1
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description: configuration register 1
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byte_offset: 8
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fieldset: CFG1
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- name: CFG2
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description: configuration register 2
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byte_offset: 12
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fieldset: CFG2
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- name: IER
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description: Interrupt Enable Register
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byte_offset: 16
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fieldset: IER
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- name: SR
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description: Status Register
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byte_offset: 20
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access: Read
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fieldset: SR
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- name: IFCR
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description: Interrupt/Status Flags Clear Register
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byte_offset: 24
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access: Write
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fieldset: IFCR
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- name: AUTOCR
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byte_offset: 28
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fieldset: AUTOCR
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- name: TXDR
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description: Transmit Data Register
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byte_offset: 32
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access: Write
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fieldset: TXDR
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- name: RXDR
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description: Receive Data Register
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byte_offset: 48
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access: Read
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fieldset: RXDR
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- name: CRCPOLY
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description: Polynomial Register
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byte_offset: 64
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fieldset: CRCPOLY
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- name: TXCRC
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description: Transmitter CRC Register
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byte_offset: 68
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fieldset: TXCRC
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- name: RXCRC
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description: Receiver CRC Register
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byte_offset: 72
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fieldset: RXCRC
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- name: UDRDR
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description: Underrun Data Register
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byte_offset: 76
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fieldset: UDRDR
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fieldset/AUTOCR:
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fields:
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- name: TRIGSEL
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description: "trigger selection (refer ).\n ...\n Note: these bits can be written only when SPE = 0."
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bit_offset: 16
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bit_size: 4
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- name: TRIGPOL
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description: "trigger polarity\n Note: This bit can be written only when SPE = 0."
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bit_offset: 20
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bit_size: 1
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enum: TRIGPOL
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- name: TRIGEN
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description: "trigger of CSTART control enable\n Note: if user can't prevent trigger event during write, the TRIGEN has to be changed when SPI is disabled"
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bit_offset: 21
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bit_size: 1
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fieldset/CFG1:
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description: configuration register 1
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fields:
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- name: DSIZE
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description: Number of bits in at single SPI data frame
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bit_offset: 0
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bit_size: 5
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- name: FTHLV
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description: threshold level
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bit_offset: 5
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bit_size: 4
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enum: FTHLV
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- name: UDRCFG
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description: Behavior of slave transmitter at underrun condition
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bit_offset: 9
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bit_size: 2
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enum: UDRCFG
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- name: RXDMAEN
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description: Rx DMA stream enable
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bit_offset: 14
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bit_size: 1
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- name: TXDMAEN
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description: Tx DMA stream enable
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bit_offset: 15
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bit_size: 1
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- name: CRCSIZE
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description: Length of CRC frame to be transacted and compared
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bit_offset: 16
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bit_size: 5
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- name: CRCEN
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description: Hardware CRC computation enable
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bit_offset: 22
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bit_size: 1
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- name: MBR
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description: Master baud rate
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bit_offset: 28
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bit_size: 3
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enum: MBR
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- name: BPASS
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description: bypass of the prescaler at master baud rate clock generator
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bit_offset: 31
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bit_size: 1
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fieldset/CFG2:
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description: configuration register 2
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fields:
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- name: MSSI
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description: Master SS Idleness
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bit_offset: 0
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bit_size: 4
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- name: MIDI
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description: Master Inter-Data Idleness
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bit_offset: 4
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bit_size: 4
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- name: RDIOM
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description: "RDY signal input/output management\n Note: When DSIZE at the CFG1 register is configured shorter than 8-bit, the RDIOM bit has to be kept at zero."
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bit_offset: 13
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bit_size: 1
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enum: RDIOM
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- name: RDIOP
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description: RDY signal input/output polarity
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bit_offset: 14
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bit_size: 1
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enum: RDIOP
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- name: IOSWP
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description: Swap functionality of MISO and MOSI pins
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bit_offset: 15
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bit_size: 1
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- name: COMM
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description: SPI Communication Mode
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bit_offset: 17
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bit_size: 2
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enum: COMM
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- name: SP
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description: Serial Protocol
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bit_offset: 19
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bit_size: 3
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enum: SP
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- name: MASTER
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description: SPI Master
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bit_offset: 22
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bit_size: 1
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enum: MASTER
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- name: LSBFIRST
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description: Data frame format
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bit_offset: 23
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bit_size: 1
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enum: LSBFIRST
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- name: CPHA
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description: Clock phase
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bit_offset: 24
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bit_size: 1
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enum: CPHA
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- name: CPOL
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description: Clock polarity
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bit_offset: 25
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bit_size: 1
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enum: CPOL
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- name: SSM
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description: Software management of SS signal input
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bit_offset: 26
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bit_size: 1
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- name: SSIOP
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description: SS input/output polarity
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bit_offset: 28
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bit_size: 1
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enum: SSIOP
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- name: SSOE
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description: SS output enable
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bit_offset: 29
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bit_size: 1
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- name: SSOM
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description: SS output management in master mode
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bit_offset: 30
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bit_size: 1
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enum: SSOM
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- name: AFCNTR
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description: Alternate function GPIOs control
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bit_offset: 31
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bit_size: 1
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enum: AFCNTR
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fieldset/CR1:
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description: control register 1
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fields:
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- name: SPE
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description: Serial Peripheral Enable
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bit_offset: 0
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bit_size: 1
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- name: MASRX
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description: Master automatic SUSP in Receive mode
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bit_offset: 8
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bit_size: 1
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- name: CSTART
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description: Master transfer start
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bit_offset: 9
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bit_size: 1
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- name: CSUSP
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description: Master SUSPend request
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bit_offset: 10
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bit_size: 1
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- name: HDDIR
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description: Rx/Tx direction at Half-duplex mode
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bit_offset: 11
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bit_size: 1
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enum: HDDIR
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- name: SSI
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description: Internal SS signal input level
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bit_offset: 12
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bit_size: 1
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- name: CRC33_17
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description: 32-bit CRC polynomial configuration
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bit_offset: 13
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bit_size: 1
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enum: CRC_
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- name: RCRCINI
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description: CRC calculation initialization pattern control for receiver
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bit_offset: 14
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bit_size: 1
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enum: RCRCINI
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- name: TCRCINI
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description: CRC calculation initialization pattern control for transmitter
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bit_offset: 15
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bit_size: 1
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enum: TCRCINI
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- name: IOLOCK
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description: Locking the AF configuration of associated IOs
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bit_offset: 16
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bit_size: 1
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fieldset/CR2:
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description: control register 2
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fields:
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- name: TSIZE
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description: Number of data at current transfer
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bit_offset: 0
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bit_size: 16
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fieldset/CRCPOLY:
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description: Polynomial Register
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fields:
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- name: CRCPOLY
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description: CRC polynomial register
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bit_offset: 0
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bit_size: 32
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fieldset/IER:
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description: Interrupt Enable Register
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fields:
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- name: RXPIE
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description: RXP Interrupt Enable
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bit_offset: 0
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bit_size: 1
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- name: TXPIE
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description: TXP interrupt enable
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bit_offset: 1
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bit_size: 1
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- name: DXPIE
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description: DXP interrupt enabled
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bit_offset: 2
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bit_size: 1
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- name: EOTIE
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description: "EOT, SUSP and TXC interrupt enable"
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bit_offset: 3
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bit_size: 1
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- name: TXTFIE
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description: TXTFIE interrupt enable
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bit_offset: 4
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bit_size: 1
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- name: UDRIE
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description: UDR interrupt enable
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bit_offset: 5
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bit_size: 1
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- name: OVRIE
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description: OVR interrupt enable
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bit_offset: 6
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bit_size: 1
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- name: CRCEIE
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description: CRC Interrupt enable
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bit_offset: 7
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bit_size: 1
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- name: TIFREIE
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description: TIFRE interrupt enable
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bit_offset: 8
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bit_size: 1
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- name: MODFIE
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description: Mode Fault interrupt enable
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bit_offset: 9
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bit_size: 1
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fieldset/IFCR:
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description: Interrupt/Status Flags Clear Register
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fields:
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- name: EOTC
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description: End Of Transfer flag clear
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bit_offset: 3
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bit_size: 1
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- name: TXTFC
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description: Transmission Transfer Filled flag clear
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bit_offset: 4
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bit_size: 1
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- name: UDRC
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description: Underrun flag clear
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bit_offset: 5
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bit_size: 1
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- name: OVRC
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description: Overrun flag clear
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bit_offset: 6
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bit_size: 1
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- name: CRCEC
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description: CRC Error flag clear
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bit_offset: 7
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bit_size: 1
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- name: TIFREC
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description: TI frame format error flag clear
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bit_offset: 8
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bit_size: 1
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- name: MODFC
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description: Mode Fault flag clear
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bit_offset: 9
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bit_size: 1
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- name: SUSPC
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description: SUSPend flag clear
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bit_offset: 11
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bit_size: 1
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fieldset/RXCRC:
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description: Receiver CRC Register
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fields:
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- name: RXCRC
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description: CRC register for receiver
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bit_offset: 0
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bit_size: 32
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fieldset/RXDR:
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description: Receive Data Register
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fields:
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- name: RXDR
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description: Receive data register
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bit_offset: 0
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bit_size: 32
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fieldset/SR:
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description: Status Register
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fields:
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- name: RXP
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description: Rx-Packet available
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bit_offset: 0
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bit_size: 1
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- name: TXP
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description: Tx-Packet space available
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bit_offset: 1
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bit_size: 1
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- name: DXP
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description: Duplex Packet
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bit_offset: 2
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bit_size: 1
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- name: EOT
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description: End Of Transfer
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bit_offset: 3
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bit_size: 1
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- name: TXTF
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description: Transmission Transfer Filled
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bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
- name: UDR
|
||||||
|
description: Underrun at slave transmission mode
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
- name: OVR
|
||||||
|
description: Overrun
|
||||||
|
bit_offset: 6
|
||||||
|
bit_size: 1
|
||||||
|
- name: CRCE
|
||||||
|
description: CRC Error
|
||||||
|
bit_offset: 7
|
||||||
|
bit_size: 1
|
||||||
|
- name: TIFRE
|
||||||
|
description: TI frame format error
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
- name: MODF
|
||||||
|
description: Mode Fault
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
- name: SUSP
|
||||||
|
description: SUSPend
|
||||||
|
bit_offset: 11
|
||||||
|
bit_size: 1
|
||||||
|
- name: TXC
|
||||||
|
description: TxFIFO transmission complete
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 1
|
||||||
|
- name: RXPLVL
|
||||||
|
description: RxFIFO Packing LeVeL
|
||||||
|
bit_offset: 13
|
||||||
|
bit_size: 2
|
||||||
|
enum: RXPLVL
|
||||||
|
- name: RXWNE
|
||||||
|
description: RxFIFO Word Not Empty
|
||||||
|
bit_offset: 15
|
||||||
|
bit_size: 1
|
||||||
|
enum: RXWNE
|
||||||
|
- name: CTSIZE
|
||||||
|
description: Number of data frames remaining in current TSIZE session
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 16
|
||||||
|
fieldset/TXCRC:
|
||||||
|
description: Transmitter CRC Register
|
||||||
|
fields:
|
||||||
|
- name: TXCRC
|
||||||
|
description: CRC register for transmitter
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/TXDR:
|
||||||
|
description: Transmit Data Register
|
||||||
|
fields:
|
||||||
|
- name: TXDR
|
||||||
|
description: Transmit data register
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/UDRDR:
|
||||||
|
description: Underrun Data Register
|
||||||
|
fields:
|
||||||
|
- name: UDRDR
|
||||||
|
description: Data at slave underrun condition
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
enum/AFCNTR:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: NotControlled
|
||||||
|
description: Peripheral takes no control of GPIOs while disabled
|
||||||
|
value: 0
|
||||||
|
- name: Controlled
|
||||||
|
description: Peripheral controls GPIOs while disabled
|
||||||
|
value: 1
|
||||||
|
enum/COMM:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: FullDuplex
|
||||||
|
description: Full duplex
|
||||||
|
value: 0
|
||||||
|
- name: Transmitter
|
||||||
|
description: Simplex transmitter only
|
||||||
|
value: 1
|
||||||
|
- name: Receiver
|
||||||
|
description: Simplex receiver only
|
||||||
|
value: 2
|
||||||
|
- name: HalfDuplex
|
||||||
|
description: Half duplex
|
||||||
|
value: 3
|
||||||
|
enum/CPHA:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: FirstEdge
|
||||||
|
description: The first clock transition is the first data capture edge
|
||||||
|
value: 0
|
||||||
|
- name: SecondEdge
|
||||||
|
description: The second clock transition is the first data capture edge
|
||||||
|
value: 1
|
||||||
|
enum/CPOL:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: IdleLow
|
||||||
|
description: CK to 0 when idle
|
||||||
|
value: 0
|
||||||
|
- name: IdleHigh
|
||||||
|
description: CK to 1 when idle
|
||||||
|
value: 1
|
||||||
|
enum/CRC_:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Disabled
|
||||||
|
description: Full size (33/17 bit) CRC polynomial is not used
|
||||||
|
value: 0
|
||||||
|
- name: Enabled
|
||||||
|
description: Full size (33/17 bit) CRC polynomial is used
|
||||||
|
value: 1
|
||||||
|
enum/DATFMT:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: RightAligned
|
||||||
|
description: The data inside RXDR and TXDR are right aligned
|
||||||
|
value: 0
|
||||||
|
- name: LeftAligned
|
||||||
|
description: The data inside RXDR and TXDR are left aligned
|
||||||
|
value: 1
|
||||||
|
enum/DATLEN:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: Bits16
|
||||||
|
description: 16 bit data length
|
||||||
|
value: 0
|
||||||
|
- name: Bits24
|
||||||
|
description: 24 bit data length
|
||||||
|
value: 1
|
||||||
|
- name: Bits32
|
||||||
|
description: 32 bit data length
|
||||||
|
value: 2
|
||||||
|
enum/FTHLV:
|
||||||
|
bit_size: 4
|
||||||
|
variants:
|
||||||
|
- name: OneFrame
|
||||||
|
description: 1 frame
|
||||||
|
value: 0
|
||||||
|
- name: TwoFrames
|
||||||
|
description: 2 frames
|
||||||
|
value: 1
|
||||||
|
- name: ThreeFrames
|
||||||
|
description: 3 frames
|
||||||
|
value: 2
|
||||||
|
- name: FourFrames
|
||||||
|
description: 4 frames
|
||||||
|
value: 3
|
||||||
|
- name: FiveFrames
|
||||||
|
description: 5 frames
|
||||||
|
value: 4
|
||||||
|
- name: SixFrames
|
||||||
|
description: 6 frames
|
||||||
|
value: 5
|
||||||
|
- name: SevenFrames
|
||||||
|
description: 7 frames
|
||||||
|
value: 6
|
||||||
|
- name: EightFrames
|
||||||
|
description: 8 frames
|
||||||
|
value: 7
|
||||||
|
- name: NineFrames
|
||||||
|
description: 9 frames
|
||||||
|
value: 8
|
||||||
|
- name: TenFrames
|
||||||
|
description: 10 frames
|
||||||
|
value: 9
|
||||||
|
- name: ElevenFrames
|
||||||
|
description: 11 frames
|
||||||
|
value: 10
|
||||||
|
- name: TwelveFrames
|
||||||
|
description: 12 frames
|
||||||
|
value: 11
|
||||||
|
- name: ThirteenFrames
|
||||||
|
description: 13 frames
|
||||||
|
value: 12
|
||||||
|
- name: FourteenFrames
|
||||||
|
description: 14 frames
|
||||||
|
value: 13
|
||||||
|
- name: FifteenFrames
|
||||||
|
description: 15 frames
|
||||||
|
value: 14
|
||||||
|
- name: SixteenFrames
|
||||||
|
description: 16 frames
|
||||||
|
value: 15
|
||||||
|
enum/HDDIR:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Receiver
|
||||||
|
description: Receiver in half duplex mode
|
||||||
|
value: 0
|
||||||
|
- name: Transmitter
|
||||||
|
description: Transmitter in half duplex mode
|
||||||
|
value: 1
|
||||||
|
enum/LSBFIRST:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: MSBFirst
|
||||||
|
description: Data is transmitted/received with the MSB first
|
||||||
|
value: 0
|
||||||
|
- name: LSBFirst
|
||||||
|
description: Data is transmitted/received with the LSB first
|
||||||
|
value: 1
|
||||||
|
enum/MASTER:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Slave
|
||||||
|
description: Slave configuration
|
||||||
|
value: 0
|
||||||
|
- name: Master
|
||||||
|
description: Master configuration
|
||||||
|
value: 1
|
||||||
|
enum/MBR:
|
||||||
|
bit_size: 3
|
||||||
|
variants:
|
||||||
|
- name: Div2
|
||||||
|
description: f_spi_ker_ck / 2
|
||||||
|
value: 0
|
||||||
|
- name: Div4
|
||||||
|
description: f_spi_ker_ck / 4
|
||||||
|
value: 1
|
||||||
|
- name: Div8
|
||||||
|
description: f_spi_ker_ck / 8
|
||||||
|
value: 2
|
||||||
|
- name: Div16
|
||||||
|
description: f_spi_ker_ck / 16
|
||||||
|
value: 3
|
||||||
|
- name: Div32
|
||||||
|
description: f_spi_ker_ck / 32
|
||||||
|
value: 4
|
||||||
|
- name: Div64
|
||||||
|
description: f_spi_ker_ck / 64
|
||||||
|
value: 5
|
||||||
|
- name: Div128
|
||||||
|
description: f_spi_ker_ck / 128
|
||||||
|
value: 6
|
||||||
|
- name: Div256
|
||||||
|
description: f_spi_ker_ck / 256
|
||||||
|
value: 7
|
||||||
|
enum/RCRCINI:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: AllZeros
|
||||||
|
description: All zeros RX CRC initialization pattern
|
||||||
|
value: 0
|
||||||
|
- name: AllOnes
|
||||||
|
description: All ones RX CRC initialization pattern
|
||||||
|
value: 1
|
||||||
|
enum/RDIOM:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: PermanentlyActive
|
||||||
|
description: RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect)
|
||||||
|
value: 0
|
||||||
|
- name: FromInput
|
||||||
|
description: RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect)
|
||||||
|
value: 1
|
||||||
|
enum/RDIOP:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: ReadyHigh
|
||||||
|
description: high level of the signal means the slave is ready for communication
|
||||||
|
value: 0
|
||||||
|
- name: ReadyLow
|
||||||
|
description: low level of the signal means the slave is ready for communication
|
||||||
|
value: 1
|
||||||
|
enum/RXPLVL:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: ZeroFrames
|
||||||
|
description: Zero frames beyond packing ratio available
|
||||||
|
value: 0
|
||||||
|
- name: OneFrame
|
||||||
|
description: One frame beyond packing ratio available
|
||||||
|
value: 1
|
||||||
|
- name: TwoFrames
|
||||||
|
description: Two frame beyond packing ratio available
|
||||||
|
value: 2
|
||||||
|
- name: ThreeFrames
|
||||||
|
description: Three frame beyond packing ratio available
|
||||||
|
value: 3
|
||||||
|
enum/RXWNE:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: LessThan32
|
||||||
|
description: Less than 32-bit data frame received
|
||||||
|
value: 0
|
||||||
|
- name: AtLeast32
|
||||||
|
description: At least 32-bit data frame received
|
||||||
|
value: 1
|
||||||
|
enum/SP:
|
||||||
|
bit_size: 3
|
||||||
|
variants:
|
||||||
|
- name: Motorola
|
||||||
|
description: Motorola SPI protocol
|
||||||
|
value: 0
|
||||||
|
- name: TI
|
||||||
|
description: TI SPI protocol
|
||||||
|
value: 1
|
||||||
|
enum/SSIOP:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: ActiveLow
|
||||||
|
description: Low level is active for SS signal
|
||||||
|
value: 0
|
||||||
|
- name: ActiveHigh
|
||||||
|
description: High level is active for SS signal
|
||||||
|
value: 1
|
||||||
|
enum/SSOM:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Asserted
|
||||||
|
description: SS is asserted until data transfer complete
|
||||||
|
value: 0
|
||||||
|
- name: NotAsserted
|
||||||
|
description: Data frames interleaved with SS not asserted during MIDI
|
||||||
|
value: 1
|
||||||
|
enum/TCRCINI:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: AllZeros
|
||||||
|
description: All zeros TX CRC initialization pattern
|
||||||
|
value: 0
|
||||||
|
- name: AllOnes
|
||||||
|
description: All ones TX CRC initialization pattern
|
||||||
|
value: 1
|
||||||
|
enum/TRIGPOL:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: RisingEdge
|
||||||
|
description: trigger is active on raising edge
|
||||||
|
value: 0
|
||||||
|
- name: FallingEdge
|
||||||
|
description: trigger is active on falling edge
|
||||||
|
value: 1
|
||||||
|
enum/UDRCFG:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: Constant
|
||||||
|
description: Slave sends a constant underrun pattern
|
||||||
|
value: 0
|
||||||
|
- name: RepeatReceived
|
||||||
|
description: Slave repeats last received data frame from master
|
||||||
|
value: 1
|
||||||
|
- name: RepeatTransmitted
|
||||||
|
description: Slave repeats last transmitted data frame
|
||||||
|
value: 2
|
||||||
@ -145,7 +145,8 @@ impl PeriMatcher {
|
|||||||
(".*:SPI:spi2s1_v3_1", ("spi", "v2", "SPI")),
|
(".*:SPI:spi2s1_v3_1", ("spi", "v2", "SPI")),
|
||||||
(".*:SPI:spi2s2_v1_1", ("spi", "v3", "SPI")),
|
(".*:SPI:spi2s2_v1_1", ("spi", "v3", "SPI")),
|
||||||
(".*:SPI:spi2s2_v1_0", ("spi", "v3", "SPI")),
|
(".*:SPI:spi2s2_v1_0", ("spi", "v3", "SPI")),
|
||||||
(".*:SPI:spi2s3_v1_1", ("spi", "v4", "SPI")),
|
(".*:SPI:spi2s3_v2_1", ("spi", "v4", "SPI")),
|
||||||
|
(".*:SPI:spi2s3_v1_1", ("spi", "v5", "SPI")),
|
||||||
(".*:I2C:i2c1_v1_5", ("i2c", "v1", "I2C")),
|
(".*:I2C:i2c1_v1_5", ("i2c", "v1", "I2C")),
|
||||||
(".*:I2C:i2c2_v1_1", ("i2c", "v2", "I2C")),
|
(".*:I2C:i2c2_v1_1", ("i2c", "v2", "I2C")),
|
||||||
(".*:I2C:i2c2_v1_1F7", ("i2c", "v2", "I2C")),
|
(".*:I2C:i2c2_v1_1F7", ("i2c", "v2", "I2C")),
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user