Merge pull request #198 from kevswims/feature/stm32g-crs

Feature/stm32g crs

data/registers/crs_v1.yaml

@@ -38,6 +38,7 @@ fieldset/CFGR:
       description: SYNC signal source selection
       bit_offset: 28
       bit_size: 2
+      enum: SYNCSRC
     - name: SYNCPOL
       description: SYNC polarity selection
       bit_offset: 31
@@ -135,3 +136,42 @@ fieldset/ISR:
       description: Frequency error capture
       bit_offset: 16
       bit_size: 16
+enum/SYNCSRC:
+  bit_size: 2
+  variants:
+    - name: GPIO
+      description: GPIO selected as SYNC signal source
+      value: 0
+    - name: LSE
+      description: LSE selected as SYNC signal source
+      value: 1
+    - name: USB
+      description: USB SOF selected as SYNC signal source
+      value: 2
+enum/SYNCDIV:
+  bit_size: 3
+  variants:
+    - name: DIV1
+      description: f(SYNCDIV) = f(SYNCSRC)
+      value: 0
+    - name: DIV2
+      description: f(SYNCDIV) = f(SYNCSRC)/2
+      value: 1
+    - name: DIV4
+      description: f(SYNCDIV) = f(SYNCSRC)/4
+      value: 2
+    - name: DIV8
+      description: f(SYNCDIV) = f(SYNCSRC)/8
+      value: 3
+    - name: DIV16
+      description: f(SYNCDIV) = f(SYNCSRC)/16
+      value: 4
+    - name: DIV32
+      description: f(SYNCDIV) = f(SYNCSRC)/32
+      value: 5
+    - name: DIV64
+      description: f(SYNCDIV) = f(SYNCSRC)/64
+      value: 6
+    - name: DIV128
+      description: f(SYNCDIV) = f(SYNCSRC)/128
+      value: 7

data/registers/rcc_g4.yaml

@@ -1022,6 +1022,7 @@ fieldset/CCIPR:
       description: 48 MHz clock source selection
       bit_offset: 26
       bit_size: 2
+      enum: CLK48SEL
     - name: ADC12SEL
       description: ADCs clock source selection
       bit_offset: 28
@@ -1479,3 +1480,12 @@ enum/SW:
     - name: PLLRCLK
       description: PLLRCLK selected as system clock
       value: 3
+enum/CLK48SEL:
+  bit_size: 2
+  variants:
+    - name: HSI48
+      description: HSI48 oscillator clock selected as 48 MHz clock
+      value: 0
+    - name: PLLQCLK
+      description: PLLQCLK selected as 48 MHz clock
+      value: 2

stm32-data-gen/src/chips.rs

@@ -284,7 +284,10 @@ impl PeriMatcher {
             ("STM32H50.*:EXTI:.*", ("exti", "h50", "EXTI")),
             ("STM32H5.*:EXTI:.*", ("exti", "h5", "EXTI")),
             (".*:EXTI:.*", ("exti", "v1", "EXTI")),
-            ("STM32L0.*:CRS:.*", ("crs", "l0", "CRS")),
+            ("STM32L0.*:CRS:.*", ("crs", "v1", "CRS")),
+            ("STM32G0B1.*:CRS:.*", ("crs", "v1", "CRS")),
+            ("STM32G0C1.*:CRS:.*", ("crs", "v1", "CRS")),
+            ("STM32G4.*:CRS:.*", ("crs", "v1", "CRS")),
             (".*SDMMC:sdmmc2_v1_0", ("sdmmc", "v2", "SDMMC")),
             ("STM32C0.*:PWR:.*", ("pwr", "c0", "PWR")),
             ("STM32G0.*:PWR:.*", ("pwr", "g0", "PWR")),