diff --git a/data/registers/crs_l0.yaml b/data/registers/crs_l0.yaml new file mode 100644 index 0000000..1fd7204 --- /dev/null +++ b/data/registers/crs_l0.yaml @@ -0,0 +1,137 @@ +--- +block/CRS: + description: Clock recovery system + items: + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: CFGR + description: configuration register + byte_offset: 4 + fieldset: CFGR + - name: ISR + description: interrupt and status register + byte_offset: 8 + access: Read + fieldset: ISR + - name: ICR + description: interrupt flag clear register + byte_offset: 12 + fieldset: ICR +fieldset/CFGR: + description: configuration register + fields: + - name: RELOAD + description: Counter reload value + bit_offset: 0 + bit_size: 16 + - name: FELIM + description: Frequency error limit + bit_offset: 16 + bit_size: 8 + - name: SYNCDIV + description: SYNC divider + bit_offset: 24 + bit_size: 3 + - name: SYNCSRC + description: SYNC signal source selection + bit_offset: 28 + bit_size: 2 + - name: SYNCPOL + description: SYNC polarity selection + bit_offset: 31 + bit_size: 1 +fieldset/CR: + description: control register + fields: + - name: SYNCOKIE + description: SYNC event OK interrupt enable + bit_offset: 0 + bit_size: 1 + - name: SYNCWARNIE + description: SYNC warning interrupt enable + bit_offset: 1 + bit_size: 1 + - name: ERRIE + description: Synchronization or trimming error interrupt enable + bit_offset: 2 + bit_size: 1 + - name: ESYNCIE + description: Expected SYNC interrupt enable + bit_offset: 3 + bit_size: 1 + - name: CEN + description: Frequency error counter enable + bit_offset: 5 + bit_size: 1 + - name: AUTOTRIMEN + description: Automatic trimming enable + bit_offset: 6 + bit_size: 1 + - name: SWSYNC + description: Generate software SYNC event + bit_offset: 7 + bit_size: 1 + - name: TRIM + description: HSI48 oscillator smooth trimming + bit_offset: 8 + bit_size: 6 +fieldset/ICR: + description: interrupt flag clear register + fields: + - name: SYNCOKC + description: SYNC event OK clear flag + bit_offset: 0 + bit_size: 1 + - name: SYNCWARNC + description: SYNC warning clear flag + bit_offset: 1 + bit_size: 1 + - name: ERRC + description: Error clear flag + bit_offset: 2 + bit_size: 1 + - name: ESYNCC + description: Expected SYNC clear flag + bit_offset: 3 + bit_size: 1 +fieldset/ISR: + description: interrupt and status register + fields: + - name: SYNCOKF + description: SYNC event OK flag + bit_offset: 0 + bit_size: 1 + - name: SYNCWARNF + description: SYNC warning flag + bit_offset: 1 + bit_size: 1 + - name: ERRF + description: Error flag + bit_offset: 2 + bit_size: 1 + - name: ESYNCF + description: Expected SYNC flag + bit_offset: 3 + bit_size: 1 + - name: SYNCERR + description: SYNC error + bit_offset: 8 + bit_size: 1 + - name: SYNCMISS + description: SYNC missed + bit_offset: 9 + bit_size: 1 + - name: TRIMOVF + description: Trimming overflow or underflow + bit_offset: 10 + bit_size: 1 + - name: FEDIR + description: Frequency error direction + bit_offset: 15 + bit_size: 1 + - name: FECAP + description: Frequency error capture + bit_offset: 16 + bit_size: 16 diff --git a/data/registers/dbg_l0.yaml b/data/registers/dbg_l0.yaml new file mode 100644 index 0000000..5fab49f --- /dev/null +++ b/data/registers/dbg_l0.yaml @@ -0,0 +1,186 @@ +--- +block/DBG: + description: Debug support + items: + - name: IDCODE + description: MCU Device ID Code Register + byte_offset: 0 + access: Read + fieldset: IDCODE + - name: CR + description: Debug MCU Configuration Register + byte_offset: 4 + fieldset: CR + - name: APB1_FZ + description: APB Low Freeze Register + byte_offset: 8 + fieldset: APB1_FZ + - name: APB2_FZ + description: APB High Freeze Register + byte_offset: 12 + fieldset: APB2_FZ +fieldset/APB1_FZ: + description: APB Low Freeze Register + fields: + - name: DBG_TIMER2_STOP + description: Debug Timer 2 stopped when Core is halted + bit_offset: 0 + bit_size: 1 + enum: DBG_TIMER_STOP + - name: DBG_TIMER6_STOP + description: Debug Timer 6 stopped when Core is halted + bit_offset: 4 + bit_size: 1 + enum: DBG_TIMER_STOP + - name: DBG_RTC_STOP + description: Debug RTC stopped when Core is halted + bit_offset: 10 + bit_size: 1 + enum: DBG_RTC_STOP + - name: DBG_WWDG_STOP + description: Debug Window Wachdog stopped when Core is halted + bit_offset: 11 + bit_size: 1 + enum: DBG_WWDG_STOP + - name: DBG_IWDG_STOP + description: Debug Independent Wachdog stopped when Core is halted + bit_offset: 12 + bit_size: 1 + enum: DBG_IWDG_STOP + - name: DBG_I2C1_STOP + description: I2C1 SMBUS timeout mode stopped when core is halted + bit_offset: 21 + bit_size: 1 + enum: DBG_IC_STOP + - name: DBG_I2C2_STOP + description: I2C2 SMBUS timeout mode stopped when core is halted + bit_offset: 22 + bit_size: 1 + enum: DBG_IC_STOP + - name: DBG_LPTIMER_STOP + description: LPTIM1 counter stopped when core is halted + bit_offset: 31 + bit_size: 1 + enum: DBG_LPTIMER_STOP +fieldset/APB2_FZ: + description: APB High Freeze Register + fields: + - name: DBG_TIMER21_STOP + description: Debug Timer 21 stopped when Core is halted + bit_offset: 2 + bit_size: 1 + enum: DBG_TIMER_STOP + - name: DBG_TIMER22_STO + description: Debug Timer 22 stopped when Core is halted + bit_offset: 6 + bit_size: 1 +fieldset/CR: + description: Debug MCU Configuration Register + fields: + - name: DBG_SLEEP + description: Debug Sleep Mode + bit_offset: 0 + bit_size: 1 + enum: DBG_SLEEP + - name: DBG_STOP + description: Debug Stop Mode + bit_offset: 1 + bit_size: 1 + enum: DBG_STOP + - name: DBG_STANDBY + description: Debug Standby Mode + bit_offset: 2 + bit_size: 1 + enum: DBG_STANDBY +fieldset/IDCODE: + description: MCU Device ID Code Register + fields: + - name: DEV_ID + description: Device Identifier + bit_offset: 0 + bit_size: 12 + - name: REV_ID + description: Revision Identifier + bit_offset: 16 + bit_size: 16 +enum/DBG_IC_STOP: + bit_size: 1 + variants: + - name: NormalMode + description: Same behavior as in normal mode + value: 0 + - name: SMBusTimeoutFrozen + description: I2C3 SMBUS timeout is frozen + value: 1 +enum/DBG_IWDG_STOP: + bit_size: 1 + variants: + - name: Continue + description: The independent watchdog counter clock continues even if the core is halted + value: 0 + - name: Stop + description: The independent watchdog counter clock is stopped when the core is halted + value: 1 +enum/DBG_LPTIMER_STOP: + bit_size: 1 + variants: + - name: Continue + description: LPTIM1 counter clock is fed even if the core is halted + value: 0 + - name: Stop + description: LPTIM1 counter clock is stopped when the core is halted + value: 1 +enum/DBG_RTC_STOP: + bit_size: 1 + variants: + - name: Continue + description: The clock of the RTC counter is fed even if the core is halted + value: 0 + - name: Stop + description: The clock of the RTC counter is stopped when the core is halted + value: 1 +enum/DBG_SLEEP: + bit_size: 1 + variants: + - name: Disabled + description: Debug Sleep Mode Disabled + value: 0 + - name: Enabled + description: Debug Sleep Mode Enabled + value: 1 +enum/DBG_STANDBY: + bit_size: 1 + variants: + - name: Disabled + description: Debug Standby Mode Disabled + value: 0 + - name: Enabled + description: Debug Standby Mode Enabled + value: 1 +enum/DBG_STOP: + bit_size: 1 + variants: + - name: Disabled + description: Debug Stop Mode Disabled + value: 0 + - name: Enabled + description: Debug Stop Mode Enabled + value: 1 +enum/DBG_TIMER_STOP: + bit_size: 1 + variants: + - name: Continue + description: The counter clock of TIMx is fed even if the core is halted + value: 0 + - name: Stop + description: The counter clock of TIMx is stopped when the core is halted + value: 1 +enum/DBG_WWDG_STOP: + bit_size: 1 + variants: + - name: Continue + description: The window watchdog counter clock continues even if the core is halted + value: 0 + - name: Stop + description: The window watchdog counter clock is stopped when the core is halted + value: 1 diff --git a/parse.py b/parse.py index b5ae916..66f54e4 100644 --- a/parse.py +++ b/parse.py @@ -239,6 +239,8 @@ perimap = [ ('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'), ('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'), ('STM32L0.*:RCC:.*', 'rcc_l0/RCC'), + ('.*:STM32L0_dbgmcu_v1_0', 'dbg_l0/DBG'), + ('.*:STM32L0_crs_v1_0', 'crs_l0/CRS'), ('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'), ('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'), ('.*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'), @@ -447,6 +449,16 @@ def parse_chips(): dbg_peri['block'] = block peris['DBGMCU'] = dbg_peri + # CRS is not in the cubedb XMLs + if addr := h['defines'].get('CRS_BASE'): + kind = 'CRS:' + chip_name[:7] + '_crs_v1_0' + crs_peri = OrderedDict({ + 'address': addr, + 'kind': kind, + }) + if block := match_peri(kind): + crs_peri['block'] = block + peris['CRS'] = crs_peri chip['peripherals'] = peris with open('data/chips/'+chip_name+'.yaml', 'w') as f: