From 23fed4339b265dfd240c4f9945b80f2f8ee8bbfc Mon Sep 17 00:00:00 2001 From: Bob McWhirter Date: Wed, 9 Jun 2021 09:52:35 -0400 Subject: [PATCH] ADC v3 attempt #2. --- data/registers/adc_common_v3.yaml | 155 ++++++++ data/registers/adc_v3.yaml | 630 ++++++++++++++++++++++++++++++ parse.py | 1 + 3 files changed, 786 insertions(+) create mode 100644 data/registers/adc_common_v3.yaml create mode 100644 data/registers/adc_v3.yaml diff --git a/data/registers/adc_common_v3.yaml b/data/registers/adc_common_v3.yaml new file mode 100644 index 0000000..6522661 --- /dev/null +++ b/data/registers/adc_common_v3.yaml @@ -0,0 +1,155 @@ +--- +block/ADC_Common: + description: Analog-to-Digital Converter + items: + - name: CSR + description: ADC Common status register + byte_offset: 0 + access: Read + fieldset: CSR + - name: CCR + description: ADC common control register + byte_offset: 8 + fieldset: CCR + - name: CDR + description: ADC common regular data register for dual and triple modes + byte_offset: 12 + access: Read + fieldset: CDR +fieldset/CCR: + description: ADC common control register + fields: + - name: MULT + description: Multi ADC mode selection + bit_offset: 0 + bit_size: 5 + - name: DELAY + description: Delay between 2 sampling phases + bit_offset: 8 + bit_size: 4 + - name: DMACFG + description: DMA configuration (for multi-ADC mode) + bit_offset: 13 + bit_size: 1 + - name: MDMA + description: Direct memory access mode for multi ADC mode + bit_offset: 14 + bit_size: 2 + - name: CKMODE + description: ADC clock mode + bit_offset: 16 + bit_size: 2 + - name: VREFEN + description: VREFINT enable + bit_offset: 22 + bit_size: 1 + - name: CH18SEL + description: CH18 selection (Vbat) + bit_offset: 23 + bit_size: 1 + - name: CH17SEL + description: CH17 selection (temperature) + bit_offset: 24 + bit_size: 1 +fieldset/CDR: + description: ADC common regular data register for dual and triple modes + fields: + - name: RDATA_MST + description: Regular data of the master ADC + bit_offset: 0 + bit_size: 16 + - name: RDATA_SLV + description: Regular data of the slave ADC + bit_offset: 16 + bit_size: 16 +fieldset/CSR: + description: ADC Common status register + fields: + - name: ADDRDY_MST + description: ADDRDY_MST + bit_offset: 0 + bit_size: 1 + - name: EOSMP_MST + description: EOSMP_MST + bit_offset: 1 + bit_size: 1 + - name: EOC_MST + description: EOC_MST + bit_offset: 2 + bit_size: 1 + - name: EOS_MST + description: EOS_MST + bit_offset: 3 + bit_size: 1 + - name: OVR_MST + description: OVR_MST + bit_offset: 4 + bit_size: 1 + - name: JEOC_MST + description: JEOC_MST + bit_offset: 5 + bit_size: 1 + - name: JEOS_MST + description: JEOS_MST + bit_offset: 6 + bit_size: 1 + - name: AWD1_MST + description: AWD1_MST + bit_offset: 7 + bit_size: 1 + - name: AWD2_MST + description: AWD2_MST + bit_offset: 8 + bit_size: 1 + - name: AWD3_MST + description: AWD3_MST + bit_offset: 9 + bit_size: 1 + - name: JQOVF_MST + description: JQOVF_MST + bit_offset: 10 + bit_size: 1 + - name: ADRDY_SLV + description: ADRDY_SLV + bit_offset: 16 + bit_size: 1 + - name: EOSMP_SLV + description: EOSMP_SLV + bit_offset: 17 + bit_size: 1 + - name: EOC_SLV + description: End of regular conversion of the slave ADC + bit_offset: 18 + bit_size: 1 + - name: EOS_SLV + description: End of regular sequence flag of the slave ADC + bit_offset: 19 + bit_size: 1 + - name: OVR_SLV + description: Overrun flag of the slave ADC + bit_offset: 20 + bit_size: 1 + - name: JEOC_SLV + description: End of injected conversion flag of the slave ADC + bit_offset: 21 + bit_size: 1 + - name: JEOS_SLV + description: End of injected sequence flag of the slave ADC + bit_offset: 22 + bit_size: 1 + - name: AWD1_SLV + description: Analog watchdog 1 flag of the slave ADC + bit_offset: 23 + bit_size: 1 + - name: AWD2_SLV + description: Analog watchdog 2 flag of the slave ADC + bit_offset: 24 + bit_size: 1 + - name: AWD3_SLV + description: Analog watchdog 3 flag of the slave ADC + bit_offset: 25 + bit_size: 1 + - name: JQOVF_SLV + description: Injected Context Queue Overflow flag of the slave ADC + bit_offset: 26 + bit_size: 1 diff --git a/data/registers/adc_v3.yaml b/data/registers/adc_v3.yaml new file mode 100644 index 0000000..df59eba --- /dev/null +++ b/data/registers/adc_v3.yaml @@ -0,0 +1,630 @@ +--- +block/ADC: + description: Analog-to-Digital Converter + items: + - name: ISR + description: interrupt and status register + byte_offset: 0 + fieldset: ISR + - name: IER + description: interrupt enable register + byte_offset: 4 + fieldset: IER + - name: CR + description: control register + byte_offset: 8 + fieldset: CR + - name: CFGR + description: configuration register + byte_offset: 12 + fieldset: CFGR + - name: CFGR2 + description: configuration register + byte_offset: 16 + fieldset: CFGR2 + - name: SMPR1 + description: sample time register 1 + byte_offset: 20 + fieldset: SMPR1 + - name: SMPR2 + description: sample time register 2 + byte_offset: 24 + fieldset: SMPR2 + - name: TR1 + description: watchdog threshold register 1 + byte_offset: 32 + fieldset: TR1 + - name: TR2 + description: watchdog threshold register + byte_offset: 36 + fieldset: TR2 + - name: TR3 + description: watchdog threshold register 3 + byte_offset: 40 + fieldset: TR3 + - name: SQR1 + description: regular sequence register 1 + byte_offset: 48 + fieldset: SQR1 + - name: SQR2 + description: regular sequence register 2 + byte_offset: 52 + fieldset: SQR2 + - name: SQR3 + description: regular sequence register 3 + byte_offset: 56 + fieldset: SQR3 + - name: SQR4 + description: regular sequence register 4 + byte_offset: 60 + fieldset: SQR4 + - name: DR + description: regular Data Register + byte_offset: 64 + access: Read + fieldset: DR + - name: JSQR + description: injected sequence register + byte_offset: 76 + fieldset: JSQR + - name: OFR + description: offset register 1 + array: + len: 4 + stride: 4 + byte_offset: 96 + fieldset: OFR1 + - name: JDR + description: injected data register 1 + array: + len: 4 + stride: 4 + byte_offset: 128 + access: Read + fieldset: JDR1 + - name: AWD2CR + description: Analog Watchdog 2 Configuration Register + byte_offset: 160 + fieldset: AWD2CR + - name: AWD3CR + description: Analog Watchdog 3 Configuration Register + byte_offset: 164 + fieldset: AWD3CR + - name: DIFSEL + description: Differential Mode Selection Register 2 + byte_offset: 176 + fieldset: DIFSEL + - name: CALFACT + description: Calibration Factors + byte_offset: 180 + fieldset: CALFACT +fieldset/AWD2CR: + description: Analog Watchdog 2 Configuration Register + fields: + - name: AWD2CH + description: AWD2CH + bit_offset: 1 + bit_size: 18 +fieldset/AWD3CR: + description: Analog Watchdog 3 Configuration Register + fields: + - name: AWD3CH + description: AWD3CH + bit_offset: 1 + bit_size: 18 +fieldset/CALFACT: + description: Calibration Factors + fields: + - name: CALFACT_S + description: CALFACT_S + bit_offset: 0 + bit_size: 7 + - name: CALFACT_D + description: CALFACT_D + bit_offset: 16 + bit_size: 7 +fieldset/CFGR: + description: configuration register + fields: + - name: DMAEN + description: DMAEN + bit_offset: 0 + bit_size: 1 + - name: DMACFG + description: DMACFG + bit_offset: 1 + bit_size: 1 + - name: RES + description: RES + bit_offset: 3 + bit_size: 2 + - name: ALIGN + description: ALIGN + bit_offset: 5 + bit_size: 1 + - name: EXTSEL + description: EXTSEL + bit_offset: 6 + bit_size: 4 + - name: EXTEN + description: EXTEN + bit_offset: 10 + bit_size: 2 + - name: OVRMOD + description: OVRMOD + bit_offset: 12 + bit_size: 1 + - name: CONT + description: CONT + bit_offset: 13 + bit_size: 1 + - name: AUTDLY + description: AUTDLY + bit_offset: 14 + bit_size: 1 + - name: AUTOFF + description: AUTOFF + bit_offset: 15 + bit_size: 1 + - name: DISCEN + description: DISCEN + bit_offset: 16 + bit_size: 1 + - name: DISCNUM + description: DISCNUM + bit_offset: 17 + bit_size: 3 + - name: JDISCEN + description: JDISCEN + bit_offset: 20 + bit_size: 1 + - name: JQM + description: JQM + bit_offset: 21 + bit_size: 1 + - name: AWD1SGL + description: AWD1SGL + bit_offset: 22 + bit_size: 1 + - name: AWD1EN + description: AWD1EN + bit_offset: 23 + bit_size: 1 + - name: JAWD1EN + description: JAWD1EN + bit_offset: 24 + bit_size: 1 + - name: JAUTO + description: JAUTO + bit_offset: 25 + bit_size: 1 + - name: AWDCH1CH + description: AWDCH1CH + bit_offset: 26 + bit_size: 5 +fieldset/CFGR2: + description: configuration register + fields: + - name: ROVSE + description: DMAEN + bit_offset: 0 + bit_size: 1 + - name: JOVSE + description: DMACFG + bit_offset: 1 + bit_size: 1 + - name: OVSR + description: RES + bit_offset: 2 + bit_size: 3 + - name: OVSS + description: ALIGN + bit_offset: 5 + bit_size: 4 + - name: TOVS + description: EXTSEL + bit_offset: 9 + bit_size: 1 + - name: ROVSM + description: EXTEN + bit_offset: 10 + bit_size: 1 +fieldset/CR: + description: control register + fields: + - name: ADEN + description: ADEN + bit_offset: 0 + bit_size: 1 + - name: ADDIS + description: ADDIS + bit_offset: 1 + bit_size: 1 + - name: ADSTART + description: ADSTART + bit_offset: 2 + bit_size: 1 + - name: JADSTART + description: JADSTART + bit_offset: 3 + bit_size: 1 + - name: ADSTP + description: ADSTP + bit_offset: 4 + bit_size: 1 + - name: JADSTP + description: JADSTP + bit_offset: 5 + bit_size: 1 + - name: ADVREGEN + description: ADVREGEN + bit_offset: 28 + bit_size: 1 + - name: DEEPPWD + description: DEEPPWD + bit_offset: 29 + bit_size: 1 + - name: ADCALDIF + description: ADCALDIF + bit_offset: 30 + bit_size: 1 + - name: ADCAL + description: ADCAL + bit_offset: 31 + bit_size: 1 +fieldset/DIFSEL: + description: Differential Mode Selection Register 2 + fields: + - name: DIFSEL_1_15 + description: Differential mode for channels 15 to 1 + bit_offset: 1 + bit_size: 15 + - name: DIFSEL_16_18 + description: Differential mode for channels 18 to 16 + bit_offset: 16 + bit_size: 3 +fieldset/DR: + description: regular Data Register + fields: + - name: regularDATA + description: regularDATA + bit_offset: 0 + bit_size: 16 +fieldset/IER: + description: interrupt enable register + fields: + - name: ADRDYIE + description: ADRDYIE + bit_offset: 0 + bit_size: 1 + - name: EOSMPIE + description: EOSMPIE + bit_offset: 1 + bit_size: 1 + - name: EOCIE + description: EOCIE + bit_offset: 2 + bit_size: 1 + - name: EOSIE + description: EOSIE + bit_offset: 3 + bit_size: 1 + - name: OVRIE + description: OVRIE + bit_offset: 4 + bit_size: 1 + - name: JEOCIE + description: JEOCIE + bit_offset: 5 + bit_size: 1 + - name: JEOSIE + description: JEOSIE + bit_offset: 6 + bit_size: 1 + - name: AWD1IE + description: AWD1IE + bit_offset: 7 + bit_size: 1 + - name: AWD2IE + description: AWD2IE + bit_offset: 8 + bit_size: 1 + - name: AWD3IE + description: AWD3IE + bit_offset: 9 + bit_size: 1 + - name: JQOVFIE + description: JQOVFIE + bit_offset: 10 + bit_size: 1 +fieldset/ISR: + description: interrupt and status register + fields: + - name: ADRDY + description: ADRDY + bit_offset: 0 + bit_size: 1 + - name: EOSMP + description: EOSMP + bit_offset: 1 + bit_size: 1 + - name: EOC + description: EOC + bit_offset: 2 + bit_size: 1 + - name: EOS + description: EOS + bit_offset: 3 + bit_size: 1 + - name: OVR + description: OVR + bit_offset: 4 + bit_size: 1 + - name: JEOC + description: JEOC + bit_offset: 5 + bit_size: 1 + - name: JEOS + description: JEOS + bit_offset: 6 + bit_size: 1 + - name: AWD + description: AWD1 + bit_offset: 7 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: JQOVF + description: JQOVF + bit_offset: 10 + bit_size: 1 +fieldset/JDR1: + description: injected data register 1 + fields: + - name: JDATA + description: JDATA1 + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 +fieldset/JDR2: + description: injected data register 2 + fields: + - name: JDATA + description: JDATA2 + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 +fieldset/JDR3: + description: injected data register 3 + fields: + - name: JDATA + description: JDATA3 + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 +fieldset/JDR4: + description: injected data register 4 + fields: + - name: JDATA + description: JDATA4 + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 +fieldset/JSQR: + description: injected sequence register + fields: + - name: JL + description: JL + bit_offset: 0 + bit_size: 2 + - name: JEXTSEL + description: JEXTSEL + bit_offset: 2 + bit_size: 4 + - name: JEXTEN + description: JEXTEN + bit_offset: 6 + bit_size: 2 + - name: JSQ + description: JSQ1 + bit_offset: 8 + bit_size: 5 + array: + len: 4 + stride: 6 +fieldset/OFR1: + description: offset register 1 + fields: + - name: OFFSET + description: OFFSET1 + bit_offset: 0 + bit_size: 12 + array: + len: 1 + stride: 0 + - name: OFFSET1_CH + description: OFFSET1_CH + bit_offset: 26 + bit_size: 5 + - name: OFFSET1_EN + description: OFFSET1_EN + bit_offset: 31 + bit_size: 1 +fieldset/OFR2: + description: offset register 2 + fields: + - name: OFFSET + description: OFFSET2 + bit_offset: 0 + bit_size: 12 + array: + len: 1 + stride: 0 + - name: OFFSET2_CH + description: OFFSET2_CH + bit_offset: 26 + bit_size: 5 + - name: OFFSET2_EN + description: OFFSET2_EN + bit_offset: 31 + bit_size: 1 +fieldset/OFR3: + description: offset register 3 + fields: + - name: OFFSET + description: OFFSET3 + bit_offset: 0 + bit_size: 12 + array: + len: 1 + stride: 0 + - name: OFFSET3_CH + description: OFFSET3_CH + bit_offset: 26 + bit_size: 5 + - name: OFFSET3_EN + description: OFFSET3_EN + bit_offset: 31 + bit_size: 1 +fieldset/OFR4: + description: offset register 4 + fields: + - name: OFFSET + description: OFFSET4 + bit_offset: 0 + bit_size: 12 + array: + len: 1 + stride: 0 + - name: OFFSET4_CH + description: OFFSET4_CH + bit_offset: 26 + bit_size: 5 + - name: OFFSET4_EN + description: OFFSET4_EN + bit_offset: 31 + bit_size: 1 +fieldset/SMPR1: + description: sample time register 1 + fields: + - name: SMP + description: Channel 0 sampling time selection + bit_offset: 0 + bit_size: 3 + array: + len: 10 + stride: 3 +fieldset/SMPR2: + description: sample time register 2 + fields: + - name: SMP + description: Channel 10 sampling time selection + bit_offset: 0 + bit_size: 3 + array: + len: 9 + stride: 3 +fieldset/SQR1: + description: regular sequence register 1 + fields: + - name: L + description: Regular channel sequence length + bit_offset: 0 + bit_size: 4 + - name: SQ + description: SQ1 + bit_offset: 6 + bit_size: 5 + array: + len: 4 + stride: 6 +fieldset/SQR2: + description: regular sequence register 2 + fields: + - name: SQ + description: SQ5 + bit_offset: 0 + bit_size: 5 + array: + len: 5 + stride: 6 +fieldset/SQR3: + description: regular sequence register 3 + fields: + - name: SQ + description: SQ10 + bit_offset: 0 + bit_size: 5 + array: + len: 5 + stride: 6 +fieldset/SQR4: + description: regular sequence register 4 + fields: + - name: SQ + description: SQ15 + bit_offset: 0 + bit_size: 5 + array: + len: 2 + stride: 6 +fieldset/TR1: + description: watchdog threshold register 1 + fields: + - name: LT + description: LT1 + bit_offset: 0 + bit_size: 12 + array: + len: 1 + stride: 0 + - name: HT + description: HT1 + bit_offset: 16 + bit_size: 12 + array: + len: 1 + stride: 0 +fieldset/TR2: + description: watchdog threshold register + fields: + - name: LT + description: LT2 + bit_offset: 0 + bit_size: 8 + array: + len: 1 + stride: 0 + - name: HT + description: HT2 + bit_offset: 16 + bit_size: 8 + array: + len: 1 + stride: 0 +fieldset/TR3: + description: watchdog threshold register 3 + fields: + - name: LT + description: LT3 + bit_offset: 0 + bit_size: 8 + array: + len: 1 + stride: 0 + - name: HT + description: HT3 + bit_offset: 16 + bit_size: 8 + array: + len: 1 + stride: 0 diff --git a/parse.py b/parse.py index 9014f11..6d03fac 100644 --- a/parse.py +++ b/parse.py @@ -238,6 +238,7 @@ perimap = [ ('.*:I2C:i2c2_v1_1F7', 'i2c_v2/I2C'), ('.*:DAC:dacif_v2_0', 'dac_v2/DAC'), ('.*:DAC:dacif_v3_0', 'dac_v2/DAC'), + ('.*:ADC:aditf5_v2_0', 'adc_v3/ADC'), ('STM32F4.*:SYS:.*', 'syscfg_f4/SYSCFG'), ('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'), ('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),