From 1f8eeeb71b53f28736c889b85c0454d85afc4e61 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Thu, 22 Feb 2024 14:00:19 +0800 Subject: [PATCH] extract and manual bug fix --- data/registers/vrefbuf_v1.yaml | 77 +++++++++++++++++++++++++++++++++ data/registers/vrefbuf_v2a.yaml | 37 ++++++++++++++++ data/registers/vrefbuf_v2b.yaml | 37 ++++++++++++++++ 3 files changed, 151 insertions(+) create mode 100644 data/registers/vrefbuf_v1.yaml create mode 100644 data/registers/vrefbuf_v2a.yaml create mode 100644 data/registers/vrefbuf_v2b.yaml diff --git a/data/registers/vrefbuf_v1.yaml b/data/registers/vrefbuf_v1.yaml new file mode 100644 index 0000000..45db2e4 --- /dev/null +++ b/data/registers/vrefbuf_v1.yaml @@ -0,0 +1,77 @@ +block/VREFBUF: + description: Voltage reference buffer. + items: + - name: CSR + description: control and status register. + byte_offset: 0 + fieldset: CSR + - name: CCR + description: calibration control register. + byte_offset: 4 + fieldset: CCR +fieldset/CCR: + description: calibration control register. + fields: + - name: TRIM + description: Trimming code. + bit_offset: 0 + bit_size: 6 +fieldset/CSR: + description: control and status register. + fields: + - name: ENVR + description: Voltage reference buffer mode enable. + bit_offset: 0 + bit_size: 1 + enum: ENVR + - name: HIZ + description: High impedance mode. + bit_offset: 1 + bit_size: 1 + enum: HIZ + - name: VRS + description: Voltage reference scale. + bit_offset: 2 + bit_size: 1 + enum: VRS + - name: VRR + description: Voltage reference buffer ready. + bit_offset: 3 + bit_size: 1 + enum: VRR +enum/ENVR: + bit_size: 1 + variants: + - name: Disabled + description: Internal voltage reference mode disable (external voltage reference mode). + value: 0 + - name: Enabled + description: Internal voltage reference mode (reference buffer enable or hold mode) enable. + value: 1 +enum/HIZ: + bit_size: 1 + variants: + - name: Connected + description: VREF+ pin is internally connected to the voltage reference buffer output. + value: 0 + - name: HighZ + description: VREF+ pin is high impedance. + value: 1 +enum/VRR: + bit_size: 1 + variants: + - name: NotReady + description: The voltage reference buffer output is not ready. + value: 0 + - name: Ready + description: The voltage reference buffer output reached the requested level. + value: 1 +enum/VRS: + bit_size: 1 + variants: + - name: V2_048 + description: Voltage reference set to VREF_OUT1 (around 2.048 V). + value: 0 + - name: V2_5 + description: Voltage reference set to VREF_OUT2 (around 2.5 V). + value: 1 diff --git a/data/registers/vrefbuf_v2a.yaml b/data/registers/vrefbuf_v2a.yaml new file mode 100644 index 0000000..44501d2 --- /dev/null +++ b/data/registers/vrefbuf_v2a.yaml @@ -0,0 +1,37 @@ +block/VREFBUF: + description: Voltage reference buffer. + items: + - name: CSR + description: VREFBUF control and status register. + byte_offset: 0 + fieldset: CSR + - name: CCR + description: VREFBUF calibration control register. + byte_offset: 4 + fieldset: CCR +fieldset/CCR: + description: VREFBUF calibration control register. + fields: + - name: TRIM + description: 'Trimming code The TRIM code is a 6-bit unsigned data (minimum 000000, maximum 111111) that is set and updated according the mechanism described below. Reset: TRIM[5:0] is automatically initialized with the VRS = 0 trimming value stored in the Flash memory during the production test. VRS change: TRIM[5:0] is automatically initialized with the trimming value (corresponding to VRS setting) stored in the Flash memory during the production test. Write in TRIM[5:0]: User can modify the TRIM[5:0] with an arbitrary value. This is permanently disabling the control of the trimming value with VRS (until the device is reset). Note: If the user application performs the trimming, the trimming code must start from 000000 to 111111 in ascending order.' + bit_offset: 0 + bit_size: 6 +fieldset/CSR: + description: VREFBUF control and status register. + fields: + - name: ENVR + description: Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode. + bit_offset: 0 + bit_size: 1 + - name: HIZ + description: High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to for the mode descriptions depending on ENVR bit configuration. + bit_offset: 1 + bit_size: 1 + - name: VRR + description: Voltage reference buffer ready. + bit_offset: 3 + bit_size: 1 + - name: VRS + description: 'Voltage reference scale These bits select the value generated by the voltage reference buffer. VRS = 000: VREFBUF0 voltage selected. VRS = 001: VREFBUF1 voltage selected. VRS = 010: VREFBUF2 voltage selected. VRS = 011: VREFBUF3 voltage selected. Others: Reserved Note: Refer to the product datasheet for each VREFBUFx voltage setting value. The software can program this bitfield only when the VREFBUF is disabled (ENVR=0).' + bit_offset: 4 + bit_size: 3 diff --git a/data/registers/vrefbuf_v2b.yaml b/data/registers/vrefbuf_v2b.yaml new file mode 100644 index 0000000..3dddcac --- /dev/null +++ b/data/registers/vrefbuf_v2b.yaml @@ -0,0 +1,37 @@ +block/VREFBUF: + description: Voltage reference buffer. + items: + - name: CSR + description: VREF_BUF Control and Status Register. + byte_offset: 0 + fieldset: CSR + - name: CCR + description: VREF_BUF Calibration Control Register. + byte_offset: 4 + fieldset: CCR +fieldset/CCR: + description: VREF_BUF Calibration Control Register. + fields: + - name: TRIM + description: Trimming code. + bit_offset: 0 + bit_size: 6 +fieldset/CSR: + description: VREF_BUF Control and Status Register. + fields: + - name: ENVR + description: Enable Voltage Reference. + bit_offset: 0 + bit_size: 1 + - name: HIZ + description: High impedence mode for the VREF_BUF. + bit_offset: 1 + bit_size: 1 + - name: VRR + description: Voltage reference buffer ready. + bit_offset: 3 + bit_size: 1 + - name: VRS + description: Voltage reference scale. + bit_offset: 4 + bit_size: 2