From 1cfb795d6bc4a9fa6299712be54b30c27120f448 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Thu, 29 Jun 2023 00:57:25 +0200 Subject: [PATCH] Fix accidental arrayifications. --- data/registers/adc_v3.yaml | 192 ++++----------------------------- data/registers/flash_l0.yaml | 26 ++--- data/registers/flash_l4.yaml | 3 - data/registers/pwr_wl5.yaml | 6 -- data/registers/rcc_u5.yaml | 3 - data/registers/spdifrx_v1.yaml | 3 - data/registers/syscfg_g0.yaml | 185 ++++++++++++++++--------------- data/registers/syscfg_wb.yaml | 5 +- 8 files changed, 127 insertions(+), 296 deletions(-) diff --git a/data/registers/adc_v3.yaml b/data/registers/adc_v3.yaml index cb7283f..752ec84 100644 --- a/data/registers/adc_v3.yaml +++ b/data/registers/adc_v3.yaml @@ -22,26 +22,20 @@ block/ADC: description: configuration register byte_offset: 16 fieldset: CFGR2 - - name: SMPR1 + - name: SMPR description: sample time register 1 + array: + len: 2 + stride: 4 byte_offset: 20 - fieldset: SMPR1 - - name: SMPR2 - description: sample time register 2 - byte_offset: 24 - fieldset: SMPR2 - - name: TR1 + fieldset: SMPR + - name: TR description: watchdog threshold register 1 + array: + len: 3 + stride: 4 byte_offset: 32 - fieldset: TR1 - - name: TR2 - description: watchdog threshold register - byte_offset: 36 - fieldset: TR2 - - name: TR3 - description: watchdog threshold register 3 - byte_offset: 40 - fieldset: TR3 + fieldset: TR - name: SQR1 description: regular sequence register 1 byte_offset: 48 @@ -73,15 +67,15 @@ block/ADC: len: 4 stride: 4 byte_offset: 96 - fieldset: OFR1 + fieldset: OFR - name: JDR - description: injected data register 1 + description: injected data registers array: len: 4 stride: 4 byte_offset: 128 access: Read - fieldset: JDR1 + fieldset: JDR - name: AWD2CR description: Analog Watchdog 2 Configuration Register byte_offset: 160 @@ -380,46 +374,13 @@ fieldset/ISR: description: JQOVF bit_offset: 10 bit_size: 1 -fieldset/JDR1: +fieldset/JDR: description: injected data register 1 fields: - name: JDATA description: JDATA1 bit_offset: 0 bit_size: 16 - array: - len: 1 - stride: 0 -fieldset/JDR2: - description: injected data register 2 - fields: - - name: JDATA - description: JDATA2 - bit_offset: 0 - bit_size: 16 - array: - len: 1 - stride: 0 -fieldset/JDR3: - description: injected data register 3 - fields: - - name: JDATA - description: JDATA3 - bit_offset: 0 - bit_size: 16 - array: - len: 1 - stride: 0 -fieldset/JDR4: - description: injected data register 4 - fields: - - name: JDATA - description: JDATA4 - bit_offset: 0 - bit_size: 16 - array: - len: 1 - stride: 0 fieldset/JSQR: description: injected sequence register fields: @@ -442,79 +403,19 @@ fieldset/JSQR: array: len: 4 stride: 6 -fieldset/OFR1: - description: offset register 1 +fieldset/OFR: + description: offset register fields: - name: OFFSET - description: OFFSET1 bit_offset: 0 bit_size: 12 - array: - len: 1 - stride: 0 - - name: OFFSET1_CH - description: OFFSET1_CH + - name: OFFSET_CH bit_offset: 26 bit_size: 5 - - name: OFFSET1_EN - description: OFFSET1_EN + - name: OFFSET_EN bit_offset: 31 bit_size: 1 -fieldset/OFR2: - description: offset register 2 - fields: - - name: OFFSET - description: OFFSET2 - bit_offset: 0 - bit_size: 12 - array: - len: 1 - stride: 0 - - name: OFFSET2_CH - description: OFFSET2_CH - bit_offset: 26 - bit_size: 5 - - name: OFFSET2_EN - description: OFFSET2_EN - bit_offset: 31 - bit_size: 1 -fieldset/OFR3: - description: offset register 3 - fields: - - name: OFFSET - description: OFFSET3 - bit_offset: 0 - bit_size: 12 - array: - len: 1 - stride: 0 - - name: OFFSET3_CH - description: OFFSET3_CH - bit_offset: 26 - bit_size: 5 - - name: OFFSET3_EN - description: OFFSET3_EN - bit_offset: 31 - bit_size: 1 -fieldset/OFR4: - description: offset register 4 - fields: - - name: OFFSET - description: OFFSET4 - bit_offset: 0 - bit_size: 12 - array: - len: 1 - stride: 0 - - name: OFFSET4_CH - description: OFFSET4_CH - bit_offset: 26 - bit_size: 5 - - name: OFFSET4_EN - description: OFFSET4_EN - bit_offset: 31 - bit_size: 1 -fieldset/SMPR1: +fieldset/SMPR: description: sample time register 1 fields: - name: SMP @@ -525,17 +426,6 @@ fieldset/SMPR1: len: 10 stride: 3 enum: SAMPLE_TIME -fieldset/SMPR2: - description: sample time register 2 - fields: - - name: SMP - description: Channel 10 sampling time selection - bit_offset: 0 - bit_size: 3 - array: - len: 9 - stride: 3 - enum: SAMPLE_TIME fieldset/SQR1: description: regular sequence register 1 fields: @@ -580,57 +470,17 @@ fieldset/SQR4: array: len: 2 stride: 6 -fieldset/TR1: - description: watchdog threshold register 1 +fieldset/TR: + description: watchdog threshold register fields: - name: LT description: LT1 bit_offset: 0 bit_size: 12 - array: - len: 1 - stride: 0 - name: HT description: HT1 bit_offset: 16 bit_size: 12 - array: - len: 1 - stride: 0 -fieldset/TR2: - description: watchdog threshold register - fields: - - name: LT - description: LT2 - bit_offset: 0 - bit_size: 8 - array: - len: 1 - stride: 0 - - name: HT - description: HT2 - bit_offset: 16 - bit_size: 8 - array: - len: 1 - stride: 0 -fieldset/TR3: - description: watchdog threshold register 3 - fields: - - name: LT - description: LT3 - bit_offset: 0 - bit_size: 8 - array: - len: 1 - stride: 0 - - name: HT - description: HT3 - bit_offset: 16 - bit_size: 8 - array: - len: 1 - stride: 0 enum/RES: bit_size: 2 variants: diff --git a/data/registers/flash_l0.yaml b/data/registers/flash_l0.yaml index edb9c00..09cadbe 100644 --- a/data/registers/flash_l0.yaml +++ b/data/registers/flash_l0.yaml @@ -39,16 +39,16 @@ block/FLASH: byte_offset: 28 access: Read fieldset: OPTR - - name: WRPROT1 + - name: WRPROT description: Write Protection Register 1 byte_offset: 32 access: Read - fieldset: WRPROT1 + fieldset: WRPROT - name: WRPROT2 description: Write Protection Register 2 byte_offset: 128 access: Read - fieldset: WRPROT2 + fieldset: WRPROT fieldset/ACR: description: Access control register fields: @@ -217,23 +217,13 @@ fieldset/SR: description: FWWERR bit_offset: 17 bit_size: 1 -fieldset/WRPROT1: - description: Write Protection Register 1 +fieldset/WRPROT: + description: Write Protection Register fields: - name: WRPROT description: Write Protection bit_offset: 0 - bit_size: 32 + bit_size: 1 array: - len: 1 - stride: 0 -fieldset/WRPROT2: - description: Write Protection Register 2 - fields: - - name: WRPROT - description: Write Protection - bit_offset: 0 - bit_size: 16 - array: - len: 1 - stride: 0 + len: 32 + stride: 1 diff --git a/data/registers/flash_l4.yaml b/data/registers/flash_l4.yaml index 8cc2bc1..a4f63c1 100644 --- a/data/registers/flash_l4.yaml +++ b/data/registers/flash_l4.yaml @@ -246,9 +246,6 @@ fieldset/OPTR: description: Dual-bank boot bit_offset: 20 bit_size: 1 - array: - len: 1 - stride: 0 - name: DUALBANK description: Dual-Bank on 512 KB or 256 KB Flash memory devices bit_offset: 21 diff --git a/data/registers/pwr_wl5.yaml b/data/registers/pwr_wl5.yaml index 2c15757..858653a 100644 --- a/data/registers/pwr_wl5.yaml +++ b/data/registers/pwr_wl5.yaml @@ -175,9 +175,6 @@ fieldset/CR2: description: "Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V" bit_offset: 6 bit_size: 1 - array: - len: 1 - stride: 0 enum: PVME fieldset/CR3: description: Power control register 3 @@ -461,9 +458,6 @@ fieldset/SR2: description: "Peripheral voltage monitoring output: VDDA vs. 1.62 V" bit_offset: 14 bit_size: 1 - array: - len: 1 - stride: 0 enum: PVMO fieldset/SUBGHZSPICR: description: Power SPI3 control register diff --git a/data/registers/rcc_u5.yaml b/data/registers/rcc_u5.yaml index 1638ec3..9e5efbb 100644 --- a/data/registers/rcc_u5.yaml +++ b/data/registers/rcc_u5.yaml @@ -2341,9 +2341,6 @@ fieldset/PLL3CFGR: description: "PLL3 DIVQ divider output enable\r Set and reset by software to enable the pll3_q_ck output of the PLL3.\r To save power, PLL3QEN and PLL3Q bits must be set to 0 when the pll3_q_ck is not used.\r This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0)." bit_offset: 17 bit_size: 1 - array: - len: 1 - stride: 0 - name: PLLREN description: "PLL3 DIVR divider output enable\r Set and reset by software to enable the pll3_r_ck output of the PLL3.\r To save power, PLL3REN and PLL3R bits must be set to 0 when the pll3_r_ck is not used.\r This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0)." bit_offset: 18 diff --git a/data/registers/spdifrx_v1.yaml b/data/registers/spdifrx_v1.yaml index c1f7f6a..ada1268 100644 --- a/data/registers/spdifrx_v1.yaml +++ b/data/registers/spdifrx_v1.yaml @@ -236,6 +236,3 @@ fieldset/SR: description: Duration of 5 symbols counted with SPDIF_CLK bit_offset: 16 bit_size: 15 - array: - len: 1 - stride: 0 diff --git a/data/registers/syscfg_g0.yaml b/data/registers/syscfg_g0.yaml index e330d11..3cf81eb 100644 --- a/data/registers/syscfg_g0.yaml +++ b/data/registers/syscfg_g0.yaml @@ -340,13 +340,14 @@ fieldset/ITLINE12: description: ADC bit_offset: 0 bit_size: 1 - - name: COMP + - name: COMP1 description: COMP1 bit_offset: 1 bit_size: 1 - array: - len: 2 - stride: 1 + - name: COMP2 + description: COMP2 + bit_offset: 2 + bit_size: 1 fieldset/ITLINE13: description: interrupt line 13 status register fields: @@ -376,71 +377,50 @@ fieldset/ITLINE14: fieldset/ITLINE15: description: interrupt line 15 status register fields: - - name: TIM + - name: TIM2 description: TIM2 bit_offset: 0 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/ITLINE16: description: interrupt line 16 status register fields: - - name: TIM + - name: TIM3 description: TIM3 bit_offset: 0 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/ITLINE17: description: interrupt line 17 status register fields: - - name: TIM + - name: TIM6 description: TIM6 bit_offset: 0 bit_size: 1 - array: - len: 1 - stride: 0 - name: DAC description: DAC bit_offset: 1 bit_size: 1 - - name: LPTIM + - name: LPTIM1 description: LPTIM1 bit_offset: 2 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/ITLINE18: description: interrupt line 18 status register fields: - - name: TIM + - name: TIM7 description: TIM7 bit_offset: 0 bit_size: 1 - array: - len: 1 - stride: 0 - - name: LPTIM + - name: LPTIM2 description: LPTIM2 bit_offset: 1 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/ITLINE19: description: interrupt line 19 status register fields: - - name: TIM + - name: TIM14 description: TIM14 bit_offset: 0 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/ITLINE2: description: interrupt line 2 status register fields: @@ -455,33 +435,24 @@ fieldset/ITLINE2: fieldset/ITLINE20: description: interrupt line 20 status register fields: - - name: TIM + - name: TIM15 description: TIM15 bit_offset: 0 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/ITLINE21: description: interrupt line 21 status register fields: - - name: TIM + - name: TIM16 description: TIM16 bit_offset: 0 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/ITLINE22: description: interrupt line 22 status register fields: - - name: TIM + - name: TIM17 description: TIM17 bit_offset: 0 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/ITLINE23: description: interrupt line 23 status register fields: @@ -499,53 +470,46 @@ fieldset/ITLINE24: fieldset/ITLINE25: description: interrupt line 25 status register fields: - - name: SPI + - name: SPI1 description: SPI1 bit_offset: 0 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/ITLINE26: description: interrupt line 26 status register fields: - - name: SPI + - name: SPI2 description: SPI2 bit_offset: 0 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/ITLINE27: description: interrupt line 27 status register fields: - - name: USART + - name: USART1 description: USART1 bit_offset: 0 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/ITLINE28: description: interrupt line 28 status register fields: - - name: USART + - name: USART2 description: USART2 bit_offset: 0 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/ITLINE29: description: interrupt line 29 status register fields: - - name: USART - description: USART3 + - name: USART3 bit_offset: 0 bit_size: 1 - array: - len: 3 - stride: 1 + - name: USART4 + bit_offset: 1 + bit_size: 1 + - name: USART5 + bit_offset: 3 + bit_size: 1 + - name: USART6 + bit_offset: 4 + bit_size: 1 fieldset/ITLINE3: description: interrupt line 3 status register fields: @@ -560,13 +524,10 @@ fieldset/ITLINE3: fieldset/ITLINE30: description: interrupt line 30 status register fields: - - name: USART + - name: CEC description: CEC bit_offset: 0 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/ITLINE31: description: interrupt line 31 status register fields: @@ -588,43 +549,91 @@ fieldset/ITLINE4: fieldset/ITLINE5: description: interrupt line 5 status register fields: - - name: EXTI - description: EXTI + - name: EXTI0 + description: EXTI0 bit_offset: 0 bit_size: 1 - array: - len: 2 - stride: 1 + - name: EXTI1 + description: EXTI1 + bit_offset: 1 + bit_size: 1 fieldset/ITLINE6: description: interrupt line 6 status register fields: - - name: EXTI - description: EXTI + - name: EXTI2 + description: EXTI2 bit_offset: 0 bit_size: 1 - array: - len: 2 - stride: 1 + - name: EXTI3 + description: EXTI3 + bit_offset: 1 + bit_size: 1 fieldset/ITLINE7: description: interrupt line 7 status register fields: - - name: EXTI - description: EXTI + - name: EXTI4 + description: EXTI4 bit_offset: 0 bit_size: 1 - array: - len: 12 - stride: 1 + - name: EXTI5 + description: EXTI5 + bit_offset: 1 + bit_size: 1 + - name: EXTI6 + description: EXTI6 + bit_offset: 2 + bit_size: 1 + - name: EXTI7 + description: EXTI7 + bit_offset: 3 + bit_size: 1 + - name: EXTI8 + description: EXTI8 + bit_offset: 4 + bit_size: 1 + - name: EXTI9 + description: EXTI9 + bit_offset: 5 + bit_size: 1 + - name: EXTI10 + description: EXTI10 + bit_offset: 6 + bit_size: 1 + - name: EXTI11 + description: EXTI11 + bit_offset: 7 + bit_size: 1 + - name: EXTI12 + description: EXTI12 + bit_offset: 8 + bit_size: 1 + - name: EXTI13 + description: EXTI13 + bit_offset: 9 + bit_size: 1 + - name: EXTI14 + description: EXTI14 + bit_offset: 10 + bit_size: 1 + - name: EXTI15 + description: EXTI15 + bit_offset: 11 + bit_size: 1 fieldset/ITLINE8: description: interrupt line 8 status register fields: - - name: UCPD + - name: UCPD1 description: UCPD1 bit_offset: 0 bit_size: 1 - array: - len: 2 - stride: 1 + - name: UCPD2 + description: UCPD2 + bit_offset: 1 + bit_size: 1 + - name: USB + description: USB + bit_offset: 2 + bit_size: 1 fieldset/ITLINE9: description: interrupt line 9 status register fields: diff --git a/data/registers/syscfg_wb.yaml b/data/registers/syscfg_wb.yaml index d25c0ef..788fa92 100644 --- a/data/registers/syscfg_wb.yaml +++ b/data/registers/syscfg_wb.yaml @@ -91,13 +91,10 @@ fieldset/C2IMR1: description: Peripheral RNG interrupt mask to CPU2 bit_offset: 9 bit_size: 1 - - name: AES + - name: AES1 description: Peripheral AES1 interrupt mask to CPU2 bit_offset: 10 bit_size: 1 - array: - len: 1 - stride: 0 - name: COMP description: Peripheral COMP interrupt mask to CPU2 bit_offset: 11