ch2_cmp, ch2, ch1_cmp, ch1 merged
This commit is contained in:
eZio Pan
parent
0ed4c863d2
commit
1b83acf50b
@ -1,861 +0,0 @@
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block/TIM_1CH:
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description: 1-channel timers
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items:
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- name: CR1
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description: control register 1
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byte_offset: 0
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fieldset: CR1_1CH
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- name: DIER
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description: DMA/Interrupt enable register
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byte_offset: 12
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fieldset: DIER_1CH
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- name: SR
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description: status register
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byte_offset: 16
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fieldset: SR_1CH
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- name: EGR
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description: event generation register
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byte_offset: 20
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access: Write
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fieldset: EGR_1CH
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- name: CCMR_Input
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description: capture/compare mode register 1 (input mode)
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array:
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len: 1
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stride: 4
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byte_offset: 24
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fieldset: CCMR_Input_1CH
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- name: CCMR_Output
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description: capture/compare mode register 1 (output mode)
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array:
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len: 1
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stride: 4
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byte_offset: 24
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fieldset: CCMR_Output_1CH
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- name: CCER
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description: capture/compare enable register
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byte_offset: 32
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fieldset: CCER_1CH
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- name: CNT
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description: counter
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byte_offset: 36
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fieldset: CNT_1CH
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- name: PSC
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description: prescaler
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byte_offset: 40
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fieldset: PSC_1CH
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- name: ARR
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description: auto-reload register (Dither mode disabled)
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byte_offset: 44
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fieldset: ARR_1CH
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- name: ARR_DITHER
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description: auto-reload register (Dither mode enabled)
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byte_offset: 44
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fieldset: ARR_DITHER_1CH
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- name: CCR
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description: capture/compare register x (x=1) (Dither mode disabled)
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array:
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len: 1
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stride: 4
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byte_offset: 52
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fieldset: CCR_1CH
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- name: CCR_DITHER
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description: capture/compare register x (x=1) (Dither mode enabled)
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array:
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len: 1
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stride: 4
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byte_offset: 52
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fieldset: CCR_DITHER_1CH
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- name: TISEL
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description: input selection register
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byte_offset: 92
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fieldset: TISEL_1CH
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fieldset/ARR_1CH:
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description: auto-reload register (Dither mode disabled)
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fields:
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- name: ARR
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description: Auto-reload value
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bit_offset: 0
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bit_size: 16
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fieldset/ARR_DITHER_1CH:
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description: auto-reload register (Dither mode enabled)
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fields:
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- name: DITHER
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description: Dither value
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bit_offset: 0
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bit_size: 4
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- name: ARR
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description: Auto-reload value
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bit_offset: 4
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bit_size: 16
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fieldset/CCER_1CH:
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description: capture/compare enable register
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fields:
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- name: CCE
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description: Capture/Compare x (x=1) output enable
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bit_offset: 0
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bit_size: 1
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array:
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len: 1
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stride: 4
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- name: CCP
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description: Capture/Compare x (x=1) output Polarity
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bit_offset: 1
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bit_size: 1
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array:
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len: 1
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stride: 4
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- name: CCNP
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description: Capture/Compare x (x=1) output Polarity
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bit_offset: 3
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bit_size: 1
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array:
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len: 1
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stride: 4
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fieldset/CCMR_Input_1CH:
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description: capture/compare mode register x (x=1) (input mode)
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fields:
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- name: CCS
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description: Capture/Compare y selection
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bit_offset: 0
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bit_size: 2
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array:
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len: 1
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stride: 8
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enum: CCMR_Input_CCS
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- name: ICPSC
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description: Input capture y prescaler
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bit_offset: 2
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bit_size: 2
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array:
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len: 1
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stride: 8
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- name: ICF
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description: Input capture y filter
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bit_offset: 4
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bit_size: 4
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array:
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len: 1
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stride: 8
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enum: FilterValue
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fieldset/CCMR_Output_1CH:
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description: capture/compare mode register x (x=1) (output mode)
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fields:
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- name: CCS
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description: Capture/Compare y selection
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bit_offset: 0
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bit_size: 2
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array:
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len: 1
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stride: 8
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enum: CCMR_Output_CCS
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- name: OCFE
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description: Output compare y fast enable
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bit_offset: 2
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bit_size: 1
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array:
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len: 1
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stride: 8
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- name: OCPE
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description: Output compare y preload enable
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bit_offset: 3
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bit_size: 1
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array:
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len: 1
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stride: 8
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- name: OCM
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description: Output compare y mode
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bit_offset: 4
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bit_size: 3
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array:
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len: 1
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stride: 8
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enum: OCM
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fieldset/CCR_1CH:
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description: capture/compare register x (x=1) (Dither mode disabled)
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fields:
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- name: CCR
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description: capture/compare x (x=1) value
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bit_offset: 0
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bit_size: 16
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fieldset/CCR_DITHER_1CH:
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description: capture/compare register x (x=1) (Dither mode enabled)
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fields:
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- name: DITHER
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description: Dither value
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bit_offset: 0
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bit_size: 4
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- name: CCR
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description: capture/compare x (x=1) value
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bit_offset: 4
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bit_size: 16
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fieldset/CNT_1CH:
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description: counter
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fields:
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- name: CNT
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description: counter value
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bit_offset: 0
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bit_size: 16
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- name: UIFCPY
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description: UIF copy
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bit_offset: 31
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bit_size: 1
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fieldset/CR1_1CH:
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description: control register 1
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fields:
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- name: CEN
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description: Counter enable
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bit_offset: 0
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bit_size: 1
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- name: UDIS
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description: Update disable
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bit_offset: 1
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bit_size: 1
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- name: URS
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description: Update request source
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bit_offset: 2
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bit_size: 1
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enum: URS
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- name: OPM
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description: One-pulse mode enbaled
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bit_offset: 3
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bit_size: 1
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- name: ARPE
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description: Auto-reload preload enable
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bit_offset: 7
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bit_size: 1
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- name: CKD
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description: Clock division
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bit_offset: 8
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bit_size: 2
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enum: CKD
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- name: UIFREMAP
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description: UIF status bit remapping enable
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bit_offset: 11
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bit_size: 1
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- name: DITHEN
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description: Dithering enable
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bit_offset: 12
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bit_size: 1
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fieldset/DIER_1CH:
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description: DMA/Interrupt enable register
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fields:
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- name: UIE
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description: Update interrupt enable
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bit_offset: 0
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bit_size: 1
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- name: CCIE
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description: Capture/Compare x (x=1) interrupt enable
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bit_offset: 1
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bit_size: 1
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array:
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len: 1
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stride: 1
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fieldset/EGR_1CH:
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description: event generation register
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fields:
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- name: UG
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description: Update generation
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bit_offset: 0
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bit_size: 1
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- name: CCG
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description: Capture/compare x (x=1) generation
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bit_offset: 1
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bit_size: 1
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array:
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len: 1
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stride: 1
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fieldset/PSC_1CH:
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description: prescaler
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fields:
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- name: PSC
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description: Prescaler value
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bit_offset: 0
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bit_size: 16
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fieldset/SR_1CH:
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description: status register
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fields:
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- name: UIF
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description: Update interrupt flag
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bit_offset: 0
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bit_size: 1
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- name: CCIF
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description: Capture/compare x (x=1) interrupt flag
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bit_offset: 1
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bit_size: 1
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array:
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len: 1
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stride: 1
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- name: CCOF
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description: Capture/Compare x (x=1) overcapture flag
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bit_offset: 9
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bit_size: 1
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array:
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len: 1
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stride: 1
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fieldset/TISEL_1CH:
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description: input selection register
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fields:
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- name: TISEL
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description: Selects TIM_TIx (x=1) input
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bit_offset: 0
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bit_size: 4
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array:
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len: 1
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stride: 8
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block/TIM_1CH_CMP:
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extends: TIM_1CH
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description: 1-channel with one complementary output timers
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items:
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- name: CR2
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description: control register 2
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byte_offset: 4
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fieldset: CR2_1CH_CMP
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- name: DIER
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description: DMA/Interrupt enable register
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byte_offset: 12
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fieldset: DIER_1CH_CMP
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- name: SR
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description: status register
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byte_offset: 16
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fieldset: SR_1CH_CMP
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- name: EGR
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description: event generation register
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byte_offset: 20
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access: Write
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fieldset: EGR_1CH_CMP
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- name: CCER
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description: capture/compare enable register
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byte_offset: 32
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fieldset: CCER_1CH_CMP
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- name: RCR
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description: repetition counter register
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byte_offset: 48
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fieldset: RCR_1CH_CMP
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- name: CCR_DITHER
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description: capture/compare register x (x=1) (Dither mode enabled)
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array:
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len: 1
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stride: 4
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byte_offset: 52
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fieldset: CCR_DITHER_1CH_CMP
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- name: BDTR
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description: break and dead-time register
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byte_offset: 68
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fieldset: BDTR_1CH_CMP
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- name: DTR2
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description: break and dead-time register
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byte_offset: 84
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fieldset: DTR2_1CH_CMP
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- name: AF1
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description: alternate function register 1
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byte_offset: 96
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fieldset: AF1_1CH_CMP
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- name: AF2
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description: alternate function register 2
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byte_offset: 100
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fieldset: AF2_1CH_CMP
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- name: DCR
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description: DMA control register
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byte_offset: 988
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fieldset: DCR_1CH_CMP
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- name: DMAR
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description: DMA address for full transfer
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byte_offset: 992
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fieldset: DMAR_1CH_CMP
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fieldset/AF1_1CH_CMP:
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description: alternate function register 1
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fields:
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- name: BKINE
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description: TIMx_BKIN input enable
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bit_offset: 0
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bit_size: 1
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- name: BKCMPE
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description: TIM_BRK_CMPx (x=1-8) enable
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bit_offset: 1
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bit_size: 1
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array:
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len: 8
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stride: 1
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- name: BKINP
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description: TIMx_BKIN input polarity
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bit_offset: 9
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bit_size: 1
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enum: BKINP
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- name: BKCMPP
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description: TIM_BRK_CMPx (x=1-4) input polarity
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bit_offset: 10
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bit_size: 1
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array:
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len: 4
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stride: 1
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enum: BKINP
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fieldset/AF2_1CH_CMP:
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description: alternate function register 2
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fields:
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- name: OCRSEL
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description: ocref_clr source selection
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bit_offset: 16
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bit_size: 3
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fieldset/BDTR_1CH_CMP:
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description: break and dead-time register
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fields:
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- name: DTG
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description: Dead-time generator setup
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bit_offset: 0
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bit_size: 8
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- name: LOCK
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description: Lock configuration
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bit_offset: 8
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bit_size: 2
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enum: LOCK
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- name: OSSI
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description: Off-state selection for Idle mode
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bit_offset: 10
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bit_size: 1
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enum: OSSI
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- name: OSSR
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description: Off-state selection for Run mode
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bit_offset: 11
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bit_size: 1
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enum: OSSR
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- name: BKE
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description: Break x (x=1) enable
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bit_offset: 12
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bit_size: 1
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array:
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len: 1
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stride: 12
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- name: BKP
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description: Break x (x=1) polarity
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bit_offset: 13
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bit_size: 1
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array:
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len: 1
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stride: 12
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enum: BKP
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- name: AOE
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description: Automatic output enable
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bit_offset: 14
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bit_size: 1
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- name: MOE
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description: Main output enable
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bit_offset: 15
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bit_size: 1
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- name: BKF
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description: Break x (x=1) filter
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bit_offset: 16
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bit_size: 4
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array:
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len: 1
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stride: 4
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enum: FilterValue
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- name: BKDSRM
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description: Break x (x=1) Disarm
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bit_offset: 26
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bit_size: 1
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array:
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len: 1
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stride: 1
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enum: BKDSRM
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- name: BKBID
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description: Break x (x=1) bidirectional
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bit_offset: 28
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bit_size: 1
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array:
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len: 1
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stride: 1
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enum: BKBID
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fieldset/CCER_1CH_CMP:
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extends: CCER_1CH
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description: capture/compare enable register
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fields:
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- name: CCE
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description: Capture/Compare x (x=1) output enable
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bit_offset: 0
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bit_size: 1
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array:
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len: 1
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stride: 4
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- name: CCP
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description: Capture/Compare x (x=1) output Polarity
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bit_offset: 1
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bit_size: 1
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array:
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len: 1
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stride: 4
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- name: CCNP
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description: Capture/Compare x (x=1) output Polarity
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bit_offset: 3
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bit_size: 1
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array:
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len: 1
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stride: 4
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fieldset/CCR_DITHER_1CH_CMP:
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description: capture/compare register x (x=1) (Dither mode enabled)
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fields:
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- name: DITHER
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description: Dither value
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bit_offset: 0
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bit_size: 4
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- name: CCR
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description: capture/compare x (x=1) value
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bit_offset: 4
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bit_size: 16
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fieldset/CR2_1CH_CMP:
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description: control register 2
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fields:
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- name: CCPC
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description: Capture/compare preloaded control
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bit_offset: 0
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bit_size: 1
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- name: CCUS
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description: Capture/compare control update selection
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bit_offset: 2
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bit_size: 1
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- name: CCDS
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description: Capture/compare DMA selection
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bit_offset: 3
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bit_size: 1
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enum: CCDS
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- name: OIS
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description: Output Idle state x (x=1)
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bit_offset: 8
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bit_size: 1
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array:
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len: 1
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stride: 2
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- name: OISN
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description: Output Idle state x (x=1)
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bit_offset: 9
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bit_size: 1
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array:
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len: 1
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stride: 2
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fieldset/DCR_1CH_CMP:
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description: DMA control register
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fields:
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- name: DBA
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description: DMA base address
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bit_offset: 0
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bit_size: 5
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- name: DBL
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description: DMA burst length
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bit_offset: 8
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bit_size: 5
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- name: DBSS
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description: DMA burst source selection
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bit_offset: 16
|
||||
bit_size: 4
|
||||
enum: DBSS
|
||||
fieldset/DIER_1CH_CMP:
|
||||
extends: DIER_1CH
|
||||
description: DMA/Interrupt enable register
|
||||
fields:
|
||||
- name: COMIE
|
||||
description: COM interrupt enable
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: BIE
|
||||
description: Break interrupt enable
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: UDE
|
||||
description: Update DMA request enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: CCDE
|
||||
description: Capture/Compare x (x=1) DMA request enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 1
|
||||
stride: 1
|
||||
fieldset/DMAR_1CH_CMP:
|
||||
description: DMA address for full transfer
|
||||
fields:
|
||||
- name: DMAB
|
||||
description: DMA register for burst accesses
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/DTR2_1CH_CMP:
|
||||
description: deadtime register 2
|
||||
fields:
|
||||
- name: DTGF
|
||||
description: Dead-time falling edge generator setup
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: DTAE
|
||||
description: Deadtime asymmetric enable
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
enum: DTAE
|
||||
- name: DTPE
|
||||
description: Deadtime preload enable
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
fieldset/EGR_1CH_CMP:
|
||||
extends: EGR_1CH
|
||||
description: event generation register
|
||||
fields:
|
||||
- name: COMG
|
||||
description: Capture/Compare control update generation
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: BG
|
||||
description: Break x (x=1) generation
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 1
|
||||
stride: 1
|
||||
fieldset/RCR_1CH_CMP:
|
||||
description: repetition counter register
|
||||
fields:
|
||||
- name: REP
|
||||
description: Repetition counter value
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/SR_1CH_CMP:
|
||||
extends: SR_1CH
|
||||
description: status register
|
||||
fields:
|
||||
- name: COMIF
|
||||
description: COM interrupt flag
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: BIF
|
||||
description: Break x (x=1) interrupt flag
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 1
|
||||
stride: 1
|
||||
enum/BKBID:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Input
|
||||
description: Break input tim_brk in input mode
|
||||
value: 0
|
||||
- name: Bidirectional
|
||||
description: Break input tim_brk in bidirectional mode
|
||||
value: 1
|
||||
enum/BKDSRM:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Armed
|
||||
description: Break input tim_brk is armed
|
||||
value: 0
|
||||
- name: Disarmed
|
||||
description: Break input tim_brk is disarmed
|
||||
value: 1
|
||||
enum/BKINP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NotInverted
|
||||
description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1)
|
||||
value: 0
|
||||
- name: Inverted
|
||||
description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1)
|
||||
value: 1
|
||||
enum/BKP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: ActiveLow
|
||||
description: Break input tim_brk is active low
|
||||
value: 0
|
||||
- name: ActiveHigh
|
||||
description: Break input tim_brk is active high
|
||||
value: 1
|
||||
enum/CCDS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: OnCompare
|
||||
description: CCx DMA request sent when CCx event occurs
|
||||
value: 0
|
||||
- name: OnUpdate
|
||||
description: CCx DMA request sent when update event occurs
|
||||
value: 1
|
||||
enum/CCMR_Input_CCS:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: TI4
|
||||
description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx'
|
||||
value: 1
|
||||
- name: TI3
|
||||
description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)
|
||||
value: 2
|
||||
- name: TRC
|
||||
description: CCx channel is configured as input, ICx is mapped on TRC
|
||||
value: 3
|
||||
enum/CCMR_Output_CCS:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Output
|
||||
description: CCx channel is configured as output
|
||||
value: 0
|
||||
enum/CKD:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Div1
|
||||
description: t_DTS = t_CK_INT
|
||||
value: 0
|
||||
- name: Div2
|
||||
description: t_DTS = 2 × t_CK_INT
|
||||
value: 1
|
||||
- name: Div4
|
||||
description: t_DTS = 4 × t_CK_INT
|
||||
value: 2
|
||||
enum/DBSS:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: Update
|
||||
description: Update
|
||||
value: 1
|
||||
- name: CC1
|
||||
description: CC1
|
||||
value: 2
|
||||
- name: CC2
|
||||
description: CC2
|
||||
value: 3
|
||||
- name: CC3
|
||||
description: CC3
|
||||
value: 4
|
||||
- name: CC4
|
||||
description: CC4
|
||||
value: 5
|
||||
- name: COM
|
||||
description: COM
|
||||
value: 6
|
||||
- name: Trigger
|
||||
description: Trigger
|
||||
value: 7
|
||||
enum/DTAE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Identical
|
||||
description: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register
|
||||
value: 0
|
||||
- name: Distinct
|
||||
description: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits.
|
||||
value: 1
|
||||
enum/FilterValue:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: NoFilter
|
||||
description: No filter, sampling is done at fDTS
|
||||
value: 0
|
||||
- name: FCK_INT_N2
|
||||
description: fSAMPLING=fCK_INT, N=2
|
||||
value: 1
|
||||
- name: FCK_INT_N4
|
||||
description: fSAMPLING=fCK_INT, N=4
|
||||
value: 2
|
||||
- name: FCK_INT_N8
|
||||
description: fSAMPLING=fCK_INT, N=8
|
||||
value: 3
|
||||
- name: FDTS_Div2_N6
|
||||
description: fSAMPLING=fDTS/2, N=6
|
||||
value: 4
|
||||
- name: FDTS_Div2_N8
|
||||
description: fSAMPLING=fDTS/2, N=8
|
||||
value: 5
|
||||
- name: FDTS_Div4_N6
|
||||
description: fSAMPLING=fDTS/4, N=6
|
||||
value: 6
|
||||
- name: FDTS_Div4_N8
|
||||
description: fSAMPLING=fDTS/4, N=8
|
||||
value: 7
|
||||
- name: FDTS_Div8_N6
|
||||
description: fSAMPLING=fDTS/8, N=6
|
||||
value: 8
|
||||
- name: FDTS_Div8_N8
|
||||
description: fSAMPLING=fDTS/8, N=8
|
||||
value: 9
|
||||
- name: FDTS_Div16_N5
|
||||
description: fSAMPLING=fDTS/16, N=5
|
||||
value: 10
|
||||
- name: FDTS_Div16_N6
|
||||
description: fSAMPLING=fDTS/16, N=6
|
||||
value: 11
|
||||
- name: FDTS_Div16_N8
|
||||
description: fSAMPLING=fDTS/16, N=8
|
||||
value: 12
|
||||
- name: FDTS_Div32_N5
|
||||
description: fSAMPLING=fDTS/32, N=5
|
||||
value: 13
|
||||
- name: FDTS_Div32_N6
|
||||
description: fSAMPLING=fDTS/32, N=6
|
||||
value: 14
|
||||
- name: FDTS_Div32_N8
|
||||
description: fSAMPLING=fDTS/32, N=8
|
||||
value: 15
|
||||
enum/LOCK:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: No bit is write protected
|
||||
value: 0
|
||||
- name: Level1
|
||||
description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written
|
||||
value: 1
|
||||
- name: Level2
|
||||
description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
|
||||
value: 2
|
||||
- name: Level3
|
||||
description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.
|
||||
value: 3
|
||||
enum/OCM:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Frozen
|
||||
description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
|
||||
value: 0
|
||||
- name: ActiveOnMatch
|
||||
description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
|
||||
value: 1
|
||||
- name: InactiveOnMatch
|
||||
description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
|
||||
value: 2
|
||||
- name: Toggle
|
||||
description: OCyREF toggles when TIMx_CNT=TIMx_CCRy
|
||||
value: 3
|
||||
- name: ForceInactive
|
||||
description: OCyREF is forced low
|
||||
value: 4
|
||||
- name: ForceActive
|
||||
description: OCyREF is forced high
|
||||
value: 5
|
||||
- name: PwmMode1
|
||||
description: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
|
||||
value: 6
|
||||
- name: PwmMode2
|
||||
description: Inversely to PwmMode1
|
||||
value: 7
|
||||
enum/OSSI:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: When inactive, OC/OCN outputs are disabled
|
||||
value: 0
|
||||
- name: IdleLevel
|
||||
description: When inactive, OC/OCN outputs are forced to idle level
|
||||
value: 1
|
||||
enum/OSSR:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: When inactive, OC/OCN outputs are disabled
|
||||
value: 0
|
||||
- name: IdleLevel
|
||||
description: When inactive, OC/OCN outputs are enabled with their inactive level
|
||||
value: 1
|
||||
enum/URS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: AnyEvent
|
||||
description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
|
||||
value: 0
|
||||
- name: CounterOnly
|
||||
description: Only counter overflow/underflow generates an update interrupt or DMA request
|
||||
value: 1
|
||||
@ -70,6 +70,59 @@ block/TIM_1CH:
|
||||
description: input selection register
|
||||
byte_offset: 92
|
||||
fieldset: TISEL_1CH
|
||||
block/TIM_1CH_CMP:
|
||||
extends: TIM_1CH
|
||||
description: 1-channel with one complementary output timers
|
||||
items:
|
||||
- name: CR2
|
||||
description: control register 2
|
||||
byte_offset: 4
|
||||
fieldset: CR2_1CH_CMP
|
||||
- name: DIER
|
||||
description: DMA/Interrupt enable register
|
||||
byte_offset: 12
|
||||
fieldset: DIER_1CH_CMP
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 16
|
||||
fieldset: SR_1CH_CMP
|
||||
- name: EGR
|
||||
description: event generation register
|
||||
byte_offset: 20
|
||||
access: Write
|
||||
fieldset: EGR_1CH_CMP
|
||||
- name: CCER
|
||||
description: capture/compare enable register
|
||||
byte_offset: 32
|
||||
fieldset: CCER_1CH_CMP
|
||||
- name: RCR
|
||||
description: repetition counter register
|
||||
byte_offset: 48
|
||||
fieldset: RCR_1CH_CMP
|
||||
- name: BDTR
|
||||
description: break and dead-time register
|
||||
byte_offset: 68
|
||||
fieldset: BDTR_1CH_CMP
|
||||
- name: DTR2
|
||||
description: break and dead-time register
|
||||
byte_offset: 84
|
||||
fieldset: DTR2_1CH_CMP
|
||||
- name: AF1
|
||||
description: alternate function register 1
|
||||
byte_offset: 96
|
||||
fieldset: AF1_1CH_CMP
|
||||
- name: AF2
|
||||
description: alternate function register 2
|
||||
byte_offset: 100
|
||||
fieldset: AF2_1CH_CMP
|
||||
- name: DCR
|
||||
description: DMA control register
|
||||
byte_offset: 988
|
||||
fieldset: DCR_1CH_CMP
|
||||
- name: DMAR
|
||||
description: DMA address for full transfer
|
||||
byte_offset: 992
|
||||
fieldset: DMAR_1CH_CMP
|
||||
block/TIM_2CH:
|
||||
extends: TIM_1CH
|
||||
description: 2-channel timers
|
||||
@ -150,12 +203,12 @@ block/TIM_2CH_CMP:
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 16
|
||||
fieldset: SR_2CH_CMP
|
||||
fieldset: SR_1CH_CMP
|
||||
- name: EGR
|
||||
description: event generation register
|
||||
byte_offset: 20
|
||||
access: Write
|
||||
fieldset: EGR_2CH_CMP
|
||||
fieldset: EGR_1CH_CMP
|
||||
- name: CCER
|
||||
description: capture/compare enable register
|
||||
byte_offset: 32
|
||||
@ -163,15 +216,15 @@ block/TIM_2CH_CMP:
|
||||
- name: RCR
|
||||
description: repetition counter register
|
||||
byte_offset: 48
|
||||
fieldset: RCR_2CH_CMP
|
||||
fieldset: RCR_1CH_CMP
|
||||
- name: BDTR
|
||||
description: break and dead-time register
|
||||
byte_offset: 68
|
||||
fieldset: BDTR_2CH_CMP
|
||||
fieldset: BDTR_1CH_CMP
|
||||
- name: DTR2
|
||||
description: break and dead-time register
|
||||
byte_offset: 84
|
||||
fieldset: DTR2_2CH_CMP
|
||||
fieldset: DTR2_1CH_CMP
|
||||
- name: TISEL
|
||||
description: input selection register
|
||||
byte_offset: 92
|
||||
@ -179,20 +232,20 @@ block/TIM_2CH_CMP:
|
||||
- name: AF1
|
||||
description: alternate function register 1
|
||||
byte_offset: 96
|
||||
fieldset: AF1_2CH_CMP
|
||||
fieldset: AF1_1CH_CMP
|
||||
- name: AF2
|
||||
description: alternate function register 2
|
||||
byte_offset: 100
|
||||
fieldset: AF2_2CH_CMP
|
||||
fieldset: AF2_1CH_CMP
|
||||
- name: DCR
|
||||
description: DMA control register
|
||||
byte_offset: 988
|
||||
fieldset: DCR_2CH_CMP
|
||||
fieldset: DCR_1CH_CMP
|
||||
- name: DMAR
|
||||
description: DMA address for full transfer
|
||||
byte_offset: 992
|
||||
fieldset: DMAR_2CH_CMP
|
||||
fieldset/AF1_2CH_CMP:
|
||||
fieldset: DMAR_1CH_CMP
|
||||
fieldset/AF1_1CH_CMP:
|
||||
description: alternate function register 1
|
||||
fields:
|
||||
- name: BKINE
|
||||
@ -219,7 +272,7 @@ fieldset/AF1_2CH_CMP:
|
||||
len: 4
|
||||
stride: 1
|
||||
enum: BKINP
|
||||
fieldset/AF2_2CH_CMP:
|
||||
fieldset/AF2_1CH_CMP:
|
||||
description: alternate function register 2
|
||||
fields:
|
||||
- name: OCRSEL
|
||||
@ -244,7 +297,7 @@ fieldset/ARR_DITHER_1CH:
|
||||
description: Auto-reload value
|
||||
bit_offset: 4
|
||||
bit_size: 16
|
||||
fieldset/BDTR_2CH_CMP:
|
||||
fieldset/BDTR_1CH_CMP:
|
||||
description: break and dead-time register
|
||||
fields:
|
||||
- name: DTG
|
||||
@ -337,6 +390,17 @@ fieldset/CCER_1CH:
|
||||
array:
|
||||
len: 1
|
||||
stride: 4
|
||||
fieldset/CCER_1CH_CMP:
|
||||
extends: CCER_1CH
|
||||
description: capture/compare enable register
|
||||
fields:
|
||||
- name: CCNE
|
||||
description: Capture/Compare x (x=1) complementary output enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 1
|
||||
stride: 4
|
||||
fieldset/CCER_2CH:
|
||||
extends: CCER_1CH
|
||||
description: capture/compare enable register
|
||||
@ -577,6 +641,36 @@ fieldset/CR1_1CH:
|
||||
description: Dithering enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
fieldset/CR2_1CH_CMP:
|
||||
description: control register 2
|
||||
fields:
|
||||
- name: CCPC
|
||||
description: Capture/compare preloaded control
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: CCUS
|
||||
description: Capture/compare control update selection
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: CCDS
|
||||
description: Capture/compare DMA selection
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
enum: CCDS
|
||||
- name: OIS
|
||||
description: Output Idle state x (x=1)
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 1
|
||||
stride: 2
|
||||
- name: OISN
|
||||
description: Output Idle state x (x=1)
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 1
|
||||
stride: 2
|
||||
fieldset/CR2_2CH:
|
||||
description: control register 2
|
||||
fields:
|
||||
@ -621,7 +715,7 @@ fieldset/CR2_2CH_CMP:
|
||||
array:
|
||||
len: 1
|
||||
stride: 2
|
||||
fieldset/DCR_2CH_CMP:
|
||||
fieldset/DCR_1CH_CMP:
|
||||
description: DMA control register
|
||||
fields:
|
||||
- name: DBA
|
||||
@ -651,25 +745,10 @@ fieldset/DIER_1CH:
|
||||
array:
|
||||
len: 1
|
||||
stride: 1
|
||||
fieldset/DIER_2CH:
|
||||
fieldset/DIER_1CH_CMP:
|
||||
extends: DIER_1CH
|
||||
description: DMA/Interrupt enable register
|
||||
fields:
|
||||
- name: CCIE
|
||||
description: Capture/Compare x (x=1-2) interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 1
|
||||
- name: TIE
|
||||
description: Trigger interrupt enable
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
fieldset/DIER_2CH_CMP:
|
||||
extends: DIER_2CH
|
||||
description: DMA/Interrupt enable register
|
||||
fields:
|
||||
- name: COMIE
|
||||
description: COM interrupt enable
|
||||
bit_offset: 5
|
||||
@ -689,6 +768,25 @@ fieldset/DIER_2CH_CMP:
|
||||
array:
|
||||
len: 1
|
||||
stride: 1
|
||||
fieldset/DIER_2CH:
|
||||
extends: DIER_1CH
|
||||
description: DMA/Interrupt enable register
|
||||
fields:
|
||||
- name: CCIE
|
||||
description: Capture/Compare x (x=1-2) interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 1
|
||||
- name: TIE
|
||||
description: Trigger interrupt enable
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
fieldset/DIER_2CH_CMP:
|
||||
extends: DIER_1CH_CMP
|
||||
description: DMA/Interrupt enable register
|
||||
fields:
|
||||
- name: COMDE
|
||||
description: COM DMA request enable
|
||||
bit_offset: 13
|
||||
@ -697,14 +795,14 @@ fieldset/DIER_2CH_CMP:
|
||||
description: Trigger DMA request enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
fieldset/DMAR_2CH_CMP:
|
||||
fieldset/DMAR_1CH_CMP:
|
||||
description: DMA address for full transfer
|
||||
fields:
|
||||
- name: DMAB
|
||||
description: DMA register for burst accesses
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/DTR2_2CH_CMP:
|
||||
fieldset/DTR2_1CH_CMP:
|
||||
description: deadtime register 2
|
||||
fields:
|
||||
- name: DTGF
|
||||
@ -734,6 +832,21 @@ fieldset/EGR_1CH:
|
||||
array:
|
||||
len: 1
|
||||
stride: 1
|
||||
fieldset/EGR_1CH_CMP:
|
||||
extends: EGR_1CH
|
||||
description: event generation register
|
||||
fields:
|
||||
- name: COMG
|
||||
description: Capture/Compare control update generation
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: BG
|
||||
description: Break x (x=1) generation
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 1
|
||||
stride: 1
|
||||
fieldset/EGR_2CH:
|
||||
extends: EGR_1CH
|
||||
description: event generation register
|
||||
@ -749,21 +862,6 @@ fieldset/EGR_2CH:
|
||||
description: Trigger generation
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
fieldset/EGR_2CH_CMP:
|
||||
extends: EGR_2CH
|
||||
description: event generation register
|
||||
fields:
|
||||
- name: COMG
|
||||
description: Capture/Compare control update generation
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: BG
|
||||
description: Break x (x=1) generation
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 1
|
||||
stride: 1
|
||||
fieldset/PSC_1CH:
|
||||
description: prescaler
|
||||
fields:
|
||||
@ -771,7 +869,7 @@ fieldset/PSC_1CH:
|
||||
description: Prescaler value
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/RCR_2CH_CMP:
|
||||
fieldset/RCR_1CH_CMP:
|
||||
description: repetition counter register
|
||||
fields:
|
||||
- name: REP
|
||||
@ -825,6 +923,21 @@ fieldset/SR_1CH:
|
||||
array:
|
||||
len: 1
|
||||
stride: 1
|
||||
fieldset/SR_1CH_CMP:
|
||||
extends: SR_1CH
|
||||
description: status register
|
||||
fields:
|
||||
- name: COMIF
|
||||
description: COM interrupt flag
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: BIF
|
||||
description: Break x (x=1) interrupt flag
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 1
|
||||
stride: 1
|
||||
fieldset/SR_2CH:
|
||||
extends: SR_1CH
|
||||
description: status register
|
||||
@ -847,21 +960,6 @@ fieldset/SR_2CH:
|
||||
array:
|
||||
len: 2
|
||||
stride: 1
|
||||
fieldset/SR_2CH_CMP:
|
||||
extends: SR_2CH
|
||||
description: status register
|
||||
fields:
|
||||
- name: COMIF
|
||||
description: COM interrupt flag
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: BIF
|
||||
description: Break x (x=1) interrupt flag
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 1
|
||||
stride: 1
|
||||
fieldset/TISEL_1CH:
|
||||
description: input selection register
|
||||
fields:
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user