diff --git a/data/registers/spi_v2.yaml b/data/registers/spi_v2.yaml
index 89b8fc2..f309658 100644
--- a/data/registers/spi_v2.yaml
+++ b/data/registers/spi_v2.yaml
@@ -1,6 +1,6 @@
 ---
-block/SPI:
-  description: Serial peripheral interface/Inter-IC sound
+block/SPI1:
+  description: Serial peripheral interface
   items:
     - name: CR1
       description: control register 1
@@ -81,6 +81,7 @@ fieldset/CR1:
       description: CRC length
       bit_offset: 11
       bit_size: 1
+      enum: CRCL
     - name: CRCNEXT
       description: CRC transfer next
       bit_offset: 12
@@ -123,6 +124,7 @@ fieldset/CR2:
       description: Frame format
       bit_offset: 4
       bit_size: 1
+      enum: FRF
     - name: ERRIE
       description: Error interrupt enable
       bit_offset: 5
@@ -139,18 +141,22 @@ fieldset/CR2:
       description: Data size
       bit_offset: 8
       bit_size: 4
+      enum: DS
     - name: FRXTH
       description: FIFO reception threshold
       bit_offset: 12
       bit_size: 1
+      enum: FRXTH
     - name: LDMA_RX
       description: Last DMA transfer for reception
       bit_offset: 13
       bit_size: 1
+      enum: LDMA_RX
     - name: LDMA_TX
       description: Last DMA transfer for transmission
       bit_offset: 14
       bit_size: 1
+      enum: LDMA_TX
 fieldset/CRCPR:
   description: CRC polynomial register
   fields:
@@ -199,19 +205,21 @@ fieldset/SR:
       description: Busy flag
       bit_offset: 7
       bit_size: 1
-      enum_read: BSYR
     - name: FRE
       description: Frame format error
       bit_offset: 8
       bit_size: 1
+      enum_read: FRER
     - name: FRLVL
       description: FIFO reception level
       bit_offset: 9
       bit_size: 2
+      enum_read: FRLVLR
     - name: FTLVL
-      description: FIFO transmission level
+      description: FIFO Transmission Level
       bit_offset: 11
       bit_size: 2
+      enum_read: FTLVLR
 fieldset/TXCRCR:
   description: TX CRC register
   fields:
@@ -264,15 +272,6 @@ enum/BR:
     - name: Div256
       description: f_PCLK / 256
       value: 7
-enum/BSYR:
-  bit_size: 1
-  variants:
-    - name: NotBusy
-      description: SPI not busy
-      value: 0
-    - name: Busy
-      description: SPI busy
-      value: 1
 enum/CPHA:
   bit_size: 1
   variants:
@@ -291,6 +290,15 @@ enum/CPOL:
     - name: IdleHigh
       description: CK to 1 when idle
       value: 1
+enum/CRCL:
+  bit_size: 1
+  variants:
+    - name: EightBit
+      description: 8-bit CRC length
+      value: 0
+    - name: SixteenBit
+      description: 16-bit CRC length
+      value: 1
 enum/CRCNEXT:
   bit_size: 1
   variants:
@@ -300,6 +308,123 @@ enum/CRCNEXT:
     - name: CRC
       description: Next transmit value is from Tx CRC register
       value: 1
+enum/DS:
+  bit_size: 4
+  variants:
+    - name: FourBit
+      description: 4-bit
+      value: 3
+    - name: FiveBit
+      description: 5-bit
+      value: 4
+    - name: SixBit
+      description: 6-bit
+      value: 5
+    - name: SevenBit
+      description: 7-bit
+      value: 6
+    - name: EightBit
+      description: 8-bit
+      value: 7
+    - name: NineBit
+      description: 9-bit
+      value: 8
+    - name: TenBit
+      description: 10-bit
+      value: 9
+    - name: ElevenBit
+      description: 11-bit
+      value: 10
+    - name: TwelveBit
+      description: 12-bit
+      value: 11
+    - name: ThirteenBit
+      description: 13-bit
+      value: 12
+    - name: FourteenBit
+      description: 14-bit
+      value: 13
+    - name: FifteenBit
+      description: 15-bit
+      value: 14
+    - name: SixteenBit
+      description: 16-bit
+      value: 15
+enum/FRER:
+  bit_size: 1
+  variants:
+    - name: NoError
+      description: No frame format error
+      value: 0
+    - name: Error
+      description: A frame format error occurred
+      value: 1
+enum/FRF:
+  bit_size: 1
+  variants:
+    - name: Motorola
+      description: SPI Motorola mode
+      value: 0
+    - name: TI
+      description: SPI TI mode
+      value: 1
+enum/FRLVLR:
+  bit_size: 2
+  variants:
+    - name: Empty
+      description: Rx FIFO Empty
+      value: 0
+    - name: Quarter
+      description: Rx 1/4 FIFO
+      value: 1
+    - name: Half
+      description: Rx 1/2 FIFO
+      value: 2
+    - name: Full
+      description: Rx FIFO full
+      value: 3
+enum/FRXTH:
+  bit_size: 1
+  variants:
+    - name: Half
+      description: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
+      value: 0
+    - name: Quarter
+      description: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
+      value: 1
+enum/FTLVLR:
+  bit_size: 2
+  variants:
+    - name: Empty
+      description: Tx FIFO Empty
+      value: 0
+    - name: Quarter
+      description: Tx 1/4 FIFO
+      value: 1
+    - name: Half
+      description: Tx 1/2 FIFO
+      value: 2
+    - name: Full
+      description: Tx FIFO full
+      value: 3
+enum/LDMA_RX:
+  bit_size: 1
+  variants:
+    - name: Even
+      description: Number of data to transfer for receive is even
+      value: 0
+    - name: Odd
+      description: Number of data to transfer for receive is odd
+      value: 1
+enum/LDMA_TX:
+  bit_size: 1
+  variants:
+    - name: Even
+      description: Number of data to transfer for transmit is even
+      value: 0
+    - name: Odd
+      description: Number of data to transfer for transmit is odd
+      value: 1
 enum/LSBFIRST:
   bit_size: 1
   variants: