stm32g0: add registers for FLASH
This commit is contained in:
Matthew W. Samsonoff
parent
57903f105d
commit
1a4706a799
454
data/registers/flash_g0.yaml
Normal file
454
data/registers/flash_g0.yaml
Normal file
@ -0,0 +1,454 @@
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---
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block/FLASH:
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description: Flash
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items:
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- name: ACR
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description: Access control register
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byte_offset: 0
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fieldset: ACR
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- name: KEYR
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description: Flash key register
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byte_offset: 8
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access: Write
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fieldset: KEYR
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- name: OPTKEYR
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description: Option byte key register
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byte_offset: 12
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access: Write
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fieldset: OPTKEYR
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- name: SR
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description: Status register
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byte_offset: 16
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fieldset: SR
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- name: CR
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description: Flash control register
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byte_offset: 20
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fieldset: CR
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- name: ECCR
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description: Flash ECC register
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byte_offset: 24
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fieldset: ECCR
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- name: OPTR
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description: Flash option register
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byte_offset: 32
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fieldset: OPTR
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- name: PCROP1ASR
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description: Flash PCROP zone A Start address register
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byte_offset: 36
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access: Read
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fieldset: PCROP1ASR
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- name: PCROP1AER
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description: Flash PCROP zone A End address register
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byte_offset: 40
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access: Read
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fieldset: PCROP1AER
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- name: WRP1AR
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description: Flash WRP area A address register
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byte_offset: 44
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access: Read
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fieldset: WRP1AR
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- name: WRP1BR
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description: Flash WRP area B address register
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byte_offset: 48
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access: Read
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fieldset: WRP1BR
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- name: PCROP1BSR
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description: Flash PCROP zone B Start address register
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byte_offset: 52
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access: Read
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fieldset: PCROP1BSR
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- name: PCROP1BER
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description: Flash PCROP zone B End address register
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byte_offset: 56
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access: Read
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fieldset: PCROP1BER
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- name: SECR
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description: Flash Security register
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byte_offset: 128
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access: Read
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fieldset: SECR
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fieldset/ACR:
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description: Access control register
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fields:
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- name: LATENCY
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description: Latency
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bit_offset: 0
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bit_size: 3
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enum: LATENCY
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- name: PRFTEN
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description: Prefetch enable
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bit_offset: 8
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bit_size: 1
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- name: ICEN
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description: Instruction cache enable
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bit_offset: 9
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bit_size: 1
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- name: ICRST
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description: Instruction cache reset
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bit_offset: 11
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bit_size: 1
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- name: EMPTY
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description: Flash User area empty
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bit_offset: 16
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bit_size: 1
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- name: DBG_SWEN
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description: Debug access software enable
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bit_offset: 18
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bit_size: 1
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fieldset/CR:
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description: Flash control register
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fields:
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- name: PG
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description: Programming
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bit_offset: 0
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bit_size: 1
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- name: PER
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description: Page erase
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bit_offset: 1
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bit_size: 1
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- name: MER
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description: Mass erase
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bit_offset: 2
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bit_size: 1
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- name: PNB
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description: Page number
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bit_offset: 3
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bit_size: 6
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- name: STRT
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description: Start
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bit_offset: 16
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bit_size: 1
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- name: OPTSTRT
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description: Options modification start
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bit_offset: 17
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bit_size: 1
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- name: FSTPG
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description: Fast programming
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bit_offset: 18
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bit_size: 1
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- name: EOPIE
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description: End of operation interrupt enable
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bit_offset: 24
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bit_size: 1
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- name: ERRIE
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description: Error interrupt enable
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bit_offset: 25
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bit_size: 1
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- name: RDERRIE
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description: PCROP read error interrupt enable
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bit_offset: 26
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bit_size: 1
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- name: OBL_LAUNCH
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description: Force the option byte loading
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bit_offset: 27
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bit_size: 1
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- name: SEC_PROT
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description: Securable memory area protection enable
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bit_offset: 28
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bit_size: 1
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- name: OPTLOCK
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description: Options Lock
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bit_offset: 30
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bit_size: 1
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- name: LOCK
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description: FLASH_CR Lock
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bit_offset: 31
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bit_size: 1
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fieldset/ECCR:
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description: Flash ECC register
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fields:
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- name: ADDR_ECC
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description: ECC fail address
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bit_offset: 0
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bit_size: 14
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- name: SYSF_ECC
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description: ECC fail for Corrected ECC Error or Double ECC Error in info block
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bit_offset: 20
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bit_size: 1
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- name: ECCIE
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description: ECC correction interrupt enable
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bit_offset: 24
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bit_size: 1
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- name: ECCC
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description: ECC correction
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bit_offset: 30
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bit_size: 1
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- name: ECCD
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description: ECC detection
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bit_offset: 31
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bit_size: 1
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fieldset/KEYR:
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description: Flash key register
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fields:
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- name: KEYR
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description: KEYR
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bit_offset: 0
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bit_size: 32
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fieldset/OPTKEYR:
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description: Option byte key register
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fields:
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- name: OPTKEYR
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description: Option byte key
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bit_offset: 0
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bit_size: 32
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fieldset/OPTR:
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description: Flash option register
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fields:
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- name: RDP
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description: Read protection level
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bit_offset: 0
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bit_size: 8
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enum: RDP
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- name: BOREN
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description: BOR reset Level
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bit_offset: 8
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bit_size: 1
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- name: BORF_LEV
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description: These bits contain the VDD supply level threshold that activates the reset
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bit_offset: 9
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bit_size: 2
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enum: BORF_LEV
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- name: BORR_LEV
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description: These bits contain the VDD supply level threshold that releases the reset.
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bit_offset: 11
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bit_size: 2
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enum: BORR_LEV
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- name: nRST_STOP
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description: nRST_STOP
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bit_offset: 13
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bit_size: 1
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- name: nRST_STDBY
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description: nRST_STDBY
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bit_offset: 14
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bit_size: 1
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- name: nRSTS_HDW
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description: nRSTS_HDW
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bit_offset: 15
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bit_size: 1
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- name: IDWG_SW
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description: Independent watchdog selection
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bit_offset: 16
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bit_size: 1
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- name: IWDG_STOP
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description: Independent watchdog counter freeze in Stop mode
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bit_offset: 17
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bit_size: 1
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- name: IWDG_STDBY
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description: Independent watchdog counter freeze in Standby mode
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bit_offset: 18
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bit_size: 1
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- name: WWDG_SW
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description: Window watchdog selection
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bit_offset: 19
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bit_size: 1
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- name: RAM_PARITY_CHECK
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description: SRAM parity check control
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bit_offset: 22
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bit_size: 1
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- name: nBOOT_SEL
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description: nBOOT_SEL
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bit_offset: 24
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bit_size: 1
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- name: nBOOT1
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description: Boot configuration
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bit_offset: 25
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bit_size: 1
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- name: nBOOT0
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description: nBOOT0 option bit
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bit_offset: 26
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bit_size: 1
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- name: NRST_MODE
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description: NRST_MODE
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bit_offset: 27
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bit_size: 2
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enum: NRST_MODE
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- name: IRHEN
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description: Internal reset holder enable bit
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bit_offset: 29
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bit_size: 1
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fieldset/PCROP1AER:
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description: Flash PCROP zone A End address register
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fields:
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- name: PCROP1A_END
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description: PCROP1A area end offset
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bit_offset: 0
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bit_size: 8
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- name: PCROP_RDP
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description: PCROP area preserved when RDP level decreased
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bit_offset: 31
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bit_size: 1
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fieldset/PCROP1ASR:
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description: Flash PCROP zone A Start address register
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fields:
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- name: PCROP1A_STRT
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description: PCROP1A area start offset
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bit_offset: 0
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bit_size: 8
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fieldset/PCROP1BER:
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description: Flash PCROP zone B End address register
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fields:
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- name: PCROP1B_END
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description: PCROP1B area end offset
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bit_offset: 0
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bit_size: 8
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fieldset/PCROP1BSR:
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description: Flash PCROP zone B Start address register
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fields:
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- name: PCROP1B_STRT
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description: PCROP1B area start offset
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bit_offset: 0
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bit_size: 8
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fieldset/SECR:
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description: Flash Security register
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fields:
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- name: SEC_SIZE
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description: Securable memory area size
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bit_offset: 0
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bit_size: 7
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- name: BOOT_LOCK
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description: used to force boot from user area
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bit_offset: 16
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bit_size: 1
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fieldset/SR:
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description: Status register
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fields:
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- name: EOP
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description: End of operation
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bit_offset: 0
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bit_size: 1
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- name: OPERR
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description: Operation error
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bit_offset: 1
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bit_size: 1
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- name: PROGERR
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description: Programming error
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bit_offset: 3
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bit_size: 1
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- name: WRPERR
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description: Write protected error
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bit_offset: 4
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bit_size: 1
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- name: PGAERR
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description: Programming alignment error
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bit_offset: 5
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bit_size: 1
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- name: SIZERR
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description: Size error
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bit_offset: 6
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bit_size: 1
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- name: PGSERR
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description: Programming sequence error
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bit_offset: 7
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bit_size: 1
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- name: MISERR
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description: Fast programming data miss error
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bit_offset: 8
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bit_size: 1
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- name: FASTERR
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description: Fast programming error
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bit_offset: 9
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bit_size: 1
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- name: RDERR
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description: PCROP read error
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bit_offset: 14
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bit_size: 1
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- name: OPTVERR
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description: Option and Engineering bits loading validity error
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bit_offset: 15
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bit_size: 1
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- name: BSY
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description: Busy
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bit_offset: 16
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bit_size: 1
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- name: CFGBSY
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description: Programming or erase configuration busy.
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bit_offset: 18
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bit_size: 1
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fieldset/WRP1AR:
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description: Flash WRP area A address register
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fields:
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- name: WRP1A_STRT
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description: WRP area A start offset
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bit_offset: 0
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bit_size: 6
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- name: WRP1A_END
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description: WRP area A end offset
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bit_offset: 16
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bit_size: 6
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fieldset/WRP1BR:
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description: Flash WRP area B address register
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fields:
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- name: WRP1B_STRT
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description: WRP area B start offset
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bit_offset: 0
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bit_size: 6
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- name: WRP1B_END
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description: WRP area B end offset
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bit_offset: 16
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bit_size: 6
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enum/LATENCY:
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bit_size: 3
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variants:
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- name: WS0
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description: Zero wait states
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value: 0b000
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- name: WS1
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description: One wait state
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value: 0b001
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- name: WS2
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description: Two wait states
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values: 0b010
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enum/NRST_MODE:
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bit_size: 2
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variants:
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- name: INPUT_ONLY
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description: Reset pin is in reset input mode only
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value: 0b01
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- name: GPIO
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description: Reset pin is in GPIO mode only
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value: 0b10
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- name: INPUT_OUTPUT
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description: Reset pin is in resety input and output mode
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value: 0b11
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enum/BORR_LEV:
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bit_size: 2
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variants:
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- name: RISING_0
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description: BOR rising level 1 with threshold around 2.1V
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value: 0b00
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- name: RISING_1
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description: BOR rising level 2 with threshold around 2.3V
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value: 0b01
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- name: RISING_2
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description: BOR rising level 3 with threshold around 2.6V
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value: 0b10
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- name: RISING_3
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description: BOR rising level 4 with threshold around 2.9V
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value: 0b11
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enum/BORF_LEV:
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bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: FALLING_0
|
||||||
|
description: BOR falling level 1 with threshold around 2.0V
|
||||||
|
value: 0b00
|
||||||
|
- name: FALLING_1
|
||||||
|
description: BOR falling level 2 with threshold around 2.2V
|
||||||
|
value: 0b01
|
||||||
|
- name: FALLING_2
|
||||||
|
description: BOR falling level 3 with threshold around 2.5V
|
||||||
|
value: 0b10
|
||||||
|
- name: FALLING_3
|
||||||
|
description: BOR falling level 4 with threshold around 2.8V
|
||||||
|
value: 0b11
|
||||||
|
enum/RDP:
|
||||||
|
bit_size: 8
|
||||||
|
variants:
|
||||||
|
- name: LEVEL_0
|
||||||
|
value: 0xAA
|
||||||
|
description: Read protection not active
|
||||||
|
- name: LEVEL_1
|
||||||
|
value: 0xBB
|
||||||
|
description: Memories read protection active
|
||||||
|
- name: LEVEL_2
|
||||||
|
value: 0xCC
|
||||||
|
description: Chip read protection active
|
||||||
@ -213,6 +213,7 @@ perimap = [
|
|||||||
('STM32L4.*:FLASH:.*', ('flash', 'l4', 'FLASH')),
|
('STM32L4.*:FLASH:.*', ('flash', 'l4', 'FLASH')),
|
||||||
('STM32U5.*:FLASH:.*', ('flash', 'u5', 'FLASH')),
|
('STM32U5.*:FLASH:.*', ('flash', 'u5', 'FLASH')),
|
||||||
('STM32WB.*:FLASH:.*', ('flash', 'wb55', 'FLASH')),
|
('STM32WB.*:FLASH:.*', ('flash', 'wb55', 'FLASH')),
|
||||||
|
('STM32G0.*:FLASH:.*', ('flash', 'g0', 'FLASH')),
|
||||||
('STM32F7.*:ETH:ETH:ethermac110_v2_0', ('eth', 'v1c', 'ETH')),
|
('STM32F7.*:ETH:ETH:ethermac110_v2_0', ('eth', 'v1c', 'ETH')),
|
||||||
('.*ETH:ethermac110_v3_0', ('eth', 'v2', 'ETH')),
|
('.*ETH:ethermac110_v3_0', ('eth', 'v2', 'ETH')),
|
||||||
|
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user