H7: Add FLASH and PWR
This commit is contained in:
Thales Fragoso
parent
2dda36bd49
commit
15bc0b7340
828
data/registers/flash_h7.yaml
Normal file
828
data/registers/flash_h7.yaml
Normal file
@ -0,0 +1,828 @@
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---
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block/BANK:
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description: "Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R"
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items:
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- name: KEYR
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description: FLASH key register for bank 1
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byte_offset: 0
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access: Write
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fieldset: KEYR
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- name: CR
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description: FLASH control register for bank 1
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byte_offset: 8
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fieldset: CR
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- name: SR
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description: FLASH status register for bank 1
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byte_offset: 12
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fieldset: SR
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- name: CCR
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description: FLASH clear control register for bank 1
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byte_offset: 16
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fieldset: CCR
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- name: PRAR_CUR
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description: FLASH protection address for bank 1
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byte_offset: 36
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access: Read
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fieldset: PRAR_CUR
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- name: PRAR_PRG
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description: FLASH protection address for bank 1
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byte_offset: 40
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fieldset: PRAR_PRG
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- name: SCAR_CUR
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description: FLASH secure address for bank 1
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byte_offset: 44
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fieldset: SCAR_CUR
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- name: SCAR_PRG
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description: FLASH secure address for bank 1
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byte_offset: 48
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fieldset: SCAR_PRG
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- name: WPSN_CURR
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description: FLASH write sector protection for bank 1
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byte_offset: 52
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access: Read
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fieldset: WPSN_CURR
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- name: WPSN_PRGR
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description: FLASH write sector protection for bank 1
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byte_offset: 56
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fieldset: WPSN_PRGR
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- name: CRCCR
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description: FLASH CRC control register for bank 1
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byte_offset: 76
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fieldset: CRCCR
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- name: CRCSADDR
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description: FLASH CRC start address register for bank 1
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byte_offset: 80
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fieldset: CRCSADDR
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- name: CRCEADDR
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description: FLASH CRC end address register for bank 1
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byte_offset: 84
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fieldset: CRCEADDR
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- name: FAR
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description: FLASH ECC fail address for bank 1
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byte_offset: 92
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access: Read
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fieldset: FAR
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block/FLASH:
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description: Flash
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items:
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- name: ACR
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description: Access control register
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byte_offset: 0
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fieldset: ACR
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- name: BANK
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description: "Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R"
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array:
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len: 2
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stride: 256
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byte_offset: 4
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block: BANK
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- name: OPTKEYR
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description: FLASH option key register
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byte_offset: 8
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fieldset: OPTKEYR
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- name: OPTCR
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description: FLASH option control register
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byte_offset: 24
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fieldset: OPTCR
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- name: OPTSR_CUR
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description: FLASH option status register
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byte_offset: 28
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fieldset: OPTSR_CUR
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- name: OPTSR_PRG
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description: FLASH option status register
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byte_offset: 32
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fieldset: OPTSR_PRG
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- name: OPTCCR
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description: FLASH option clear control register
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byte_offset: 36
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access: Write
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fieldset: OPTCCR
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- name: BOOT_CURR
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description: FLASH register with boot address
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byte_offset: 64
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access: Read
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fieldset: BOOT_CURR
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- name: BOOT_PRGR
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description: FLASH register with boot address
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byte_offset: 68
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fieldset: BOOT_PRGR
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- name: CRCDATAR
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description: FLASH CRC data register
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byte_offset: 92
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fieldset: CRCDATAR
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- name: ACR_
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description: Access control register
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byte_offset: 256
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fieldset: ACR_
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- name: OPTKEYR_
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description: FLASH option key register
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byte_offset: 264
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fieldset: OPTKEYR_
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- name: OPTCR_
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description: FLASH option control register
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byte_offset: 280
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fieldset: OPTCR_
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- name: OPTSR_CUR_
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description: FLASH option status register
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byte_offset: 284
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fieldset: OPTSR_CUR_
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- name: OPTSR_PRG_
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description: FLASH option status register
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byte_offset: 288
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fieldset: OPTSR_PRG_
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- name: OPTCCR_
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description: FLASH option clear control register
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byte_offset: 292
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access: Write
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fieldset: OPTCCR_
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fieldset/ACR:
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description: Access control register
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fields:
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- name: LATENCY
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description: Read latency
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bit_offset: 0
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bit_size: 3
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- name: WRHIGHFREQ
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description: Flash signal delay
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bit_offset: 4
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bit_size: 2
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fieldset/ACR_:
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description: Access control register
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fields:
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- name: LATENCY
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description: Read latency
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bit_offset: 0
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bit_size: 3
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- name: WRHIGHFREQ
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description: Flash signal delay
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bit_offset: 4
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bit_size: 2
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fieldset/BOOT_CURR:
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description: FLASH register with boot address
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fields:
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- name: BOOT_ADD0
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description: Boot address 0
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bit_offset: 0
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bit_size: 16
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- name: BOOT_ADD1
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description: Boot address 1
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bit_offset: 16
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bit_size: 16
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fieldset/BOOT_PRGR:
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description: FLASH register with boot address
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fields:
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- name: BOOT_ADD0
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description: Boot address 0
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bit_offset: 0
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bit_size: 16
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- name: BOOT_ADD1
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description: Boot address 1
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bit_offset: 16
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bit_size: 16
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fieldset/CCR:
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description: FLASH clear control register for bank 1
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fields:
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- name: CLR_EOP
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description: Bank 1 EOP1 flag clear bit
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bit_offset: 16
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bit_size: 1
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- name: CLR_WRPERR
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description: Bank 1 WRPERR1 flag clear bit
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bit_offset: 17
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bit_size: 1
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- name: CLR_PGSERR
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description: Bank 1 PGSERR1 flag clear bi
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bit_offset: 18
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bit_size: 1
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- name: CLR_STRBERR
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description: Bank 1 STRBERR1 flag clear bit
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bit_offset: 19
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bit_size: 1
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- name: CLR_INCERR
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description: Bank 1 INCERR1 flag clear bit
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bit_offset: 21
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bit_size: 1
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- name: CLR_OPERR
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description: Bank 1 OPERR1 flag clear bit
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bit_offset: 22
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bit_size: 1
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- name: CLR_RDPERR
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description: Bank 1 RDPERR1 flag clear bit
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bit_offset: 23
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bit_size: 1
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- name: CLR_RDSERR
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description: Bank 1 RDSERR1 flag clear bit
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bit_offset: 24
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bit_size: 1
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- name: CLR_SNECCERR
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description: Bank 1 SNECCERR1 flag clear bit
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bit_offset: 25
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bit_size: 1
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- name: CLR_DBECCERR
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description: Bank 1 DBECCERR1 flag clear bit
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bit_offset: 26
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bit_size: 1
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- name: CLR_CRCEND
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description: Bank 1 CRCEND1 flag clear bit
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bit_offset: 27
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bit_size: 1
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fieldset/CR:
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description: FLASH control register for bank 1
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fields:
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- name: LOCK
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description: Bank 1 configuration lock bit
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bit_offset: 0
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bit_size: 1
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- name: PG
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description: Bank 1 program enable bit
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bit_offset: 1
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bit_size: 1
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- name: SER
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description: Bank 1 sector erase request
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bit_offset: 2
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bit_size: 1
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- name: BER
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description: Bank 1 erase request
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bit_offset: 3
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bit_size: 1
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- name: PSIZE
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description: Bank 1 program size
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bit_offset: 4
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bit_size: 2
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- name: FW
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description: Bank 1 write forcing control bit
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bit_offset: 6
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bit_size: 1
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- name: START
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description: Bank 1 bank or sector erase start control bit
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bit_offset: 7
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bit_size: 1
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- name: SNB
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description: Bank 1 sector erase selection number
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bit_offset: 8
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bit_size: 3
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- name: CRC_EN
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description: Bank 1 CRC control bit
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bit_offset: 15
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bit_size: 1
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- name: EOPIE
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description: Bank 1 end-of-program interrupt control bit
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bit_offset: 16
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bit_size: 1
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- name: WRPERRIE
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description: Bank 1 write protection error interrupt enable bit
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bit_offset: 17
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bit_size: 1
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- name: PGSERRIE
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description: Bank 1 programming sequence error interrupt enable bit
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bit_offset: 18
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bit_size: 1
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- name: STRBERRIE
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description: Bank 1 strobe error interrupt enable bit
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bit_offset: 19
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bit_size: 1
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- name: INCERRIE
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description: Bank 1 inconsistency error interrupt enable bit
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bit_offset: 21
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bit_size: 1
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- name: OPERRIE
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description: Bank 1 write/erase error interrupt enable bit
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bit_offset: 22
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bit_size: 1
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- name: RDPERRIE
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description: Bank 1 read protection error interrupt enable bit
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bit_offset: 23
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bit_size: 1
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- name: RDSERRIE
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description: Bank 1 secure error interrupt enable bit
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bit_offset: 24
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bit_size: 1
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- name: SNECCERRIE
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description: Bank 1 ECC single correction error interrupt enable bit
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bit_offset: 25
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bit_size: 1
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- name: DBECCERRIE
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description: Bank 1 ECC double detection error interrupt enable bit
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bit_offset: 26
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bit_size: 1
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- name: CRCENDIE
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description: Bank 1 end of CRC calculation interrupt enable bit
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bit_offset: 27
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bit_size: 1
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fieldset/CRCCR:
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description: FLASH CRC control register for bank 1
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fields:
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- name: CRC_SECT
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description: Bank 1 CRC sector number
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bit_offset: 0
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bit_size: 3
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- name: ALL_BANK
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description: Bank 1 CRC select bit
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bit_offset: 7
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bit_size: 1
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- name: CRC_BY_SECT
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description: Bank 1 CRC sector mode select bit
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bit_offset: 8
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bit_size: 1
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- name: ADD_SECT
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description: Bank 1 CRC sector select bit
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bit_offset: 9
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bit_size: 1
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- name: CLEAN_SECT
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description: Bank 1 CRC sector list clear bit
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bit_offset: 10
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bit_size: 1
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- name: START_CRC
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description: Bank 1 CRC start bit
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bit_offset: 16
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bit_size: 1
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- name: CLEAN_CRC
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description: Bank 1 CRC clear bit
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bit_offset: 17
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bit_size: 1
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- name: CRC_BURST
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description: Bank 1 CRC burst size
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bit_offset: 20
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bit_size: 2
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fieldset/CRCDATAR:
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description: FLASH CRC data register
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fields:
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- name: CRC_DATA
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description: CRC result
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bit_offset: 0
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bit_size: 32
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fieldset/CRCEADDR:
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description: FLASH CRC end address register for bank 1
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fields:
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- name: CRC_END_ADDR
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description: CRC end address on bank 1
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bit_offset: 0
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bit_size: 32
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fieldset/CRCSADDR:
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description: FLASH CRC start address register for bank 1
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fields:
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- name: CRC_START_ADDR
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description: CRC start address on bank 1
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bit_offset: 0
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bit_size: 32
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fieldset/FAR:
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description: FLASH ECC fail address for bank 1
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fields:
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- name: FAIL_ECC_ADDR
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description: Bank 1 ECC error address
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bit_offset: 0
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bit_size: 15
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fieldset/KEYR:
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description: FLASH key register for bank 1
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fields:
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- name: KEYR
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description: Bank 1 access configuration unlock key
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bit_offset: 0
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bit_size: 32
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fieldset/OPTCCR:
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description: FLASH option clear control register
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fields:
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- name: CLR_OPTCHANGEERR
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description: OPTCHANGEERR reset bit
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bit_offset: 30
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bit_size: 1
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fieldset/OPTCCR_:
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description: FLASH option clear control register
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fields:
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- name: CLR_OPTCHANGEERR
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description: OPTCHANGEERR reset bit
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bit_offset: 30
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bit_size: 1
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fieldset/OPTCR:
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description: FLASH option control register
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fields:
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- name: OPTLOCK
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description: FLASH_OPTCR lock option configuration bit
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bit_offset: 0
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bit_size: 1
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- name: OPTSTART
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description: Option byte start change option configuration bit
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bit_offset: 1
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bit_size: 1
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- name: MER
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description: Flash mass erase enable bit
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bit_offset: 4
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bit_size: 1
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- name: OPTCHANGEERRIE
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description: Option byte change error interrupt enable bit
|
||||||
|
bit_offset: 30
|
||||||
|
bit_size: 1
|
||||||
|
- name: SWAP_BANK
|
||||||
|
description: Bank swapping configuration bit
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/OPTCR_:
|
||||||
|
description: FLASH option control register
|
||||||
|
fields:
|
||||||
|
- name: OPTLOCK
|
||||||
|
description: FLASH_OPTCR lock option configuration bit
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: OPTSTART
|
||||||
|
description: Option byte start change option configuration bit
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: MER
|
||||||
|
description: Flash mass erase enable bit
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
- name: OPTCHANGEERRIE
|
||||||
|
description: Option byte change error interrupt enable bit
|
||||||
|
bit_offset: 30
|
||||||
|
bit_size: 1
|
||||||
|
- name: SWAP_BANK
|
||||||
|
description: Bank swapping configuration bit
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/OPTKEYR:
|
||||||
|
description: FLASH option key register
|
||||||
|
fields:
|
||||||
|
- name: OPTKEYR
|
||||||
|
description: Unlock key option bytes
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/OPTKEYR_:
|
||||||
|
description: FLASH option key register
|
||||||
|
fields:
|
||||||
|
- name: OPTKEYR
|
||||||
|
description: Unlock key option bytes
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/OPTSR_CUR:
|
||||||
|
description: FLASH option status register
|
||||||
|
fields:
|
||||||
|
- name: OPT_BUSY
|
||||||
|
description: Option byte change ongoing flag
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: BOR_LEV
|
||||||
|
description: Brownout level option status bit
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 2
|
||||||
|
- name: IWDG1_HW
|
||||||
|
description: IWDG1 control option status bit
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
- name: nRST_STOP_D1
|
||||||
|
description: D1 DStop entry reset option status bit
|
||||||
|
bit_offset: 6
|
||||||
|
bit_size: 1
|
||||||
|
- name: nRST_STBY_D1
|
||||||
|
description: D1 DStandby entry reset option status bit
|
||||||
|
bit_offset: 7
|
||||||
|
bit_size: 1
|
||||||
|
- name: RDP
|
||||||
|
description: Readout protection level option status byte
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 8
|
||||||
|
- name: FZ_IWDG_STOP
|
||||||
|
description: IWDG Stop mode freeze option status bit
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
- name: FZ_IWDG_SDBY
|
||||||
|
description: IWDG Standby mode freeze option status bit
|
||||||
|
bit_offset: 18
|
||||||
|
bit_size: 1
|
||||||
|
- name: ST_RAM_SIZE
|
||||||
|
description: DTCM RAM size option status
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 2
|
||||||
|
- name: SECURITY
|
||||||
|
description: Security enable option status bit
|
||||||
|
bit_offset: 21
|
||||||
|
bit_size: 1
|
||||||
|
- name: RSS1
|
||||||
|
description: User option bit 1
|
||||||
|
bit_offset: 26
|
||||||
|
bit_size: 1
|
||||||
|
- name: PERSO_OK
|
||||||
|
description: Device personalization status bit
|
||||||
|
bit_offset: 28
|
||||||
|
bit_size: 1
|
||||||
|
- name: IO_HSLV
|
||||||
|
description: I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V)
|
||||||
|
bit_offset: 29
|
||||||
|
bit_size: 1
|
||||||
|
- name: OPTCHANGEERR
|
||||||
|
description: Option byte change error flag
|
||||||
|
bit_offset: 30
|
||||||
|
bit_size: 1
|
||||||
|
- name: SWAP_BANK_OPT
|
||||||
|
description: Bank swapping option status bit
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/OPTSR_CUR_:
|
||||||
|
description: FLASH option status register
|
||||||
|
fields:
|
||||||
|
- name: OPT_BUSY
|
||||||
|
description: Option byte change ongoing flag
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: BOR_LEV
|
||||||
|
description: Brownout level option status bit
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 2
|
||||||
|
- name: IWDG1_HW
|
||||||
|
description: IWDG1 control option status bit
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
- name: nRST_STOP_D1
|
||||||
|
description: D1 DStop entry reset option status bit
|
||||||
|
bit_offset: 6
|
||||||
|
bit_size: 1
|
||||||
|
- name: nRST_STBY_D1
|
||||||
|
description: D1 DStandby entry reset option status bit
|
||||||
|
bit_offset: 7
|
||||||
|
bit_size: 1
|
||||||
|
- name: RDP
|
||||||
|
description: Readout protection level option status byte
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 8
|
||||||
|
- name: FZ_IWDG_STOP
|
||||||
|
description: IWDG Stop mode freeze option status bit
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
- name: FZ_IWDG_SDBY
|
||||||
|
description: IWDG Standby mode freeze option status bit
|
||||||
|
bit_offset: 18
|
||||||
|
bit_size: 1
|
||||||
|
- name: ST_RAM_SIZE
|
||||||
|
description: DTCM RAM size option status
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 2
|
||||||
|
- name: SECURITY
|
||||||
|
description: Security enable option status bit
|
||||||
|
bit_offset: 21
|
||||||
|
bit_size: 1
|
||||||
|
- name: RSS1
|
||||||
|
description: User option bit 1
|
||||||
|
bit_offset: 26
|
||||||
|
bit_size: 1
|
||||||
|
- name: PERSO_OK
|
||||||
|
description: Device personalization status bit
|
||||||
|
bit_offset: 28
|
||||||
|
bit_size: 1
|
||||||
|
- name: IO_HSLV
|
||||||
|
description: I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V)
|
||||||
|
bit_offset: 29
|
||||||
|
bit_size: 1
|
||||||
|
- name: OPTCHANGEERR
|
||||||
|
description: Option byte change error flag
|
||||||
|
bit_offset: 30
|
||||||
|
bit_size: 1
|
||||||
|
- name: SWAP_BANK_OPT
|
||||||
|
description: Bank swapping option status bit
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/OPTSR_PRG:
|
||||||
|
description: FLASH option status register
|
||||||
|
fields:
|
||||||
|
- name: BOR_LEV
|
||||||
|
description: BOR reset level option configuration bits
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 2
|
||||||
|
- name: IWDG1_HW
|
||||||
|
description: IWDG1 option configuration bit
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
- name: nRST_STOP_D1
|
||||||
|
description: Option byte erase after D1 DStop option configuration bit
|
||||||
|
bit_offset: 6
|
||||||
|
bit_size: 1
|
||||||
|
- name: nRST_STBY_D1
|
||||||
|
description: Option byte erase after D1 DStandby option configuration bit
|
||||||
|
bit_offset: 7
|
||||||
|
bit_size: 1
|
||||||
|
- name: RDP
|
||||||
|
description: Readout protection level option configuration byte
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 8
|
||||||
|
- name: FZ_IWDG_STOP
|
||||||
|
description: IWDG Stop mode freeze option configuration bit
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
- name: FZ_IWDG_SDBY
|
||||||
|
description: IWDG Standby mode freeze option configuration bit
|
||||||
|
bit_offset: 18
|
||||||
|
bit_size: 1
|
||||||
|
- name: ST_RAM_SIZE
|
||||||
|
description: DTCM size select option configuration bits
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 2
|
||||||
|
- name: SECURITY
|
||||||
|
description: Security option configuration bit
|
||||||
|
bit_offset: 21
|
||||||
|
bit_size: 1
|
||||||
|
- name: RSS1
|
||||||
|
description: User option configuration bit 1
|
||||||
|
bit_offset: 26
|
||||||
|
bit_size: 1
|
||||||
|
- name: RSS2
|
||||||
|
description: User option configuration bit 2
|
||||||
|
bit_offset: 27
|
||||||
|
bit_size: 1
|
||||||
|
- name: IO_HSLV
|
||||||
|
description: I/O high-speed at low-voltage (PRODUCT_BELOW_25V)
|
||||||
|
bit_offset: 29
|
||||||
|
bit_size: 1
|
||||||
|
- name: SWAP_BANK_OPT
|
||||||
|
description: Bank swapping option configuration bit
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/OPTSR_PRG_:
|
||||||
|
description: FLASH option status register
|
||||||
|
fields:
|
||||||
|
- name: BOR_LEV
|
||||||
|
description: BOR reset level option configuration bits
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 2
|
||||||
|
- name: IWDG1_HW
|
||||||
|
description: IWDG1 option configuration bit
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
- name: nRST_STOP_D1
|
||||||
|
description: Option byte erase after D1 DStop option configuration bit
|
||||||
|
bit_offset: 6
|
||||||
|
bit_size: 1
|
||||||
|
- name: nRST_STBY_D1
|
||||||
|
description: Option byte erase after D1 DStandby option configuration bit
|
||||||
|
bit_offset: 7
|
||||||
|
bit_size: 1
|
||||||
|
- name: RDP
|
||||||
|
description: Readout protection level option configuration byte
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 8
|
||||||
|
- name: FZ_IWDG_STOP
|
||||||
|
description: IWDG Stop mode freeze option configuration bit
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
- name: FZ_IWDG_SDBY
|
||||||
|
description: IWDG Standby mode freeze option configuration bit
|
||||||
|
bit_offset: 18
|
||||||
|
bit_size: 1
|
||||||
|
- name: ST_RAM_SIZE
|
||||||
|
description: DTCM size select option configuration bits
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 2
|
||||||
|
- name: SECURITY
|
||||||
|
description: Security option configuration bit
|
||||||
|
bit_offset: 21
|
||||||
|
bit_size: 1
|
||||||
|
- name: RSS1
|
||||||
|
description: User option configuration bit 1
|
||||||
|
bit_offset: 26
|
||||||
|
bit_size: 1
|
||||||
|
- name: RSS2
|
||||||
|
description: User option configuration bit 2
|
||||||
|
bit_offset: 27
|
||||||
|
bit_size: 1
|
||||||
|
- name: IO_HSLV
|
||||||
|
description: I/O high-speed at low-voltage (PRODUCT_BELOW_25V)
|
||||||
|
bit_offset: 29
|
||||||
|
bit_size: 1
|
||||||
|
- name: SWAP_BANK_OPT
|
||||||
|
description: Bank swapping option configuration bit
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/PRAR_CUR:
|
||||||
|
description: FLASH protection address for bank 1
|
||||||
|
fields:
|
||||||
|
- name: PROT_AREA_START
|
||||||
|
description: Bank 1 lowest PCROP protected address
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 12
|
||||||
|
- name: PROT_AREA_END
|
||||||
|
description: Bank 1 highest PCROP protected address
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 12
|
||||||
|
- name: DMEP
|
||||||
|
description: Bank 1 PCROP protected erase enable option status bit
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/PRAR_PRG:
|
||||||
|
description: FLASH protection address for bank 1
|
||||||
|
fields:
|
||||||
|
- name: PROT_AREA_START
|
||||||
|
description: Bank 1 lowest PCROP protected address configuration
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 12
|
||||||
|
- name: PROT_AREA_END
|
||||||
|
description: Bank 1 highest PCROP protected address configuration
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 12
|
||||||
|
- name: DMEP
|
||||||
|
description: Bank 1 PCROP protected erase enable option configuration bit
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/SCAR_CUR:
|
||||||
|
description: FLASH secure address for bank 1
|
||||||
|
fields:
|
||||||
|
- name: SEC_AREA_START
|
||||||
|
description: Bank 1 lowest secure protected address
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 12
|
||||||
|
- name: SEC_AREA_END
|
||||||
|
description: Bank 1 highest secure protected address
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 12
|
||||||
|
- name: DMES
|
||||||
|
description: Bank 1 secure protected erase enable option status bit
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/SCAR_PRG:
|
||||||
|
description: FLASH secure address for bank 1
|
||||||
|
fields:
|
||||||
|
- name: SEC_AREA_START
|
||||||
|
description: Bank 1 lowest secure protected address configuration
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 12
|
||||||
|
- name: SEC_AREA_END
|
||||||
|
description: Bank 1 highest secure protected address configuration
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 12
|
||||||
|
- name: DMES
|
||||||
|
description: Bank 1 secure protected erase enable option configuration bit
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/SR:
|
||||||
|
description: FLASH status register for bank 1
|
||||||
|
fields:
|
||||||
|
- name: BSY
|
||||||
|
description: Bank 1 ongoing program flag
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: WBNE
|
||||||
|
description: Bank 1 write buffer not empty flag
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: QW
|
||||||
|
description: Bank 1 wait queue flag
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
- name: CRC_BUSY
|
||||||
|
description: Bank 1 CRC busy flag
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: EOP
|
||||||
|
description: Bank 1 end-of-program flag
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: WRPERR
|
||||||
|
description: Bank 1 write protection error flag
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
- name: PGSERR
|
||||||
|
description: Bank 1 programming sequence error flag
|
||||||
|
bit_offset: 18
|
||||||
|
bit_size: 1
|
||||||
|
- name: STRBERR
|
||||||
|
description: Bank 1 strobe error flag
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
- name: INCERR
|
||||||
|
description: Bank 1 inconsistency error flag
|
||||||
|
bit_offset: 21
|
||||||
|
bit_size: 1
|
||||||
|
- name: OPERR
|
||||||
|
description: Bank 1 write/erase error flag
|
||||||
|
bit_offset: 22
|
||||||
|
bit_size: 1
|
||||||
|
- name: RDPERR
|
||||||
|
description: Bank 1 read protection error flag
|
||||||
|
bit_offset: 23
|
||||||
|
bit_size: 1
|
||||||
|
- name: RDSERR
|
||||||
|
description: Bank 1 secure error flag
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 1
|
||||||
|
- name: SNECCERR1
|
||||||
|
description: Bank 1 single correction error flag
|
||||||
|
bit_offset: 25
|
||||||
|
bit_size: 1
|
||||||
|
- name: DBECCERR
|
||||||
|
description: Bank 1 ECC double detection error flag
|
||||||
|
bit_offset: 26
|
||||||
|
bit_size: 1
|
||||||
|
- name: CRCEND
|
||||||
|
description: Bank 1 CRC-complete flag
|
||||||
|
bit_offset: 27
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/WPSN_CURR:
|
||||||
|
description: FLASH write sector protection for bank 1
|
||||||
|
fields:
|
||||||
|
- name: WRPSn
|
||||||
|
description: Bank 1 sector write protection option status byte
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
|
fieldset/WPSN_PRGR:
|
||||||
|
description: FLASH write sector protection for bank 1
|
||||||
|
fields:
|
||||||
|
- name: WRPSn
|
||||||
|
description: Bank 1 sector write protection configuration byte
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
252
data/registers/pwr_h7.yaml
Normal file
252
data/registers/pwr_h7.yaml
Normal file
@ -0,0 +1,252 @@
|
|||||||
|
---
|
||||||
|
block/PWR:
|
||||||
|
description: PWR
|
||||||
|
items:
|
||||||
|
- name: CR1
|
||||||
|
description: PWR control register 1
|
||||||
|
byte_offset: 0
|
||||||
|
fieldset: CR1
|
||||||
|
- name: CSR1
|
||||||
|
description: PWR control status register 1
|
||||||
|
byte_offset: 4
|
||||||
|
access: Read
|
||||||
|
fieldset: CSR1
|
||||||
|
- name: CR2
|
||||||
|
description: "This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection."
|
||||||
|
byte_offset: 8
|
||||||
|
fieldset: CR2
|
||||||
|
- name: CR3
|
||||||
|
description: "Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value."
|
||||||
|
byte_offset: 12
|
||||||
|
fieldset: CR3
|
||||||
|
- name: CPUCR
|
||||||
|
description: This register allows controlling CPU1 power.
|
||||||
|
byte_offset: 16
|
||||||
|
fieldset: CPUCR
|
||||||
|
- name: D3CR
|
||||||
|
description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software
|
||||||
|
byte_offset: 24
|
||||||
|
fieldset: D3CR
|
||||||
|
- name: WKUPCR
|
||||||
|
description: "reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared)."
|
||||||
|
byte_offset: 32
|
||||||
|
fieldset: WKUPCR
|
||||||
|
- name: WKUPFR
|
||||||
|
description: "reset only by system reset, not reset by wakeup from Standby mode"
|
||||||
|
byte_offset: 36
|
||||||
|
fieldset: WKUPFR
|
||||||
|
- name: WKUPEPR
|
||||||
|
description: "Reset only by system reset, not reset by wakeup from Standby mode"
|
||||||
|
byte_offset: 40
|
||||||
|
fieldset: WKUPEPR
|
||||||
|
fieldset/CPUCR:
|
||||||
|
description: This register allows controlling CPU1 power.
|
||||||
|
fields:
|
||||||
|
- name: PDDS_D1
|
||||||
|
description: D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain.
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: PDDS_D2
|
||||||
|
description: D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain.
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: PDDS_D3
|
||||||
|
description: System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain.
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
- name: STOPF
|
||||||
|
description: STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit.
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
- name: SBF
|
||||||
|
description: System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit
|
||||||
|
bit_offset: 6
|
||||||
|
bit_size: 1
|
||||||
|
- name: SBF_D1
|
||||||
|
description: "D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode."
|
||||||
|
bit_offset: 7
|
||||||
|
bit_size: 1
|
||||||
|
- name: SBF_D2
|
||||||
|
description: "D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
- name: CSSF
|
||||||
|
description: "Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware."
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
- name: RUN_D3
|
||||||
|
description: Keep system D3 domain in Run mode regardless of the CPU sub-systems modes
|
||||||
|
bit_offset: 11
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/CR1:
|
||||||
|
description: PWR control register 1
|
||||||
|
fields:
|
||||||
|
- name: LPDS
|
||||||
|
description: "Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit)"
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: PVDE
|
||||||
|
description: Programmable voltage detector enable
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
- name: PLS
|
||||||
|
description: "Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details."
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 3
|
||||||
|
- name: DBP
|
||||||
|
description: "Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
- name: FLPS
|
||||||
|
description: "Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode."
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
- name: SVOS
|
||||||
|
description: "System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance."
|
||||||
|
bit_offset: 14
|
||||||
|
bit_size: 2
|
||||||
|
- name: AVDEN
|
||||||
|
description: Peripheral voltage monitor on VDDA enable
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: ALS
|
||||||
|
description: Analog voltage detector level selection These bits select the voltage threshold detected by the AVD.
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 2
|
||||||
|
fieldset/CR2:
|
||||||
|
description: "This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection."
|
||||||
|
fields:
|
||||||
|
- name: BREN
|
||||||
|
description: "Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: MONEN
|
||||||
|
description: "VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled."
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
- name: BRRDY
|
||||||
|
description: Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready.
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: VBATL
|
||||||
|
description: VBAT level monitoring versus low threshold
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 1
|
||||||
|
- name: VBATH
|
||||||
|
description: VBAT level monitoring versus high threshold
|
||||||
|
bit_offset: 21
|
||||||
|
bit_size: 1
|
||||||
|
- name: TEMPL
|
||||||
|
description: Temperature level monitoring versus low threshold
|
||||||
|
bit_offset: 22
|
||||||
|
bit_size: 1
|
||||||
|
- name: TEMPH
|
||||||
|
description: Temperature level monitoring versus high threshold
|
||||||
|
bit_offset: 23
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/CR3:
|
||||||
|
description: "Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value."
|
||||||
|
fields:
|
||||||
|
- name: BYPASS
|
||||||
|
description: Power management unit bypass
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: LDOEN
|
||||||
|
description: Low drop-out regulator enable
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: SCUEN
|
||||||
|
description: SD converter Enable
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
- name: VBE
|
||||||
|
description: VBAT charging enable
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
- name: VBRS
|
||||||
|
description: VBAT charging resistor selection
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
- name: USB33DEN
|
||||||
|
description: VDD33USB voltage level detector enable.
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 1
|
||||||
|
- name: USBREGEN
|
||||||
|
description: USB regulator enable.
|
||||||
|
bit_offset: 25
|
||||||
|
bit_size: 1
|
||||||
|
- name: USB33RDY
|
||||||
|
description: USB supply ready.
|
||||||
|
bit_offset: 26
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/CSR1:
|
||||||
|
description: PWR control status register 1
|
||||||
|
fields:
|
||||||
|
- name: PVDO
|
||||||
|
description: "Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set."
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
- name: ACTVOSRDY
|
||||||
|
description: Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3).
|
||||||
|
bit_offset: 13
|
||||||
|
bit_size: 1
|
||||||
|
- name: ACTVOS
|
||||||
|
description: VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU.
|
||||||
|
bit_offset: 14
|
||||||
|
bit_size: 2
|
||||||
|
- name: AVDO
|
||||||
|
description: "Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set."
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/D3CR:
|
||||||
|
description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software
|
||||||
|
fields:
|
||||||
|
- name: VOSRDY
|
||||||
|
description: VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3).
|
||||||
|
bit_offset: 13
|
||||||
|
bit_size: 1
|
||||||
|
- name: VOS
|
||||||
|
description: "Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling."
|
||||||
|
bit_offset: 14
|
||||||
|
bit_size: 2
|
||||||
|
fieldset/WKUPCR:
|
||||||
|
description: "reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared)."
|
||||||
|
fields:
|
||||||
|
- name: WKUPC
|
||||||
|
description: Clear Wakeup pin flag for WKUP. These bits are always read as 0.
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 6
|
||||||
|
fieldset/WKUPEPR:
|
||||||
|
description: "Reset only by system reset, not reset by wakeup from Standby mode"
|
||||||
|
fields:
|
||||||
|
- name: WKUPEN
|
||||||
|
description: "Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 6
|
||||||
|
stride: 1
|
||||||
|
- name: WKUPP
|
||||||
|
description: Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin.
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 6
|
||||||
|
stride: 1
|
||||||
|
- name: WKUPPUPD
|
||||||
|
description: Wakeup pin pull configuration
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 2
|
||||||
|
array:
|
||||||
|
len: 6
|
||||||
|
stride: 2
|
||||||
|
fieldset/WKUPFR:
|
||||||
|
description: "reset only by system reset, not reset by wakeup from Standby mode"
|
||||||
|
fields:
|
||||||
|
- name: WKUPF
|
||||||
|
description: Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR).
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 6
|
||||||
|
stride: 1
|
||||||
1
parse.py
1
parse.py
@ -241,6 +241,7 @@ perimap = [
|
|||||||
('STM32L0.*:RCC:.*', 'rcc_l0/RCC'),
|
('STM32L0.*:RCC:.*', 'rcc_l0/RCC'),
|
||||||
('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'),
|
('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'),
|
||||||
('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'),
|
('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'),
|
||||||
|
('.*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'),
|
||||||
]
|
]
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user