From 1595920962e1b7d20cea4f552a4fb73a823449bc Mon Sep 17 00:00:00 2001
From: xoviat <xoviat@users.noreply.github.com>
Date: Mon, 25 Sep 2023 19:26:46 -0500
Subject: [PATCH] rcc: pipe through sel mux

---
 stm32-data-gen/src/rcc.rs     | 21 +++++++++++++++++++++
 stm32-data-serde/src/lib.rs   |  8 ++++++++
 stm32-metapac-gen/src/data.rs |  2 ++
 3 files changed, 31 insertions(+)

diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs
index 7316c3d..cf81c4e 100644
--- a/stm32-data-gen/src/rcc.rs
+++ b/stm32-data-gen/src/rcc.rs
@@ -14,6 +14,24 @@ impl PeripheralToClock {
 
         for (rcc_name, ir) in &registers.registers {
             if let Some(rcc_name) = rcc_name.strip_prefix("rcc_") {
+                let mut family_muxes = HashMap::new();
+                for (reg, body) in &ir.fieldsets {
+                    let key = format!("fieldset/{reg}");
+                    if let Some(_) = regex!(r"^fieldset/CCIPR\d?$").captures(&key) {
+                        for field in &body.fields {
+                            if let Some(peri) = field.name.strip_suffix("SEL") {
+                                family_muxes.insert(
+                                    peri.to_string(),
+                                    stm32_data_serde::chip::core::peripheral::rcc::Mux {
+                                        register: reg.clone(),
+                                        field: field.name.clone(),
+                                    },
+                                );
+                            }
+                        }
+                    }
+                }
+
                 let mut family_clocks = HashMap::new();
                 for (reg, body) in &ir.fieldsets {
                     let key = format!("fieldset/{reg}");
@@ -49,6 +67,8 @@ impl PeripheralToClock {
                                     }
                                 }
 
+                                let mux = family_muxes.get(peri).map(|peri| peri.clone());
+
                                 let res = stm32_data_serde::chip::core::peripheral::Rcc {
                                     clock: peri_clock,
                                     enable: stm32_data_serde::chip::core::peripheral::rcc::Enable {
@@ -56,6 +76,7 @@ impl PeripheralToClock {
                                         field: field.name.clone(),
                                     },
                                     reset,
+                                    mux,
                                 };
 
                                 family_clocks.insert(peri.to_string(), res);
diff --git a/stm32-data-serde/src/lib.rs b/stm32-data-serde/src/lib.rs
index dd44b07..323f80a 100644
--- a/stm32-data-serde/src/lib.rs
+++ b/stm32-data-serde/src/lib.rs
@@ -103,6 +103,8 @@ pub mod chip {
                 pub enable: rcc::Enable,
                 #[serde(skip_serializing_if = "Option::is_none")]
                 pub reset: Option<rcc::Reset>,
+                #[serde(skip_serializing_if = "Option::is_none")]
+                pub mux: Option<rcc::Mux>,
             }
 
             pub mod rcc {
@@ -119,6 +121,12 @@ pub mod chip {
                     pub register: String,
                     pub field: String,
                 }
+
+                #[derive(Clone, Debug, Eq, PartialEq, Hash, PartialOrd, Ord, Serialize, Deserialize)]
+                pub struct Mux {
+                    pub register: String,
+                    pub field: String,
+                }
             }
 
             #[derive(Clone, Debug, Eq, PartialEq, Hash, PartialOrd, Ord, Serialize, Deserialize)]
diff --git a/stm32-metapac-gen/src/data.rs b/stm32-metapac-gen/src/data.rs
index 38e85d6..db6f972 100644
--- a/stm32-metapac-gen/src/data.rs
+++ b/stm32-metapac-gen/src/data.rs
@@ -85,6 +85,8 @@ pub struct PeripheralRcc {
     pub enable: Option<PeripheralRccRegister>,
     #[serde(default)]
     pub reset: Option<PeripheralRccRegister>,
+    #[serde(default)]
+    pub mux: Option<PeripheralRccRegister>,
 }
 
 #[derive(Debug, Eq, PartialEq, Clone, Deserialize)]